(Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
(Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
+(Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
+(Select1 <t> (Add64carry x y c)) =>
+ (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
+
// math package intrinsics
(Abs ...) => (ABSD ...)
(GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
(GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
+// SGT/SGTU with known outcomes.
+(SGT x x) => (MOVVconst [0])
+(SGTU x x) => (MOVVconst [0])
+
// fold readonly sym load
(MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read8(sym, int64(off)))])
(MOVHload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
v.AddArg(x)
return true
}
+ // match: (SGT x x)
+ // result: (MOVVconst [0])
+ for {
+ x := v_0
+ if x != v_1 {
+ break
+ }
+ v.reset(OpMIPS64MOVVconst)
+ v.AuxInt = int64ToAuxInt(0)
+ return true
+ }
return false
}
func rewriteValueMIPS64_OpMIPS64SGTU(v *Value) bool {
v.AddArg(x)
return true
}
+ // match: (SGTU x x)
+ // result: (MOVVconst [0])
+ for {
+ x := v_0
+ if x != v_1 {
+ break
+ }
+ v.reset(OpMIPS64MOVVconst)
+ v.AuxInt = int64ToAuxInt(0)
+ return true
+ }
return false
}
func rewriteValueMIPS64_OpMIPS64SGTUconst(v *Value) bool {
v.AddArg(v0)
return true
}
+ // match: (Select0 <t> (Add64carry x y c))
+ // result: (ADDV (ADDV <t> x y) c)
+ for {
+ t := v.Type
+ if v_0.Op != OpAdd64carry {
+ break
+ }
+ c := v_0.Args[2]
+ x := v_0.Args[0]
+ y := v_0.Args[1]
+ v.reset(OpMIPS64ADDV)
+ v0 := b.NewValue0(v.Pos, OpMIPS64ADDV, t)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, c)
+ return true
+ }
// match: (Select0 (DIVVU _ (MOVVconst [1])))
// result: (MOVVconst [0])
for {
v.AddArg2(v0, v2)
return true
}
+ // match: (Select1 <t> (Add64carry x y c))
+ // result: (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
+ for {
+ t := v.Type
+ if v_0.Op != OpAdd64carry {
+ break
+ }
+ c := v_0.Args[2]
+ x := v_0.Args[0]
+ y := v_0.Args[1]
+ v.reset(OpMIPS64OR)
+ v0 := b.NewValue0(v.Pos, OpMIPS64SGTU, t)
+ s := b.NewValue0(v.Pos, OpMIPS64ADDV, t)
+ s.AddArg2(x, y)
+ v0.AddArg2(x, s)
+ v2 := b.NewValue0(v.Pos, OpMIPS64SGTU, t)
+ v3 := b.NewValue0(v.Pos, OpMIPS64ADDV, t)
+ v3.AddArg2(s, c)
+ v2.AddArg2(s, v3)
+ v.AddArg2(v0, v2)
+ return true
+ }
// match: (Select1 (MULVU x (MOVVconst [-1])))
// result: (NEGV x)
for {
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
return s.newValue3(ssa.OpAdd64carry, types.NewTuple(types.Types[types.TUINT64], types.Types[types.TUINT64]), args[0], args[1], args[2])
},
- sys.AMD64, sys.ARM64, sys.PPC64, sys.S390X, sys.RISCV64, sys.Loong64)
+ sys.AMD64, sys.ARM64, sys.PPC64, sys.S390X, sys.RISCV64, sys.Loong64, sys.MIPS64)
alias("math/bits", "Add", "math/bits", "Add64", p8...)
addF("math/bits", "Sub64",
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
// loong64: "ADDV", "SGTU"
// ppc64x: "ADDC", "ADDE", "ADDZE"
// s390x:"ADDE","ADDC\t[$]-1,"
+ // mips64:"ADDV","SGTU"
// riscv64: "ADD","SLTU"
return bits.Add(x, 7, ci)
}
// loong64: "ADDV", "SGTU"
// ppc64x: "ADDC", -"ADDE", "ADDZE"
// s390x:"ADDC",-"ADDC\t[$]-1,"
+ // mips64:"ADDV","SGTU"
// riscv64: "ADD","SLTU"
return bits.Add(x, y, 0)
}
// loong64: "ADDV", -"SGTU"
// ppc64x: "ADDC", "ADDE", -"ADDZE"
// s390x:"ADDE","ADDC\t[$]-1,"
+ // mips64:"ADDV",-"SGTU"
// riscv64: "ADD",-"SLTU"
r, _ := bits.Add(x, y, ci)
return r
// loong64: "ADDV", "SGTU"
// ppc64x: "ADDC", "ADDE", "ADDZE"
// s390x:"ADDE","ADDC\t[$]-1,"
+ // mips64:"ADDV","SGTU"
// riscv64: "ADD","SLTU"
return bits.Add64(x, y, ci)
}
// loong64: "ADDV", "SGTU"
// ppc64x: "ADDC", "ADDE", "ADDZE"
// s390x:"ADDE","ADDC\t[$]-1,"
+ // mips64:"ADDV","SGTU"
// riscv64: "ADD","SLTU"
return bits.Add64(x, 7, ci)
}
// loong64: "ADDV", "SGTU"
// ppc64x: "ADDC", -"ADDE", "ADDZE"
// s390x:"ADDC",-"ADDC\t[$]-1,"
+ // mips64:"ADDV","SGTU"
// riscv64: "ADD","SLTU"
return bits.Add64(x, y, 0)
}
// loong64: "ADDV", -"SGTU"
// ppc64x: "ADDC", "ADDE", -"ADDZE"
// s390x:"ADDE","ADDC\t[$]-1,"
+ // mips64:"ADDV",-"SGTU"
// riscv64: "ADD",-"SLTU"
r, _ := bits.Add64(x, y, ci)
return r