src/cmd/compile/internal/ssa/opGen.go

   1 // Code generated from _gen/*Ops.go using 'go generate'; DO NOT EDIT.
   2
   3 package ssa
   4
   5 import (
   6         "cmd/internal/obj"
   7         "cmd/internal/obj/arm"
   8         "cmd/internal/obj/arm64"
   9         "cmd/internal/obj/loong64"
  10         "cmd/internal/obj/mips"
  11         "cmd/internal/obj/ppc64"
  12         "cmd/internal/obj/riscv"
  13         "cmd/internal/obj/s390x"
  14         "cmd/internal/obj/wasm"
  15         "cmd/internal/obj/x86"
  16 )
  17
  18 const (
  19         BlockInvalid BlockKind = iota
  20
  21         Block386EQ
  22         Block386NE
  23         Block386LT
  24         Block386LE
  25         Block386GT
  26         Block386GE
  27         Block386OS
  28         Block386OC
  29         Block386ULT
  30         Block386ULE
  31         Block386UGT
  32         Block386UGE
  33         Block386EQF
  34         Block386NEF
  35         Block386ORD
  36         Block386NAN
  37
  38         BlockAMD64EQ
  39         BlockAMD64NE
  40         BlockAMD64LT
  41         BlockAMD64LE
  42         BlockAMD64GT
  43         BlockAMD64GE
  44         BlockAMD64OS
  45         BlockAMD64OC
  46         BlockAMD64ULT
  47         BlockAMD64ULE
  48         BlockAMD64UGT
  49         BlockAMD64UGE
  50         BlockAMD64EQF
  51         BlockAMD64NEF
  52         BlockAMD64ORD
  53         BlockAMD64NAN
  54         BlockAMD64JUMPTABLE
  55
  56         BlockARMEQ
  57         BlockARMNE
  58         BlockARMLT
  59         BlockARMLE
  60         BlockARMGT
  61         BlockARMGE
  62         BlockARMULT
  63         BlockARMULE
  64         BlockARMUGT
  65         BlockARMUGE
  66         BlockARMLTnoov
  67         BlockARMLEnoov
  68         BlockARMGTnoov
  69         BlockARMGEnoov
  70
  71         BlockARM64EQ
  72         BlockARM64NE
  73         BlockARM64LT
  74         BlockARM64LE
  75         BlockARM64GT
  76         BlockARM64GE
  77         BlockARM64ULT
  78         BlockARM64ULE
  79         BlockARM64UGT
  80         BlockARM64UGE
  81         BlockARM64Z
  82         BlockARM64NZ
  83         BlockARM64ZW
  84         BlockARM64NZW
  85         BlockARM64TBZ
  86         BlockARM64TBNZ
  87         BlockARM64FLT
  88         BlockARM64FLE
  89         BlockARM64FGT
  90         BlockARM64FGE
  91         BlockARM64LTnoov
  92         BlockARM64LEnoov
  93         BlockARM64GTnoov
  94         BlockARM64GEnoov
  95         BlockARM64JUMPTABLE
  96
  97         BlockLOONG64EQ
  98         BlockLOONG64NE
  99         BlockLOONG64LTZ
 100         BlockLOONG64LEZ
 101         BlockLOONG64GTZ
 102         BlockLOONG64GEZ
 103         BlockLOONG64FPT
 104         BlockLOONG64FPF
 105
 106         BlockMIPSEQ
 107         BlockMIPSNE
 108         BlockMIPSLTZ
 109         BlockMIPSLEZ
 110         BlockMIPSGTZ
 111         BlockMIPSGEZ
 112         BlockMIPSFPT
 113         BlockMIPSFPF
 114
 115         BlockMIPS64EQ
 116         BlockMIPS64NE
 117         BlockMIPS64LTZ
 118         BlockMIPS64LEZ
 119         BlockMIPS64GTZ
 120         BlockMIPS64GEZ
 121         BlockMIPS64FPT
 122         BlockMIPS64FPF
 123
 124         BlockPPC64EQ
 125         BlockPPC64NE
 126         BlockPPC64LT
 127         BlockPPC64LE
 128         BlockPPC64GT
 129         BlockPPC64GE
 130         BlockPPC64FLT
 131         BlockPPC64FLE
 132         BlockPPC64FGT
 133         BlockPPC64FGE
 134
 135         BlockRISCV64BEQ
 136         BlockRISCV64BNE
 137         BlockRISCV64BLT
 138         BlockRISCV64BGE
 139         BlockRISCV64BLTU
 140         BlockRISCV64BGEU
 141         BlockRISCV64BEQZ
 142         BlockRISCV64BNEZ
 143         BlockRISCV64BLEZ
 144         BlockRISCV64BGEZ
 145         BlockRISCV64BLTZ
 146         BlockRISCV64BGTZ
 147
 148         BlockS390XBRC
 149         BlockS390XCRJ
 150         BlockS390XCGRJ
 151         BlockS390XCLRJ
 152         BlockS390XCLGRJ
 153         BlockS390XCIJ
 154         BlockS390XCGIJ
 155         BlockS390XCLIJ
 156         BlockS390XCLGIJ
 157
 158         BlockPlain
 159         BlockIf
 160         BlockDefer
 161         BlockRet
 162         BlockRetJmp
 163         BlockExit
 164         BlockJumpTable
 165         BlockFirst
 166 )
 167
 168 var blockString = [...]string{
 169         BlockInvalid: "BlockInvalid",
 170
 171         Block386EQ:  "EQ",
 172         Block386NE:  "NE",
 173         Block386LT:  "LT",
 174         Block386LE:  "LE",
 175         Block386GT:  "GT",
 176         Block386GE:  "GE",
 177         Block386OS:  "OS",
 178         Block386OC:  "OC",
 179         Block386ULT: "ULT",
 180         Block386ULE: "ULE",
 181         Block386UGT: "UGT",
 182         Block386UGE: "UGE",
 183         Block386EQF: "EQF",
 184         Block386NEF: "NEF",
 185         Block386ORD: "ORD",
 186         Block386NAN: "NAN",
 187
 188         BlockAMD64EQ:        "EQ",
 189         BlockAMD64NE:        "NE",
 190         BlockAMD64LT:        "LT",
 191         BlockAMD64LE:        "LE",
 192         BlockAMD64GT:        "GT",
 193         BlockAMD64GE:        "GE",
 194         BlockAMD64OS:        "OS",
 195         BlockAMD64OC:        "OC",
 196         BlockAMD64ULT:       "ULT",
 197         BlockAMD64ULE:       "ULE",
 198         BlockAMD64UGT:       "UGT",
 199         BlockAMD64UGE:       "UGE",
 200         BlockAMD64EQF:       "EQF",
 201         BlockAMD64NEF:       "NEF",
 202         BlockAMD64ORD:       "ORD",
 203         BlockAMD64NAN:       "NAN",
 204         BlockAMD64JUMPTABLE: "JUMPTABLE",
 205
 206         BlockARMEQ:     "EQ",
 207         BlockARMNE:     "NE",
 208         BlockARMLT:     "LT",
 209         BlockARMLE:     "LE",
 210         BlockARMGT:     "GT",
 211         BlockARMGE:     "GE",
 212         BlockARMULT:    "ULT",
 213         BlockARMULE:    "ULE",
 214         BlockARMUGT:    "UGT",
 215         BlockARMUGE:    "UGE",
 216         BlockARMLTnoov: "LTnoov",
 217         BlockARMLEnoov: "LEnoov",
 218         BlockARMGTnoov: "GTnoov",
 219         BlockARMGEnoov: "GEnoov",
 220
 221         BlockARM64EQ:        "EQ",
 222         BlockARM64NE:        "NE",
 223         BlockARM64LT:        "LT",
 224         BlockARM64LE:        "LE",
 225         BlockARM64GT:        "GT",
 226         BlockARM64GE:        "GE",
 227         BlockARM64ULT:       "ULT",
 228         BlockARM64ULE:       "ULE",
 229         BlockARM64UGT:       "UGT",
 230         BlockARM64UGE:       "UGE",
 231         BlockARM64Z:         "Z",
 232         BlockARM64NZ:        "NZ",
 233         BlockARM64ZW:        "ZW",
 234         BlockARM64NZW:       "NZW",
 235         BlockARM64TBZ:       "TBZ",
 236         BlockARM64TBNZ:      "TBNZ",
 237         BlockARM64FLT:       "FLT",
 238         BlockARM64FLE:       "FLE",
 239         BlockARM64FGT:       "FGT",
 240         BlockARM64FGE:       "FGE",
 241         BlockARM64LTnoov:    "LTnoov",
 242         BlockARM64LEnoov:    "LEnoov",
 243         BlockARM64GTnoov:    "GTnoov",
 244         BlockARM64GEnoov:    "GEnoov",
 245         BlockARM64JUMPTABLE: "JUMPTABLE",
 246
 247         BlockLOONG64EQ:  "EQ",
 248         BlockLOONG64NE:  "NE",
 249         BlockLOONG64LTZ: "LTZ",
 250         BlockLOONG64LEZ: "LEZ",
 251         BlockLOONG64GTZ: "GTZ",
 252         BlockLOONG64GEZ: "GEZ",
 253         BlockLOONG64FPT: "FPT",
 254         BlockLOONG64FPF: "FPF",
 255
 256         BlockMIPSEQ:  "EQ",
 257         BlockMIPSNE:  "NE",
 258         BlockMIPSLTZ: "LTZ",
 259         BlockMIPSLEZ: "LEZ",
 260         BlockMIPSGTZ: "GTZ",
 261         BlockMIPSGEZ: "GEZ",
 262         BlockMIPSFPT: "FPT",
 263         BlockMIPSFPF: "FPF",
 264
 265         BlockMIPS64EQ:  "EQ",
 266         BlockMIPS64NE:  "NE",
 267         BlockMIPS64LTZ: "LTZ",
 268         BlockMIPS64LEZ: "LEZ",
 269         BlockMIPS64GTZ: "GTZ",
 270         BlockMIPS64GEZ: "GEZ",
 271         BlockMIPS64FPT: "FPT",
 272         BlockMIPS64FPF: "FPF",
 273
 274         BlockPPC64EQ:  "EQ",
 275         BlockPPC64NE:  "NE",
 276         BlockPPC64LT:  "LT",
 277         BlockPPC64LE:  "LE",
 278         BlockPPC64GT:  "GT",
 279         BlockPPC64GE:  "GE",
 280         BlockPPC64FLT: "FLT",
 281         BlockPPC64FLE: "FLE",
 282         BlockPPC64FGT: "FGT",
 283         BlockPPC64FGE: "FGE",
 284
 285         BlockRISCV64BEQ:  "BEQ",
 286         BlockRISCV64BNE:  "BNE",
 287         BlockRISCV64BLT:  "BLT",
 288         BlockRISCV64BGE:  "BGE",
 289         BlockRISCV64BLTU: "BLTU",
 290         BlockRISCV64BGEU: "BGEU",
 291         BlockRISCV64BEQZ: "BEQZ",
 292         BlockRISCV64BNEZ: "BNEZ",
 293         BlockRISCV64BLEZ: "BLEZ",
 294         BlockRISCV64BGEZ: "BGEZ",
 295         BlockRISCV64BLTZ: "BLTZ",
 296         BlockRISCV64BGTZ: "BGTZ",
 297
 298         BlockS390XBRC:   "BRC",
 299         BlockS390XCRJ:   "CRJ",
 300         BlockS390XCGRJ:  "CGRJ",
 301         BlockS390XCLRJ:  "CLRJ",
 302         BlockS390XCLGRJ: "CLGRJ",
 303         BlockS390XCIJ:   "CIJ",
 304         BlockS390XCGIJ:  "CGIJ",
 305         BlockS390XCLIJ:  "CLIJ",
 306         BlockS390XCLGIJ: "CLGIJ",
 307
 308         BlockPlain:     "Plain",
 309         BlockIf:        "If",
 310         BlockDefer:     "Defer",
 311         BlockRet:       "Ret",
 312         BlockRetJmp:    "RetJmp",
 313         BlockExit:      "Exit",
 314         BlockJumpTable: "JumpTable",
 315         BlockFirst:     "First",
 316 }
 317
 318 func (k BlockKind) String() string { return blockString[k] }
 319 func (k BlockKind) AuxIntType() string {
 320         switch k {
 321         case BlockARM64TBZ:
 322                 return "int64"
 323         case BlockARM64TBNZ:
 324                 return "int64"
 325         case BlockS390XCIJ:
 326                 return "int8"
 327         case BlockS390XCGIJ:
 328                 return "int8"
 329         case BlockS390XCLIJ:
 330                 return "uint8"
 331         case BlockS390XCLGIJ:
 332                 return "uint8"
 333         }
 334         return ""
 335 }
 336
 337 const (
 338         OpInvalid Op = iota
 339
 340         Op386ADDSS
 341         Op386ADDSD
 342         Op386SUBSS
 343         Op386SUBSD
 344         Op386MULSS
 345         Op386MULSD
 346         Op386DIVSS
 347         Op386DIVSD
 348         Op386MOVSSload
 349         Op386MOVSDload
 350         Op386MOVSSconst
 351         Op386MOVSDconst
 352         Op386MOVSSloadidx1
 353         Op386MOVSSloadidx4
 354         Op386MOVSDloadidx1
 355         Op386MOVSDloadidx8
 356         Op386MOVSSstore
 357         Op386MOVSDstore
 358         Op386MOVSSstoreidx1
 359         Op386MOVSSstoreidx4
 360         Op386MOVSDstoreidx1
 361         Op386MOVSDstoreidx8
 362         Op386ADDSSload
 363         Op386ADDSDload
 364         Op386SUBSSload
 365         Op386SUBSDload
 366         Op386MULSSload
 367         Op386MULSDload
 368         Op386DIVSSload
 369         Op386DIVSDload
 370         Op386ADDL
 371         Op386ADDLconst
 372         Op386ADDLcarry
 373         Op386ADDLconstcarry
 374         Op386ADCL
 375         Op386ADCLconst
 376         Op386SUBL
 377         Op386SUBLconst
 378         Op386SUBLcarry
 379         Op386SUBLconstcarry
 380         Op386SBBL
 381         Op386SBBLconst
 382         Op386MULL
 383         Op386MULLconst
 384         Op386MULLU
 385         Op386HMULL
 386         Op386HMULLU
 387         Op386MULLQU
 388         Op386AVGLU
 389         Op386DIVL
 390         Op386DIVW
 391         Op386DIVLU
 392         Op386DIVWU
 393         Op386MODL
 394         Op386MODW
 395         Op386MODLU
 396         Op386MODWU
 397         Op386ANDL
 398         Op386ANDLconst
 399         Op386ORL
 400         Op386ORLconst
 401         Op386XORL
 402         Op386XORLconst
 403         Op386CMPL
 404         Op386CMPW
 405         Op386CMPB
 406         Op386CMPLconst
 407         Op386CMPWconst
 408         Op386CMPBconst
 409         Op386CMPLload
 410         Op386CMPWload
 411         Op386CMPBload
 412         Op386CMPLconstload
 413         Op386CMPWconstload
 414         Op386CMPBconstload
 415         Op386UCOMISS
 416         Op386UCOMISD
 417         Op386TESTL
 418         Op386TESTW
 419         Op386TESTB
 420         Op386TESTLconst
 421         Op386TESTWconst
 422         Op386TESTBconst
 423         Op386SHLL
 424         Op386SHLLconst
 425         Op386SHRL
 426         Op386SHRW
 427         Op386SHRB
 428         Op386SHRLconst
 429         Op386SHRWconst
 430         Op386SHRBconst
 431         Op386SARL
 432         Op386SARW
 433         Op386SARB
 434         Op386SARLconst
 435         Op386SARWconst
 436         Op386SARBconst
 437         Op386ROLL
 438         Op386ROLW
 439         Op386ROLB
 440         Op386ROLLconst
 441         Op386ROLWconst
 442         Op386ROLBconst
 443         Op386ADDLload
 444         Op386SUBLload
 445         Op386MULLload
 446         Op386ANDLload
 447         Op386ORLload
 448         Op386XORLload
 449         Op386ADDLloadidx4
 450         Op386SUBLloadidx4
 451         Op386MULLloadidx4
 452         Op386ANDLloadidx4
 453         Op386ORLloadidx4
 454         Op386XORLloadidx4
 455         Op386NEGL
 456         Op386NOTL
 457         Op386BSFL
 458         Op386BSFW
 459         Op386LoweredCtz32
 460         Op386BSRL
 461         Op386BSRW
 462         Op386BSWAPL
 463         Op386SQRTSD
 464         Op386SQRTSS
 465         Op386SBBLcarrymask
 466         Op386SETEQ
 467         Op386SETNE
 468         Op386SETL
 469         Op386SETLE
 470         Op386SETG
 471         Op386SETGE
 472         Op386SETB
 473         Op386SETBE
 474         Op386SETA
 475         Op386SETAE
 476         Op386SETO
 477         Op386SETEQF
 478         Op386SETNEF
 479         Op386SETORD
 480         Op386SETNAN
 481         Op386SETGF
 482         Op386SETGEF
 483         Op386MOVBLSX
 484         Op386MOVBLZX
 485         Op386MOVWLSX
 486         Op386MOVWLZX
 487         Op386MOVLconst
 488         Op386CVTTSD2SL
 489         Op386CVTTSS2SL
 490         Op386CVTSL2SS
 491         Op386CVTSL2SD
 492         Op386CVTSD2SS
 493         Op386CVTSS2SD
 494         Op386PXOR
 495         Op386LEAL
 496         Op386LEAL1
 497         Op386LEAL2
 498         Op386LEAL4
 499         Op386LEAL8
 500         Op386MOVBload
 501         Op386MOVBLSXload
 502         Op386MOVWload
 503         Op386MOVWLSXload
 504         Op386MOVLload
 505         Op386MOVBstore
 506         Op386MOVWstore
 507         Op386MOVLstore
 508         Op386ADDLmodify
 509         Op386SUBLmodify
 510         Op386ANDLmodify
 511         Op386ORLmodify
 512         Op386XORLmodify
 513         Op386ADDLmodifyidx4
 514         Op386SUBLmodifyidx4
 515         Op386ANDLmodifyidx4
 516         Op386ORLmodifyidx4
 517         Op386XORLmodifyidx4
 518         Op386ADDLconstmodify
 519         Op386ANDLconstmodify
 520         Op386ORLconstmodify
 521         Op386XORLconstmodify
 522         Op386ADDLconstmodifyidx4
 523         Op386ANDLconstmodifyidx4
 524         Op386ORLconstmodifyidx4
 525         Op386XORLconstmodifyidx4
 526         Op386MOVBloadidx1
 527         Op386MOVWloadidx1
 528         Op386MOVWloadidx2
 529         Op386MOVLloadidx1
 530         Op386MOVLloadidx4
 531         Op386MOVBstoreidx1
 532         Op386MOVWstoreidx1
 533         Op386MOVWstoreidx2
 534         Op386MOVLstoreidx1
 535         Op386MOVLstoreidx4
 536         Op386MOVBstoreconst
 537         Op386MOVWstoreconst
 538         Op386MOVLstoreconst
 539         Op386MOVBstoreconstidx1
 540         Op386MOVWstoreconstidx1
 541         Op386MOVWstoreconstidx2
 542         Op386MOVLstoreconstidx1
 543         Op386MOVLstoreconstidx4
 544         Op386DUFFZERO
 545         Op386REPSTOSL
 546         Op386CALLstatic
 547         Op386CALLtail
 548         Op386CALLclosure
 549         Op386CALLinter
 550         Op386DUFFCOPY
 551         Op386REPMOVSL
 552         Op386InvertFlags
 553         Op386LoweredGetG
 554         Op386LoweredGetClosurePtr
 555         Op386LoweredGetCallerPC
 556         Op386LoweredGetCallerSP
 557         Op386LoweredNilCheck
 558         Op386LoweredWB
 559         Op386LoweredPanicBoundsA
 560         Op386LoweredPanicBoundsB
 561         Op386LoweredPanicBoundsC
 562         Op386LoweredPanicExtendA
 563         Op386LoweredPanicExtendB
 564         Op386LoweredPanicExtendC
 565         Op386FlagEQ
 566         Op386FlagLT_ULT
 567         Op386FlagLT_UGT
 568         Op386FlagGT_UGT
 569         Op386FlagGT_ULT
 570         Op386MOVSSconst1
 571         Op386MOVSDconst1
 572         Op386MOVSSconst2
 573         Op386MOVSDconst2
 574
 575         OpAMD64ADDSS
 576         OpAMD64ADDSD
 577         OpAMD64SUBSS
 578         OpAMD64SUBSD
 579         OpAMD64MULSS
 580         OpAMD64MULSD
 581         OpAMD64DIVSS
 582         OpAMD64DIVSD
 583         OpAMD64MOVSSload
 584         OpAMD64MOVSDload
 585         OpAMD64MOVSSconst
 586         OpAMD64MOVSDconst
 587         OpAMD64MOVSSloadidx1
 588         OpAMD64MOVSSloadidx4
 589         OpAMD64MOVSDloadidx1
 590         OpAMD64MOVSDloadidx8
 591         OpAMD64MOVSSstore
 592         OpAMD64MOVSDstore
 593         OpAMD64MOVSSstoreidx1
 594         OpAMD64MOVSSstoreidx4
 595         OpAMD64MOVSDstoreidx1
 596         OpAMD64MOVSDstoreidx8
 597         OpAMD64ADDSSload
 598         OpAMD64ADDSDload
 599         OpAMD64SUBSSload
 600         OpAMD64SUBSDload
 601         OpAMD64MULSSload
 602         OpAMD64MULSDload
 603         OpAMD64DIVSSload
 604         OpAMD64DIVSDload
 605         OpAMD64ADDSSloadidx1
 606         OpAMD64ADDSSloadidx4
 607         OpAMD64ADDSDloadidx1
 608         OpAMD64ADDSDloadidx8
 609         OpAMD64SUBSSloadidx1
 610         OpAMD64SUBSSloadidx4
 611         OpAMD64SUBSDloadidx1
 612         OpAMD64SUBSDloadidx8
 613         OpAMD64MULSSloadidx1
 614         OpAMD64MULSSloadidx4
 615         OpAMD64MULSDloadidx1
 616         OpAMD64MULSDloadidx8
 617         OpAMD64DIVSSloadidx1
 618         OpAMD64DIVSSloadidx4
 619         OpAMD64DIVSDloadidx1
 620         OpAMD64DIVSDloadidx8
 621         OpAMD64ADDQ
 622         OpAMD64ADDL
 623         OpAMD64ADDQconst
 624         OpAMD64ADDLconst
 625         OpAMD64ADDQconstmodify
 626         OpAMD64ADDLconstmodify
 627         OpAMD64SUBQ
 628         OpAMD64SUBL
 629         OpAMD64SUBQconst
 630         OpAMD64SUBLconst
 631         OpAMD64MULQ
 632         OpAMD64MULL
 633         OpAMD64MULQconst
 634         OpAMD64MULLconst
 635         OpAMD64MULLU
 636         OpAMD64MULQU
 637         OpAMD64HMULQ
 638         OpAMD64HMULL
 639         OpAMD64HMULQU
 640         OpAMD64HMULLU
 641         OpAMD64AVGQU
 642         OpAMD64DIVQ
 643         OpAMD64DIVL
 644         OpAMD64DIVW
 645         OpAMD64DIVQU
 646         OpAMD64DIVLU
 647         OpAMD64DIVWU
 648         OpAMD64NEGLflags
 649         OpAMD64ADDQcarry
 650         OpAMD64ADCQ
 651         OpAMD64ADDQconstcarry
 652         OpAMD64ADCQconst
 653         OpAMD64SUBQborrow
 654         OpAMD64SBBQ
 655         OpAMD64SUBQconstborrow
 656         OpAMD64SBBQconst
 657         OpAMD64MULQU2
 658         OpAMD64DIVQU2
 659         OpAMD64ANDQ
 660         OpAMD64ANDL
 661         OpAMD64ANDQconst
 662         OpAMD64ANDLconst
 663         OpAMD64ANDQconstmodify
 664         OpAMD64ANDLconstmodify
 665         OpAMD64ORQ
 666         OpAMD64ORL
 667         OpAMD64ORQconst
 668         OpAMD64ORLconst
 669         OpAMD64ORQconstmodify
 670         OpAMD64ORLconstmodify
 671         OpAMD64XORQ
 672         OpAMD64XORL
 673         OpAMD64XORQconst
 674         OpAMD64XORLconst
 675         OpAMD64XORQconstmodify
 676         OpAMD64XORLconstmodify
 677         OpAMD64CMPQ
 678         OpAMD64CMPL
 679         OpAMD64CMPW
 680         OpAMD64CMPB
 681         OpAMD64CMPQconst
 682         OpAMD64CMPLconst
 683         OpAMD64CMPWconst
 684         OpAMD64CMPBconst
 685         OpAMD64CMPQload
 686         OpAMD64CMPLload
 687         OpAMD64CMPWload
 688         OpAMD64CMPBload
 689         OpAMD64CMPQconstload
 690         OpAMD64CMPLconstload
 691         OpAMD64CMPWconstload
 692         OpAMD64CMPBconstload
 693         OpAMD64CMPQloadidx8
 694         OpAMD64CMPQloadidx1
 695         OpAMD64CMPLloadidx4
 696         OpAMD64CMPLloadidx1
 697         OpAMD64CMPWloadidx2
 698         OpAMD64CMPWloadidx1
 699         OpAMD64CMPBloadidx1
 700         OpAMD64CMPQconstloadidx8
 701         OpAMD64CMPQconstloadidx1
 702         OpAMD64CMPLconstloadidx4
 703         OpAMD64CMPLconstloadidx1
 704         OpAMD64CMPWconstloadidx2
 705         OpAMD64CMPWconstloadidx1
 706         OpAMD64CMPBconstloadidx1
 707         OpAMD64UCOMISS
 708         OpAMD64UCOMISD
 709         OpAMD64BTL
 710         OpAMD64BTQ
 711         OpAMD64BTCL
 712         OpAMD64BTCQ
 713         OpAMD64BTRL
 714         OpAMD64BTRQ
 715         OpAMD64BTSL
 716         OpAMD64BTSQ
 717         OpAMD64BTLconst
 718         OpAMD64BTQconst
 719         OpAMD64BTCQconst
 720         OpAMD64BTRQconst
 721         OpAMD64BTSQconst
 722         OpAMD64BTSQconstmodify
 723         OpAMD64BTRQconstmodify
 724         OpAMD64BTCQconstmodify
 725         OpAMD64TESTQ
 726         OpAMD64TESTL
 727         OpAMD64TESTW
 728         OpAMD64TESTB
 729         OpAMD64TESTQconst
 730         OpAMD64TESTLconst
 731         OpAMD64TESTWconst
 732         OpAMD64TESTBconst
 733         OpAMD64SHLQ
 734         OpAMD64SHLL
 735         OpAMD64SHLQconst
 736         OpAMD64SHLLconst
 737         OpAMD64SHRQ
 738         OpAMD64SHRL
 739         OpAMD64SHRW
 740         OpAMD64SHRB
 741         OpAMD64SHRQconst
 742         OpAMD64SHRLconst
 743         OpAMD64SHRWconst
 744         OpAMD64SHRBconst
 745         OpAMD64SARQ
 746         OpAMD64SARL
 747         OpAMD64SARW
 748         OpAMD64SARB
 749         OpAMD64SARQconst
 750         OpAMD64SARLconst
 751         OpAMD64SARWconst
 752         OpAMD64SARBconst
 753         OpAMD64SHRDQ
 754         OpAMD64SHLDQ
 755         OpAMD64ROLQ
 756         OpAMD64ROLL
 757         OpAMD64ROLW
 758         OpAMD64ROLB
 759         OpAMD64RORQ
 760         OpAMD64RORL
 761         OpAMD64RORW
 762         OpAMD64RORB
 763         OpAMD64ROLQconst
 764         OpAMD64ROLLconst
 765         OpAMD64ROLWconst
 766         OpAMD64ROLBconst
 767         OpAMD64ADDLload
 768         OpAMD64ADDQload
 769         OpAMD64SUBQload
 770         OpAMD64SUBLload
 771         OpAMD64ANDLload
 772         OpAMD64ANDQload
 773         OpAMD64ORQload
 774         OpAMD64ORLload
 775         OpAMD64XORQload
 776         OpAMD64XORLload
 777         OpAMD64ADDLloadidx1
 778         OpAMD64ADDLloadidx4
 779         OpAMD64ADDLloadidx8
 780         OpAMD64ADDQloadidx1
 781         OpAMD64ADDQloadidx8
 782         OpAMD64SUBLloadidx1
 783         OpAMD64SUBLloadidx4
 784         OpAMD64SUBLloadidx8
 785         OpAMD64SUBQloadidx1
 786         OpAMD64SUBQloadidx8
 787         OpAMD64ANDLloadidx1
 788         OpAMD64ANDLloadidx4
 789         OpAMD64ANDLloadidx8
 790         OpAMD64ANDQloadidx1
 791         OpAMD64ANDQloadidx8
 792         OpAMD64ORLloadidx1
 793         OpAMD64ORLloadidx4
 794         OpAMD64ORLloadidx8
 795         OpAMD64ORQloadidx1
 796         OpAMD64ORQloadidx8
 797         OpAMD64XORLloadidx1
 798         OpAMD64XORLloadidx4
 799         OpAMD64XORLloadidx8
 800         OpAMD64XORQloadidx1
 801         OpAMD64XORQloadidx8
 802         OpAMD64ADDQmodify
 803         OpAMD64SUBQmodify
 804         OpAMD64ANDQmodify
 805         OpAMD64ORQmodify
 806         OpAMD64XORQmodify
 807         OpAMD64ADDLmodify
 808         OpAMD64SUBLmodify
 809         OpAMD64ANDLmodify
 810         OpAMD64ORLmodify
 811         OpAMD64XORLmodify
 812         OpAMD64ADDQmodifyidx1
 813         OpAMD64ADDQmodifyidx8
 814         OpAMD64SUBQmodifyidx1
 815         OpAMD64SUBQmodifyidx8
 816         OpAMD64ANDQmodifyidx1
 817         OpAMD64ANDQmodifyidx8
 818         OpAMD64ORQmodifyidx1
 819         OpAMD64ORQmodifyidx8
 820         OpAMD64XORQmodifyidx1
 821         OpAMD64XORQmodifyidx8
 822         OpAMD64ADDLmodifyidx1
 823         OpAMD64ADDLmodifyidx4
 824         OpAMD64ADDLmodifyidx8
 825         OpAMD64SUBLmodifyidx1
 826         OpAMD64SUBLmodifyidx4
 827         OpAMD64SUBLmodifyidx8
 828         OpAMD64ANDLmodifyidx1
 829         OpAMD64ANDLmodifyidx4
 830         OpAMD64ANDLmodifyidx8
 831         OpAMD64ORLmodifyidx1
 832         OpAMD64ORLmodifyidx4
 833         OpAMD64ORLmodifyidx8
 834         OpAMD64XORLmodifyidx1
 835         OpAMD64XORLmodifyidx4
 836         OpAMD64XORLmodifyidx8
 837         OpAMD64ADDQconstmodifyidx1
 838         OpAMD64ADDQconstmodifyidx8
 839         OpAMD64ANDQconstmodifyidx1
 840         OpAMD64ANDQconstmodifyidx8
 841         OpAMD64ORQconstmodifyidx1
 842         OpAMD64ORQconstmodifyidx8
 843         OpAMD64XORQconstmodifyidx1
 844         OpAMD64XORQconstmodifyidx8
 845         OpAMD64ADDLconstmodifyidx1
 846         OpAMD64ADDLconstmodifyidx4
 847         OpAMD64ADDLconstmodifyidx8
 848         OpAMD64ANDLconstmodifyidx1
 849         OpAMD64ANDLconstmodifyidx4
 850         OpAMD64ANDLconstmodifyidx8
 851         OpAMD64ORLconstmodifyidx1
 852         OpAMD64ORLconstmodifyidx4
 853         OpAMD64ORLconstmodifyidx8
 854         OpAMD64XORLconstmodifyidx1
 855         OpAMD64XORLconstmodifyidx4
 856         OpAMD64XORLconstmodifyidx8
 857         OpAMD64NEGQ
 858         OpAMD64NEGL
 859         OpAMD64NOTQ
 860         OpAMD64NOTL
 861         OpAMD64BSFQ
 862         OpAMD64BSFL
 863         OpAMD64BSRQ
 864         OpAMD64BSRL
 865         OpAMD64CMOVQEQ
 866         OpAMD64CMOVQNE
 867         OpAMD64CMOVQLT
 868         OpAMD64CMOVQGT
 869         OpAMD64CMOVQLE
 870         OpAMD64CMOVQGE
 871         OpAMD64CMOVQLS
 872         OpAMD64CMOVQHI
 873         OpAMD64CMOVQCC
 874         OpAMD64CMOVQCS
 875         OpAMD64CMOVLEQ
 876         OpAMD64CMOVLNE
 877         OpAMD64CMOVLLT
 878         OpAMD64CMOVLGT
 879         OpAMD64CMOVLLE
 880         OpAMD64CMOVLGE
 881         OpAMD64CMOVLLS
 882         OpAMD64CMOVLHI
 883         OpAMD64CMOVLCC
 884         OpAMD64CMOVLCS
 885         OpAMD64CMOVWEQ
 886         OpAMD64CMOVWNE
 887         OpAMD64CMOVWLT
 888         OpAMD64CMOVWGT
 889         OpAMD64CMOVWLE
 890         OpAMD64CMOVWGE
 891         OpAMD64CMOVWLS
 892         OpAMD64CMOVWHI
 893         OpAMD64CMOVWCC
 894         OpAMD64CMOVWCS
 895         OpAMD64CMOVQEQF
 896         OpAMD64CMOVQNEF
 897         OpAMD64CMOVQGTF
 898         OpAMD64CMOVQGEF
 899         OpAMD64CMOVLEQF
 900         OpAMD64CMOVLNEF
 901         OpAMD64CMOVLGTF
 902         OpAMD64CMOVLGEF
 903         OpAMD64CMOVWEQF
 904         OpAMD64CMOVWNEF
 905         OpAMD64CMOVWGTF
 906         OpAMD64CMOVWGEF
 907         OpAMD64BSWAPQ
 908         OpAMD64BSWAPL
 909         OpAMD64POPCNTQ
 910         OpAMD64POPCNTL
 911         OpAMD64SQRTSD
 912         OpAMD64SQRTSS
 913         OpAMD64ROUNDSD
 914         OpAMD64VFMADD231SD
 915         OpAMD64MINSD
 916         OpAMD64MINSS
 917         OpAMD64SBBQcarrymask
 918         OpAMD64SBBLcarrymask
 919         OpAMD64SETEQ
 920         OpAMD64SETNE
 921         OpAMD64SETL
 922         OpAMD64SETLE
 923         OpAMD64SETG
 924         OpAMD64SETGE
 925         OpAMD64SETB
 926         OpAMD64SETBE
 927         OpAMD64SETA
 928         OpAMD64SETAE
 929         OpAMD64SETO
 930         OpAMD64SETEQstore
 931         OpAMD64SETNEstore
 932         OpAMD64SETLstore
 933         OpAMD64SETLEstore
 934         OpAMD64SETGstore
 935         OpAMD64SETGEstore
 936         OpAMD64SETBstore
 937         OpAMD64SETBEstore
 938         OpAMD64SETAstore
 939         OpAMD64SETAEstore
 940         OpAMD64SETEQstoreidx1
 941         OpAMD64SETNEstoreidx1
 942         OpAMD64SETLstoreidx1
 943         OpAMD64SETLEstoreidx1
 944         OpAMD64SETGstoreidx1
 945         OpAMD64SETGEstoreidx1
 946         OpAMD64SETBstoreidx1
 947         OpAMD64SETBEstoreidx1
 948         OpAMD64SETAstoreidx1
 949         OpAMD64SETAEstoreidx1
 950         OpAMD64SETEQF
 951         OpAMD64SETNEF
 952         OpAMD64SETORD
 953         OpAMD64SETNAN
 954         OpAMD64SETGF
 955         OpAMD64SETGEF
 956         OpAMD64MOVBQSX
 957         OpAMD64MOVBQZX
 958         OpAMD64MOVWQSX
 959         OpAMD64MOVWQZX
 960         OpAMD64MOVLQSX
 961         OpAMD64MOVLQZX
 962         OpAMD64MOVLconst
 963         OpAMD64MOVQconst
 964         OpAMD64CVTTSD2SL
 965         OpAMD64CVTTSD2SQ
 966         OpAMD64CVTTSS2SL
 967         OpAMD64CVTTSS2SQ
 968         OpAMD64CVTSL2SS
 969         OpAMD64CVTSL2SD
 970         OpAMD64CVTSQ2SS
 971         OpAMD64CVTSQ2SD
 972         OpAMD64CVTSD2SS
 973         OpAMD64CVTSS2SD
 974         OpAMD64MOVQi2f
 975         OpAMD64MOVQf2i
 976         OpAMD64MOVLi2f
 977         OpAMD64MOVLf2i
 978         OpAMD64PXOR
 979         OpAMD64POR
 980         OpAMD64LEAQ
 981         OpAMD64LEAL
 982         OpAMD64LEAW
 983         OpAMD64LEAQ1
 984         OpAMD64LEAL1
 985         OpAMD64LEAW1
 986         OpAMD64LEAQ2
 987         OpAMD64LEAL2
 988         OpAMD64LEAW2
 989         OpAMD64LEAQ4
 990         OpAMD64LEAL4
 991         OpAMD64LEAW4
 992         OpAMD64LEAQ8
 993         OpAMD64LEAL8
 994         OpAMD64LEAW8
 995         OpAMD64MOVBload
 996         OpAMD64MOVBQSXload
 997         OpAMD64MOVWload
 998         OpAMD64MOVWQSXload
 999         OpAMD64MOVLload
1000         OpAMD64MOVLQSXload
1001         OpAMD64MOVQload
1002         OpAMD64MOVBstore
1003         OpAMD64MOVWstore
1004         OpAMD64MOVLstore
1005         OpAMD64MOVQstore
1006         OpAMD64MOVOload
1007         OpAMD64MOVOstore
1008         OpAMD64MOVBloadidx1
1009         OpAMD64MOVWloadidx1
1010         OpAMD64MOVWloadidx2
1011         OpAMD64MOVLloadidx1
1012         OpAMD64MOVLloadidx4
1013         OpAMD64MOVLloadidx8
1014         OpAMD64MOVQloadidx1
1015         OpAMD64MOVQloadidx8
1016         OpAMD64MOVBstoreidx1
1017         OpAMD64MOVWstoreidx1
1018         OpAMD64MOVWstoreidx2
1019         OpAMD64MOVLstoreidx1
1020         OpAMD64MOVLstoreidx4
1021         OpAMD64MOVLstoreidx8
1022         OpAMD64MOVQstoreidx1
1023         OpAMD64MOVQstoreidx8
1024         OpAMD64MOVBstoreconst
1025         OpAMD64MOVWstoreconst
1026         OpAMD64MOVLstoreconst
1027         OpAMD64MOVQstoreconst
1028         OpAMD64MOVOstoreconst
1029         OpAMD64MOVBstoreconstidx1
1030         OpAMD64MOVWstoreconstidx1
1031         OpAMD64MOVWstoreconstidx2
1032         OpAMD64MOVLstoreconstidx1
1033         OpAMD64MOVLstoreconstidx4
1034         OpAMD64MOVQstoreconstidx1
1035         OpAMD64MOVQstoreconstidx8
1036         OpAMD64DUFFZERO
1037         OpAMD64REPSTOSQ
1038         OpAMD64CALLstatic
1039         OpAMD64CALLtail
1040         OpAMD64CALLclosure
1041         OpAMD64CALLinter
1042         OpAMD64DUFFCOPY
1043         OpAMD64REPMOVSQ
1044         OpAMD64InvertFlags
1045         OpAMD64LoweredGetG
1046         OpAMD64LoweredGetClosurePtr
1047         OpAMD64LoweredGetCallerPC
1048         OpAMD64LoweredGetCallerSP
1049         OpAMD64LoweredNilCheck
1050         OpAMD64LoweredWB
1051         OpAMD64LoweredHasCPUFeature
1052         OpAMD64LoweredPanicBoundsA
1053         OpAMD64LoweredPanicBoundsB
1054         OpAMD64LoweredPanicBoundsC
1055         OpAMD64FlagEQ
1056         OpAMD64FlagLT_ULT
1057         OpAMD64FlagLT_UGT
1058         OpAMD64FlagGT_UGT
1059         OpAMD64FlagGT_ULT
1060         OpAMD64MOVBatomicload
1061         OpAMD64MOVLatomicload
1062         OpAMD64MOVQatomicload
1063         OpAMD64XCHGB
1064         OpAMD64XCHGL
1065         OpAMD64XCHGQ
1066         OpAMD64XADDLlock
1067         OpAMD64XADDQlock
1068         OpAMD64AddTupleFirst32
1069         OpAMD64AddTupleFirst64
1070         OpAMD64CMPXCHGLlock
1071         OpAMD64CMPXCHGQlock
1072         OpAMD64ANDBlock
1073         OpAMD64ANDLlock
1074         OpAMD64ORBlock
1075         OpAMD64ORLlock
1076         OpAMD64PrefetchT0
1077         OpAMD64PrefetchNTA
1078         OpAMD64ANDNQ
1079         OpAMD64ANDNL
1080         OpAMD64BLSIQ
1081         OpAMD64BLSIL
1082         OpAMD64BLSMSKQ
1083         OpAMD64BLSMSKL
1084         OpAMD64BLSRQ
1085         OpAMD64BLSRL
1086         OpAMD64TZCNTQ
1087         OpAMD64TZCNTL
1088         OpAMD64LZCNTQ
1089         OpAMD64LZCNTL
1090         OpAMD64MOVBEWstore
1091         OpAMD64MOVBELload
1092         OpAMD64MOVBELstore
1093         OpAMD64MOVBEQload
1094         OpAMD64MOVBEQstore
1095         OpAMD64MOVBELloadidx1
1096         OpAMD64MOVBELloadidx4
1097         OpAMD64MOVBELloadidx8
1098         OpAMD64MOVBEQloadidx1
1099         OpAMD64MOVBEQloadidx8
1100         OpAMD64MOVBEWstoreidx1
1101         OpAMD64MOVBEWstoreidx2
1102         OpAMD64MOVBELstoreidx1
1103         OpAMD64MOVBELstoreidx4
1104         OpAMD64MOVBELstoreidx8
1105         OpAMD64MOVBEQstoreidx1
1106         OpAMD64MOVBEQstoreidx8
1107         OpAMD64SARXQ
1108         OpAMD64SARXL
1109         OpAMD64SHLXQ
1110         OpAMD64SHLXL
1111         OpAMD64SHRXQ
1112         OpAMD64SHRXL
1113         OpAMD64SARXLload
1114         OpAMD64SARXQload
1115         OpAMD64SHLXLload
1116         OpAMD64SHLXQload
1117         OpAMD64SHRXLload
1118         OpAMD64SHRXQload
1119         OpAMD64SARXLloadidx1
1120         OpAMD64SARXLloadidx4
1121         OpAMD64SARXLloadidx8
1122         OpAMD64SARXQloadidx1
1123         OpAMD64SARXQloadidx8
1124         OpAMD64SHLXLloadidx1
1125         OpAMD64SHLXLloadidx4
1126         OpAMD64SHLXLloadidx8
1127         OpAMD64SHLXQloadidx1
1128         OpAMD64SHLXQloadidx8
1129         OpAMD64SHRXLloadidx1
1130         OpAMD64SHRXLloadidx4
1131         OpAMD64SHRXLloadidx8
1132         OpAMD64SHRXQloadidx1
1133         OpAMD64SHRXQloadidx8
1134
1135         OpARMADD
1136         OpARMADDconst
1137         OpARMSUB
1138         OpARMSUBconst
1139         OpARMRSB
1140         OpARMRSBconst
1141         OpARMMUL
1142         OpARMHMUL
1143         OpARMHMULU
1144         OpARMCALLudiv
1145         OpARMADDS
1146         OpARMADDSconst
1147         OpARMADC
1148         OpARMADCconst
1149         OpARMSUBS
1150         OpARMSUBSconst
1151         OpARMRSBSconst
1152         OpARMSBC
1153         OpARMSBCconst
1154         OpARMRSCconst
1155         OpARMMULLU
1156         OpARMMULA
1157         OpARMMULS
1158         OpARMADDF
1159         OpARMADDD
1160         OpARMSUBF
1161         OpARMSUBD
1162         OpARMMULF
1163         OpARMMULD
1164         OpARMNMULF
1165         OpARMNMULD
1166         OpARMDIVF
1167         OpARMDIVD
1168         OpARMMULAF
1169         OpARMMULAD
1170         OpARMMULSF
1171         OpARMMULSD
1172         OpARMFMULAD
1173         OpARMAND
1174         OpARMANDconst
1175         OpARMOR
1176         OpARMORconst
1177         OpARMXOR
1178         OpARMXORconst
1179         OpARMBIC
1180         OpARMBICconst
1181         OpARMBFX
1182         OpARMBFXU
1183         OpARMMVN
1184         OpARMNEGF
1185         OpARMNEGD
1186         OpARMSQRTD
1187         OpARMSQRTF
1188         OpARMABSD
1189         OpARMCLZ
1190         OpARMREV
1191         OpARMREV16
1192         OpARMRBIT
1193         OpARMSLL
1194         OpARMSLLconst
1195         OpARMSRL
1196         OpARMSRLconst
1197         OpARMSRA
1198         OpARMSRAconst
1199         OpARMSRR
1200         OpARMSRRconst
1201         OpARMADDshiftLL
1202         OpARMADDshiftRL
1203         OpARMADDshiftRA
1204         OpARMSUBshiftLL
1205         OpARMSUBshiftRL
1206         OpARMSUBshiftRA
1207         OpARMRSBshiftLL
1208         OpARMRSBshiftRL
1209         OpARMRSBshiftRA
1210         OpARMANDshiftLL
1211         OpARMANDshiftRL
1212         OpARMANDshiftRA
1213         OpARMORshiftLL
1214         OpARMORshiftRL
1215         OpARMORshiftRA
1216         OpARMXORshiftLL
1217         OpARMXORshiftRL
1218         OpARMXORshiftRA
1219         OpARMXORshiftRR
1220         OpARMBICshiftLL
1221         OpARMBICshiftRL
1222         OpARMBICshiftRA
1223         OpARMMVNshiftLL
1224         OpARMMVNshiftRL
1225         OpARMMVNshiftRA
1226         OpARMADCshiftLL
1227         OpARMADCshiftRL
1228         OpARMADCshiftRA
1229         OpARMSBCshiftLL
1230         OpARMSBCshiftRL
1231         OpARMSBCshiftRA
1232         OpARMRSCshiftLL
1233         OpARMRSCshiftRL
1234         OpARMRSCshiftRA
1235         OpARMADDSshiftLL
1236         OpARMADDSshiftRL
1237         OpARMADDSshiftRA
1238         OpARMSUBSshiftLL
1239         OpARMSUBSshiftRL
1240         OpARMSUBSshiftRA
1241         OpARMRSBSshiftLL
1242         OpARMRSBSshiftRL
1243         OpARMRSBSshiftRA
1244         OpARMADDshiftLLreg
1245         OpARMADDshiftRLreg
1246         OpARMADDshiftRAreg
1247         OpARMSUBshiftLLreg
1248         OpARMSUBshiftRLreg
1249         OpARMSUBshiftRAreg
1250         OpARMRSBshiftLLreg
1251         OpARMRSBshiftRLreg
1252         OpARMRSBshiftRAreg
1253         OpARMANDshiftLLreg
1254         OpARMANDshiftRLreg
1255         OpARMANDshiftRAreg
1256         OpARMORshiftLLreg
1257         OpARMORshiftRLreg
1258         OpARMORshiftRAreg
1259         OpARMXORshiftLLreg
1260         OpARMXORshiftRLreg
1261         OpARMXORshiftRAreg
1262         OpARMBICshiftLLreg
1263         OpARMBICshiftRLreg
1264         OpARMBICshiftRAreg
1265         OpARMMVNshiftLLreg
1266         OpARMMVNshiftRLreg
1267         OpARMMVNshiftRAreg
1268         OpARMADCshiftLLreg
1269         OpARMADCshiftRLreg
1270         OpARMADCshiftRAreg
1271         OpARMSBCshiftLLreg
1272         OpARMSBCshiftRLreg
1273         OpARMSBCshiftRAreg
1274         OpARMRSCshiftLLreg
1275         OpARMRSCshiftRLreg
1276         OpARMRSCshiftRAreg
1277         OpARMADDSshiftLLreg
1278         OpARMADDSshiftRLreg
1279         OpARMADDSshiftRAreg
1280         OpARMSUBSshiftLLreg
1281         OpARMSUBSshiftRLreg
1282         OpARMSUBSshiftRAreg
1283         OpARMRSBSshiftLLreg
1284         OpARMRSBSshiftRLreg
1285         OpARMRSBSshiftRAreg
1286         OpARMCMP
1287         OpARMCMPconst
1288         OpARMCMN
1289         OpARMCMNconst
1290         OpARMTST
1291         OpARMTSTconst
1292         OpARMTEQ
1293         OpARMTEQconst
1294         OpARMCMPF
1295         OpARMCMPD
1296         OpARMCMPshiftLL
1297         OpARMCMPshiftRL
1298         OpARMCMPshiftRA
1299         OpARMCMNshiftLL
1300         OpARMCMNshiftRL
1301         OpARMCMNshiftRA
1302         OpARMTSTshiftLL
1303         OpARMTSTshiftRL
1304         OpARMTSTshiftRA
1305         OpARMTEQshiftLL
1306         OpARMTEQshiftRL
1307         OpARMTEQshiftRA
1308         OpARMCMPshiftLLreg
1309         OpARMCMPshiftRLreg
1310         OpARMCMPshiftRAreg
1311         OpARMCMNshiftLLreg
1312         OpARMCMNshiftRLreg
1313         OpARMCMNshiftRAreg
1314         OpARMTSTshiftLLreg
1315         OpARMTSTshiftRLreg
1316         OpARMTSTshiftRAreg
1317         OpARMTEQshiftLLreg
1318         OpARMTEQshiftRLreg
1319         OpARMTEQshiftRAreg
1320         OpARMCMPF0
1321         OpARMCMPD0
1322         OpARMMOVWconst
1323         OpARMMOVFconst
1324         OpARMMOVDconst
1325         OpARMMOVWaddr
1326         OpARMMOVBload
1327         OpARMMOVBUload
1328         OpARMMOVHload
1329         OpARMMOVHUload
1330         OpARMMOVWload
1331         OpARMMOVFload
1332         OpARMMOVDload
1333         OpARMMOVBstore
1334         OpARMMOVHstore
1335         OpARMMOVWstore
1336         OpARMMOVFstore
1337         OpARMMOVDstore
1338         OpARMMOVWloadidx
1339         OpARMMOVWloadshiftLL
1340         OpARMMOVWloadshiftRL
1341         OpARMMOVWloadshiftRA
1342         OpARMMOVBUloadidx
1343         OpARMMOVBloadidx
1344         OpARMMOVHUloadidx
1345         OpARMMOVHloadidx
1346         OpARMMOVWstoreidx
1347         OpARMMOVWstoreshiftLL
1348         OpARMMOVWstoreshiftRL
1349         OpARMMOVWstoreshiftRA
1350         OpARMMOVBstoreidx
1351         OpARMMOVHstoreidx
1352         OpARMMOVBreg
1353         OpARMMOVBUreg
1354         OpARMMOVHreg
1355         OpARMMOVHUreg
1356         OpARMMOVWreg
1357         OpARMMOVWnop
1358         OpARMMOVWF
1359         OpARMMOVWD
1360         OpARMMOVWUF
1361         OpARMMOVWUD
1362         OpARMMOVFW
1363         OpARMMOVDW
1364         OpARMMOVFWU
1365         OpARMMOVDWU
1366         OpARMMOVFD
1367         OpARMMOVDF
1368         OpARMCMOVWHSconst
1369         OpARMCMOVWLSconst
1370         OpARMSRAcond
1371         OpARMCALLstatic
1372         OpARMCALLtail
1373         OpARMCALLclosure
1374         OpARMCALLinter
1375         OpARMLoweredNilCheck
1376         OpARMEqual
1377         OpARMNotEqual
1378         OpARMLessThan
1379         OpARMLessEqual
1380         OpARMGreaterThan
1381         OpARMGreaterEqual
1382         OpARMLessThanU
1383         OpARMLessEqualU
1384         OpARMGreaterThanU
1385         OpARMGreaterEqualU
1386         OpARMDUFFZERO
1387         OpARMDUFFCOPY
1388         OpARMLoweredZero
1389         OpARMLoweredMove
1390         OpARMLoweredGetClosurePtr
1391         OpARMLoweredGetCallerSP
1392         OpARMLoweredGetCallerPC
1393         OpARMLoweredPanicBoundsA
1394         OpARMLoweredPanicBoundsB
1395         OpARMLoweredPanicBoundsC
1396         OpARMLoweredPanicExtendA
1397         OpARMLoweredPanicExtendB
1398         OpARMLoweredPanicExtendC
1399         OpARMFlagConstant
1400         OpARMInvertFlags
1401         OpARMLoweredWB
1402
1403         OpARM64ADCSflags
1404         OpARM64ADCzerocarry
1405         OpARM64ADD
1406         OpARM64ADDconst
1407         OpARM64ADDSconstflags
1408         OpARM64ADDSflags
1409         OpARM64SUB
1410         OpARM64SUBconst
1411         OpARM64SBCSflags
1412         OpARM64SUBSflags
1413         OpARM64MUL
1414         OpARM64MULW
1415         OpARM64MNEG
1416         OpARM64MNEGW
1417         OpARM64MULH
1418         OpARM64UMULH
1419         OpARM64MULL
1420         OpARM64UMULL
1421         OpARM64DIV
1422         OpARM64UDIV
1423         OpARM64DIVW
1424         OpARM64UDIVW
1425         OpARM64MOD
1426         OpARM64UMOD
1427         OpARM64MODW
1428         OpARM64UMODW
1429         OpARM64FADDS
1430         OpARM64FADDD
1431         OpARM64FSUBS
1432         OpARM64FSUBD
1433         OpARM64FMULS
1434         OpARM64FMULD
1435         OpARM64FNMULS
1436         OpARM64FNMULD
1437         OpARM64FDIVS
1438         OpARM64FDIVD
1439         OpARM64AND
1440         OpARM64ANDconst
1441         OpARM64OR
1442         OpARM64ORconst
1443         OpARM64XOR
1444         OpARM64XORconst
1445         OpARM64BIC
1446         OpARM64EON
1447         OpARM64ORN
1448         OpARM64MVN
1449         OpARM64NEG
1450         OpARM64NEGSflags
1451         OpARM64NGCzerocarry
1452         OpARM64FABSD
1453         OpARM64FNEGS
1454         OpARM64FNEGD
1455         OpARM64FSQRTD
1456         OpARM64FSQRTS
1457         OpARM64FMIND
1458         OpARM64FMINS
1459         OpARM64FMAXD
1460         OpARM64FMAXS
1461         OpARM64REV
1462         OpARM64REVW
1463         OpARM64REV16
1464         OpARM64REV16W
1465         OpARM64RBIT
1466         OpARM64RBITW
1467         OpARM64CLZ
1468         OpARM64CLZW
1469         OpARM64VCNT
1470         OpARM64VUADDLV
1471         OpARM64LoweredRound32F
1472         OpARM64LoweredRound64F
1473         OpARM64FMADDS
1474         OpARM64FMADDD
1475         OpARM64FNMADDS
1476         OpARM64FNMADDD
1477         OpARM64FMSUBS
1478         OpARM64FMSUBD
1479         OpARM64FNMSUBS
1480         OpARM64FNMSUBD
1481         OpARM64MADD
1482         OpARM64MADDW
1483         OpARM64MSUB
1484         OpARM64MSUBW
1485         OpARM64SLL
1486         OpARM64SLLconst
1487         OpARM64SRL
1488         OpARM64SRLconst
1489         OpARM64SRA
1490         OpARM64SRAconst
1491         OpARM64ROR
1492         OpARM64RORW
1493         OpARM64RORconst
1494         OpARM64RORWconst
1495         OpARM64EXTRconst
1496         OpARM64EXTRWconst
1497         OpARM64CMP
1498         OpARM64CMPconst
1499         OpARM64CMPW
1500         OpARM64CMPWconst
1501         OpARM64CMN
1502         OpARM64CMNconst
1503         OpARM64CMNW
1504         OpARM64CMNWconst
1505         OpARM64TST
1506         OpARM64TSTconst
1507         OpARM64TSTW
1508         OpARM64TSTWconst
1509         OpARM64FCMPS
1510         OpARM64FCMPD
1511         OpARM64FCMPS0
1512         OpARM64FCMPD0
1513         OpARM64MVNshiftLL
1514         OpARM64MVNshiftRL
1515         OpARM64MVNshiftRA
1516         OpARM64MVNshiftRO
1517         OpARM64NEGshiftLL
1518         OpARM64NEGshiftRL
1519         OpARM64NEGshiftRA
1520         OpARM64ADDshiftLL
1521         OpARM64ADDshiftRL
1522         OpARM64ADDshiftRA
1523         OpARM64SUBshiftLL
1524         OpARM64SUBshiftRL
1525         OpARM64SUBshiftRA
1526         OpARM64ANDshiftLL
1527         OpARM64ANDshiftRL
1528         OpARM64ANDshiftRA
1529         OpARM64ANDshiftRO
1530         OpARM64ORshiftLL
1531         OpARM64ORshiftRL
1532         OpARM64ORshiftRA
1533         OpARM64ORshiftRO
1534         OpARM64XORshiftLL
1535         OpARM64XORshiftRL
1536         OpARM64XORshiftRA
1537         OpARM64XORshiftRO
1538         OpARM64BICshiftLL
1539         OpARM64BICshiftRL
1540         OpARM64BICshiftRA
1541         OpARM64BICshiftRO
1542         OpARM64EONshiftLL
1543         OpARM64EONshiftRL
1544         OpARM64EONshiftRA
1545         OpARM64EONshiftRO
1546         OpARM64ORNshiftLL
1547         OpARM64ORNshiftRL
1548         OpARM64ORNshiftRA
1549         OpARM64ORNshiftRO
1550         OpARM64CMPshiftLL
1551         OpARM64CMPshiftRL
1552         OpARM64CMPshiftRA
1553         OpARM64CMNshiftLL
1554         OpARM64CMNshiftRL
1555         OpARM64CMNshiftRA
1556         OpARM64TSTshiftLL
1557         OpARM64TSTshiftRL
1558         OpARM64TSTshiftRA
1559         OpARM64TSTshiftRO
1560         OpARM64BFI
1561         OpARM64BFXIL
1562         OpARM64SBFIZ
1563         OpARM64SBFX
1564         OpARM64UBFIZ
1565         OpARM64UBFX
1566         OpARM64MOVDconst
1567         OpARM64FMOVSconst
1568         OpARM64FMOVDconst
1569         OpARM64MOVDaddr
1570         OpARM64MOVBload
1571         OpARM64MOVBUload
1572         OpARM64MOVHload
1573         OpARM64MOVHUload
1574         OpARM64MOVWload
1575         OpARM64MOVWUload
1576         OpARM64MOVDload
1577         OpARM64LDP
1578         OpARM64FMOVSload
1579         OpARM64FMOVDload
1580         OpARM64MOVDloadidx
1581         OpARM64MOVWloadidx
1582         OpARM64MOVWUloadidx
1583         OpARM64MOVHloadidx
1584         OpARM64MOVHUloadidx
1585         OpARM64MOVBloadidx
1586         OpARM64MOVBUloadidx
1587         OpARM64FMOVSloadidx
1588         OpARM64FMOVDloadidx
1589         OpARM64MOVHloadidx2
1590         OpARM64MOVHUloadidx2
1591         OpARM64MOVWloadidx4
1592         OpARM64MOVWUloadidx4
1593         OpARM64MOVDloadidx8
1594         OpARM64FMOVSloadidx4
1595         OpARM64FMOVDloadidx8
1596         OpARM64MOVBstore
1597         OpARM64MOVHstore
1598         OpARM64MOVWstore
1599         OpARM64MOVDstore
1600         OpARM64STP
1601         OpARM64FMOVSstore
1602         OpARM64FMOVDstore
1603         OpARM64MOVBstoreidx
1604         OpARM64MOVHstoreidx
1605         OpARM64MOVWstoreidx
1606         OpARM64MOVDstoreidx
1607         OpARM64FMOVSstoreidx
1608         OpARM64FMOVDstoreidx
1609         OpARM64MOVHstoreidx2
1610         OpARM64MOVWstoreidx4
1611         OpARM64MOVDstoreidx8
1612         OpARM64FMOVSstoreidx4
1613         OpARM64FMOVDstoreidx8
1614         OpARM64MOVBstorezero
1615         OpARM64MOVHstorezero
1616         OpARM64MOVWstorezero
1617         OpARM64MOVDstorezero
1618         OpARM64MOVQstorezero
1619         OpARM64MOVBstorezeroidx
1620         OpARM64MOVHstorezeroidx
1621         OpARM64MOVWstorezeroidx
1622         OpARM64MOVDstorezeroidx
1623         OpARM64MOVHstorezeroidx2
1624         OpARM64MOVWstorezeroidx4
1625         OpARM64MOVDstorezeroidx8
1626         OpARM64FMOVDgpfp
1627         OpARM64FMOVDfpgp
1628         OpARM64FMOVSgpfp
1629         OpARM64FMOVSfpgp
1630         OpARM64MOVBreg
1631         OpARM64MOVBUreg
1632         OpARM64MOVHreg
1633         OpARM64MOVHUreg
1634         OpARM64MOVWreg
1635         OpARM64MOVWUreg
1636         OpARM64MOVDreg
1637         OpARM64MOVDnop
1638         OpARM64SCVTFWS
1639         OpARM64SCVTFWD
1640         OpARM64UCVTFWS
1641         OpARM64UCVTFWD
1642         OpARM64SCVTFS
1643         OpARM64SCVTFD
1644         OpARM64UCVTFS
1645         OpARM64UCVTFD
1646         OpARM64FCVTZSSW
1647         OpARM64FCVTZSDW
1648         OpARM64FCVTZUSW
1649         OpARM64FCVTZUDW
1650         OpARM64FCVTZSS
1651         OpARM64FCVTZSD
1652         OpARM64FCVTZUS
1653         OpARM64FCVTZUD
1654         OpARM64FCVTSD
1655         OpARM64FCVTDS
1656         OpARM64FRINTAD
1657         OpARM64FRINTMD
1658         OpARM64FRINTND
1659         OpARM64FRINTPD
1660         OpARM64FRINTZD
1661         OpARM64CSEL
1662         OpARM64CSEL0
1663         OpARM64CSINC
1664         OpARM64CSINV
1665         OpARM64CSNEG
1666         OpARM64CSETM
1667         OpARM64CALLstatic
1668         OpARM64CALLtail
1669         OpARM64CALLclosure
1670         OpARM64CALLinter
1671         OpARM64LoweredNilCheck
1672         OpARM64Equal
1673         OpARM64NotEqual
1674         OpARM64LessThan
1675         OpARM64LessEqual
1676         OpARM64GreaterThan
1677         OpARM64GreaterEqual
1678         OpARM64LessThanU
1679         OpARM64LessEqualU
1680         OpARM64GreaterThanU
1681         OpARM64GreaterEqualU
1682         OpARM64LessThanF
1683         OpARM64LessEqualF
1684         OpARM64GreaterThanF
1685         OpARM64GreaterEqualF
1686         OpARM64NotLessThanF
1687         OpARM64NotLessEqualF
1688         OpARM64NotGreaterThanF
1689         OpARM64NotGreaterEqualF
1690         OpARM64LessThanNoov
1691         OpARM64GreaterEqualNoov
1692         OpARM64DUFFZERO
1693         OpARM64LoweredZero
1694         OpARM64DUFFCOPY
1695         OpARM64LoweredMove
1696         OpARM64LoweredGetClosurePtr
1697         OpARM64LoweredGetCallerSP
1698         OpARM64LoweredGetCallerPC
1699         OpARM64FlagConstant
1700         OpARM64InvertFlags
1701         OpARM64LDAR
1702         OpARM64LDARB
1703         OpARM64LDARW
1704         OpARM64STLRB
1705         OpARM64STLR
1706         OpARM64STLRW
1707         OpARM64LoweredAtomicExchange64
1708         OpARM64LoweredAtomicExchange32
1709         OpARM64LoweredAtomicExchange64Variant
1710         OpARM64LoweredAtomicExchange32Variant
1711         OpARM64LoweredAtomicAdd64
1712         OpARM64LoweredAtomicAdd32
1713         OpARM64LoweredAtomicAdd64Variant
1714         OpARM64LoweredAtomicAdd32Variant
1715         OpARM64LoweredAtomicCas64
1716         OpARM64LoweredAtomicCas32
1717         OpARM64LoweredAtomicCas64Variant
1718         OpARM64LoweredAtomicCas32Variant
1719         OpARM64LoweredAtomicAnd8
1720         OpARM64LoweredAtomicAnd32
1721         OpARM64LoweredAtomicOr8
1722         OpARM64LoweredAtomicOr32
1723         OpARM64LoweredAtomicAnd8Variant
1724         OpARM64LoweredAtomicAnd32Variant
1725         OpARM64LoweredAtomicOr8Variant
1726         OpARM64LoweredAtomicOr32Variant
1727         OpARM64LoweredWB
1728         OpARM64LoweredPanicBoundsA
1729         OpARM64LoweredPanicBoundsB
1730         OpARM64LoweredPanicBoundsC
1731         OpARM64PRFM
1732         OpARM64DMB
1733
1734         OpLOONG64ADDV
1735         OpLOONG64ADDVconst
1736         OpLOONG64SUBV
1737         OpLOONG64SUBVconst
1738         OpLOONG64MULV
1739         OpLOONG64MULHV
1740         OpLOONG64MULHVU
1741         OpLOONG64DIVV
1742         OpLOONG64DIVVU
1743         OpLOONG64REMV
1744         OpLOONG64REMVU
1745         OpLOONG64ADDF
1746         OpLOONG64ADDD
1747         OpLOONG64SUBF
1748         OpLOONG64SUBD
1749         OpLOONG64MULF
1750         OpLOONG64MULD
1751         OpLOONG64DIVF
1752         OpLOONG64DIVD
1753         OpLOONG64AND
1754         OpLOONG64ANDconst
1755         OpLOONG64OR
1756         OpLOONG64ORconst
1757         OpLOONG64XOR
1758         OpLOONG64XORconst
1759         OpLOONG64NOR
1760         OpLOONG64NORconst
1761         OpLOONG64NEGV
1762         OpLOONG64NEGF
1763         OpLOONG64NEGD
1764         OpLOONG64SQRTD
1765         OpLOONG64SQRTF
1766         OpLOONG64MASKEQZ
1767         OpLOONG64MASKNEZ
1768         OpLOONG64SLLV
1769         OpLOONG64SLLVconst
1770         OpLOONG64SRLV
1771         OpLOONG64SRLVconst
1772         OpLOONG64SRAV
1773         OpLOONG64SRAVconst
1774         OpLOONG64ROTR
1775         OpLOONG64ROTRV
1776         OpLOONG64ROTRconst
1777         OpLOONG64ROTRVconst
1778         OpLOONG64SGT
1779         OpLOONG64SGTconst
1780         OpLOONG64SGTU
1781         OpLOONG64SGTUconst
1782         OpLOONG64CMPEQF
1783         OpLOONG64CMPEQD
1784         OpLOONG64CMPGEF
1785         OpLOONG64CMPGED
1786         OpLOONG64CMPGTF
1787         OpLOONG64CMPGTD
1788         OpLOONG64MOVVconst
1789         OpLOONG64MOVFconst
1790         OpLOONG64MOVDconst
1791         OpLOONG64MOVVaddr
1792         OpLOONG64MOVBload
1793         OpLOONG64MOVBUload
1794         OpLOONG64MOVHload
1795         OpLOONG64MOVHUload
1796         OpLOONG64MOVWload
1797         OpLOONG64MOVWUload
1798         OpLOONG64MOVVload
1799         OpLOONG64MOVFload
1800         OpLOONG64MOVDload
1801         OpLOONG64MOVBstore
1802         OpLOONG64MOVHstore
1803         OpLOONG64MOVWstore
1804         OpLOONG64MOVVstore
1805         OpLOONG64MOVFstore
1806         OpLOONG64MOVDstore
1807         OpLOONG64MOVBstorezero
1808         OpLOONG64MOVHstorezero
1809         OpLOONG64MOVWstorezero
1810         OpLOONG64MOVVstorezero
1811         OpLOONG64MOVBreg
1812         OpLOONG64MOVBUreg
1813         OpLOONG64MOVHreg
1814         OpLOONG64MOVHUreg
1815         OpLOONG64MOVWreg
1816         OpLOONG64MOVWUreg
1817         OpLOONG64MOVVreg
1818         OpLOONG64MOVVnop
1819         OpLOONG64MOVWF
1820         OpLOONG64MOVWD
1821         OpLOONG64MOVVF
1822         OpLOONG64MOVVD
1823         OpLOONG64TRUNCFW
1824         OpLOONG64TRUNCDW
1825         OpLOONG64TRUNCFV
1826         OpLOONG64TRUNCDV
1827         OpLOONG64MOVFD
1828         OpLOONG64MOVDF
1829         OpLOONG64CALLstatic
1830         OpLOONG64CALLtail
1831         OpLOONG64CALLclosure
1832         OpLOONG64CALLinter
1833         OpLOONG64DUFFZERO
1834         OpLOONG64DUFFCOPY
1835         OpLOONG64LoweredZero
1836         OpLOONG64LoweredMove
1837         OpLOONG64LoweredAtomicLoad8
1838         OpLOONG64LoweredAtomicLoad32
1839         OpLOONG64LoweredAtomicLoad64
1840         OpLOONG64LoweredAtomicStore8
1841         OpLOONG64LoweredAtomicStore32
1842         OpLOONG64LoweredAtomicStore64
1843         OpLOONG64LoweredAtomicStorezero32
1844         OpLOONG64LoweredAtomicStorezero64
1845         OpLOONG64LoweredAtomicExchange32
1846         OpLOONG64LoweredAtomicExchange64
1847         OpLOONG64LoweredAtomicAdd32
1848         OpLOONG64LoweredAtomicAdd64
1849         OpLOONG64LoweredAtomicAddconst32
1850         OpLOONG64LoweredAtomicAddconst64
1851         OpLOONG64LoweredAtomicCas32
1852         OpLOONG64LoweredAtomicCas64
1853         OpLOONG64LoweredNilCheck
1854         OpLOONG64FPFlagTrue
1855         OpLOONG64FPFlagFalse
1856         OpLOONG64LoweredGetClosurePtr
1857         OpLOONG64LoweredGetCallerSP
1858         OpLOONG64LoweredGetCallerPC
1859         OpLOONG64LoweredWB
1860         OpLOONG64LoweredPanicBoundsA
1861         OpLOONG64LoweredPanicBoundsB
1862         OpLOONG64LoweredPanicBoundsC
1863
1864         OpMIPSADD
1865         OpMIPSADDconst
1866         OpMIPSSUB
1867         OpMIPSSUBconst
1868         OpMIPSMUL
1869         OpMIPSMULT
1870         OpMIPSMULTU
1871         OpMIPSDIV
1872         OpMIPSDIVU
1873         OpMIPSADDF
1874         OpMIPSADDD
1875         OpMIPSSUBF
1876         OpMIPSSUBD
1877         OpMIPSMULF
1878         OpMIPSMULD
1879         OpMIPSDIVF
1880         OpMIPSDIVD
1881         OpMIPSAND
1882         OpMIPSANDconst
1883         OpMIPSOR
1884         OpMIPSORconst
1885         OpMIPSXOR
1886         OpMIPSXORconst
1887         OpMIPSNOR
1888         OpMIPSNORconst
1889         OpMIPSNEG
1890         OpMIPSNEGF
1891         OpMIPSNEGD
1892         OpMIPSABSD
1893         OpMIPSSQRTD
1894         OpMIPSSQRTF
1895         OpMIPSSLL
1896         OpMIPSSLLconst
1897         OpMIPSSRL
1898         OpMIPSSRLconst
1899         OpMIPSSRA
1900         OpMIPSSRAconst
1901         OpMIPSCLZ
1902         OpMIPSSGT
1903         OpMIPSSGTconst
1904         OpMIPSSGTzero
1905         OpMIPSSGTU
1906         OpMIPSSGTUconst
1907         OpMIPSSGTUzero
1908         OpMIPSCMPEQF
1909         OpMIPSCMPEQD
1910         OpMIPSCMPGEF
1911         OpMIPSCMPGED
1912         OpMIPSCMPGTF
1913         OpMIPSCMPGTD
1914         OpMIPSMOVWconst
1915         OpMIPSMOVFconst
1916         OpMIPSMOVDconst
1917         OpMIPSMOVWaddr
1918         OpMIPSMOVBload
1919         OpMIPSMOVBUload
1920         OpMIPSMOVHload
1921         OpMIPSMOVHUload
1922         OpMIPSMOVWload
1923         OpMIPSMOVFload
1924         OpMIPSMOVDload
1925         OpMIPSMOVBstore
1926         OpMIPSMOVHstore
1927         OpMIPSMOVWstore
1928         OpMIPSMOVFstore
1929         OpMIPSMOVDstore
1930         OpMIPSMOVBstorezero
1931         OpMIPSMOVHstorezero
1932         OpMIPSMOVWstorezero
1933         OpMIPSMOVWfpgp
1934         OpMIPSMOVWgpfp
1935         OpMIPSMOVBreg
1936         OpMIPSMOVBUreg
1937         OpMIPSMOVHreg
1938         OpMIPSMOVHUreg
1939         OpMIPSMOVWreg
1940         OpMIPSMOVWnop
1941         OpMIPSCMOVZ
1942         OpMIPSCMOVZzero
1943         OpMIPSMOVWF
1944         OpMIPSMOVWD
1945         OpMIPSTRUNCFW
1946         OpMIPSTRUNCDW
1947         OpMIPSMOVFD
1948         OpMIPSMOVDF
1949         OpMIPSCALLstatic
1950         OpMIPSCALLtail
1951         OpMIPSCALLclosure
1952         OpMIPSCALLinter
1953         OpMIPSLoweredAtomicLoad8
1954         OpMIPSLoweredAtomicLoad32
1955         OpMIPSLoweredAtomicStore8
1956         OpMIPSLoweredAtomicStore32
1957         OpMIPSLoweredAtomicStorezero
1958         OpMIPSLoweredAtomicExchange
1959         OpMIPSLoweredAtomicAdd
1960         OpMIPSLoweredAtomicAddconst
1961         OpMIPSLoweredAtomicCas
1962         OpMIPSLoweredAtomicAnd
1963         OpMIPSLoweredAtomicOr
1964         OpMIPSLoweredZero
1965         OpMIPSLoweredMove
1966         OpMIPSLoweredNilCheck
1967         OpMIPSFPFlagTrue
1968         OpMIPSFPFlagFalse
1969         OpMIPSLoweredGetClosurePtr
1970         OpMIPSLoweredGetCallerSP
1971         OpMIPSLoweredGetCallerPC
1972         OpMIPSLoweredWB
1973         OpMIPSLoweredPanicBoundsA
1974         OpMIPSLoweredPanicBoundsB
1975         OpMIPSLoweredPanicBoundsC
1976         OpMIPSLoweredPanicExtendA
1977         OpMIPSLoweredPanicExtendB
1978         OpMIPSLoweredPanicExtendC
1979
1980         OpMIPS64ADDV
1981         OpMIPS64ADDVconst
1982         OpMIPS64SUBV
1983         OpMIPS64SUBVconst
1984         OpMIPS64MULV
1985         OpMIPS64MULVU
1986         OpMIPS64DIVV
1987         OpMIPS64DIVVU
1988         OpMIPS64ADDF
1989         OpMIPS64ADDD
1990         OpMIPS64SUBF
1991         OpMIPS64SUBD
1992         OpMIPS64MULF
1993         OpMIPS64MULD
1994         OpMIPS64DIVF
1995         OpMIPS64DIVD
1996         OpMIPS64AND
1997         OpMIPS64ANDconst
1998         OpMIPS64OR
1999         OpMIPS64ORconst
2000         OpMIPS64XOR
2001         OpMIPS64XORconst
2002         OpMIPS64NOR
2003         OpMIPS64NORconst
2004         OpMIPS64NEGV
2005         OpMIPS64NEGF
2006         OpMIPS64NEGD
2007         OpMIPS64ABSD
2008         OpMIPS64SQRTD
2009         OpMIPS64SQRTF
2010         OpMIPS64SLLV
2011         OpMIPS64SLLVconst
2012         OpMIPS64SRLV
2013         OpMIPS64SRLVconst
2014         OpMIPS64SRAV
2015         OpMIPS64SRAVconst
2016         OpMIPS64SGT
2017         OpMIPS64SGTconst
2018         OpMIPS64SGTU
2019         OpMIPS64SGTUconst
2020         OpMIPS64CMPEQF
2021         OpMIPS64CMPEQD
2022         OpMIPS64CMPGEF
2023         OpMIPS64CMPGED
2024         OpMIPS64CMPGTF
2025         OpMIPS64CMPGTD
2026         OpMIPS64MOVVconst
2027         OpMIPS64MOVFconst
2028         OpMIPS64MOVDconst
2029         OpMIPS64MOVVaddr
2030         OpMIPS64MOVBload
2031         OpMIPS64MOVBUload
2032         OpMIPS64MOVHload
2033         OpMIPS64MOVHUload
2034         OpMIPS64MOVWload
2035         OpMIPS64MOVWUload
2036         OpMIPS64MOVVload
2037         OpMIPS64MOVFload
2038         OpMIPS64MOVDload
2039         OpMIPS64MOVBstore
2040         OpMIPS64MOVHstore
2041         OpMIPS64MOVWstore
2042         OpMIPS64MOVVstore
2043         OpMIPS64MOVFstore
2044         OpMIPS64MOVDstore
2045         OpMIPS64MOVBstorezero
2046         OpMIPS64MOVHstorezero
2047         OpMIPS64MOVWstorezero
2048         OpMIPS64MOVVstorezero
2049         OpMIPS64MOVWfpgp
2050         OpMIPS64MOVWgpfp
2051         OpMIPS64MOVVfpgp
2052         OpMIPS64MOVVgpfp
2053         OpMIPS64MOVBreg
2054         OpMIPS64MOVBUreg
2055         OpMIPS64MOVHreg
2056         OpMIPS64MOVHUreg
2057         OpMIPS64MOVWreg
2058         OpMIPS64MOVWUreg
2059         OpMIPS64MOVVreg
2060         OpMIPS64MOVVnop
2061         OpMIPS64MOVWF
2062         OpMIPS64MOVWD
2063         OpMIPS64MOVVF
2064         OpMIPS64MOVVD
2065         OpMIPS64TRUNCFW
2066         OpMIPS64TRUNCDW
2067         OpMIPS64TRUNCFV
2068         OpMIPS64TRUNCDV
2069         OpMIPS64MOVFD
2070         OpMIPS64MOVDF
2071         OpMIPS64CALLstatic
2072         OpMIPS64CALLtail
2073         OpMIPS64CALLclosure
2074         OpMIPS64CALLinter
2075         OpMIPS64DUFFZERO
2076         OpMIPS64DUFFCOPY
2077         OpMIPS64LoweredZero
2078         OpMIPS64LoweredMove
2079         OpMIPS64LoweredAtomicAnd32
2080         OpMIPS64LoweredAtomicOr32
2081         OpMIPS64LoweredAtomicLoad8
2082         OpMIPS64LoweredAtomicLoad32
2083         OpMIPS64LoweredAtomicLoad64
2084         OpMIPS64LoweredAtomicStore8
2085         OpMIPS64LoweredAtomicStore32
2086         OpMIPS64LoweredAtomicStore64
2087         OpMIPS64LoweredAtomicStorezero32
2088         OpMIPS64LoweredAtomicStorezero64
2089         OpMIPS64LoweredAtomicExchange32
2090         OpMIPS64LoweredAtomicExchange64
2091         OpMIPS64LoweredAtomicAdd32
2092         OpMIPS64LoweredAtomicAdd64
2093         OpMIPS64LoweredAtomicAddconst32
2094         OpMIPS64LoweredAtomicAddconst64
2095         OpMIPS64LoweredAtomicCas32
2096         OpMIPS64LoweredAtomicCas64
2097         OpMIPS64LoweredNilCheck
2098         OpMIPS64FPFlagTrue
2099         OpMIPS64FPFlagFalse
2100         OpMIPS64LoweredGetClosurePtr
2101         OpMIPS64LoweredGetCallerSP
2102         OpMIPS64LoweredGetCallerPC
2103         OpMIPS64LoweredWB
2104         OpMIPS64LoweredPanicBoundsA
2105         OpMIPS64LoweredPanicBoundsB
2106         OpMIPS64LoweredPanicBoundsC
2107
2108         OpPPC64ADD
2109         OpPPC64ADDCC
2110         OpPPC64ADDconst
2111         OpPPC64ADDCCconst
2112         OpPPC64FADD
2113         OpPPC64FADDS
2114         OpPPC64SUB
2115         OpPPC64SUBCC
2116         OpPPC64SUBFCconst
2117         OpPPC64FSUB
2118         OpPPC64FSUBS
2119         OpPPC64MULLD
2120         OpPPC64MULLW
2121         OpPPC64MULLDconst
2122         OpPPC64MULLWconst
2123         OpPPC64MADDLD
2124         OpPPC64MULHD
2125         OpPPC64MULHW
2126         OpPPC64MULHDU
2127         OpPPC64MULHWU
2128         OpPPC64FMUL
2129         OpPPC64FMULS
2130         OpPPC64FMADD
2131         OpPPC64FMADDS
2132         OpPPC64FMSUB
2133         OpPPC64FMSUBS
2134         OpPPC64SRAD
2135         OpPPC64SRAW
2136         OpPPC64SRD
2137         OpPPC64SRW
2138         OpPPC64SLD
2139         OpPPC64SLW
2140         OpPPC64ROTL
2141         OpPPC64ROTLW
2142         OpPPC64CLRLSLWI
2143         OpPPC64CLRLSLDI
2144         OpPPC64ADDC
2145         OpPPC64SUBC
2146         OpPPC64ADDCconst
2147         OpPPC64SUBCconst
2148         OpPPC64ADDE
2149         OpPPC64SUBE
2150         OpPPC64ADDZEzero
2151         OpPPC64SUBZEzero
2152         OpPPC64SRADconst
2153         OpPPC64SRAWconst
2154         OpPPC64SRDconst
2155         OpPPC64SRWconst
2156         OpPPC64SLDconst
2157         OpPPC64SLWconst
2158         OpPPC64ROTLconst
2159         OpPPC64ROTLWconst
2160         OpPPC64EXTSWSLconst
2161         OpPPC64RLWINM
2162         OpPPC64RLWNM
2163         OpPPC64RLWMI
2164         OpPPC64RLDICL
2165         OpPPC64RLDICR
2166         OpPPC64CNTLZD
2167         OpPPC64CNTLZDCC
2168         OpPPC64CNTLZW
2169         OpPPC64CNTTZD
2170         OpPPC64CNTTZW
2171         OpPPC64POPCNTD
2172         OpPPC64POPCNTW
2173         OpPPC64POPCNTB
2174         OpPPC64FDIV
2175         OpPPC64FDIVS
2176         OpPPC64DIVD
2177         OpPPC64DIVW
2178         OpPPC64DIVDU
2179         OpPPC64DIVWU
2180         OpPPC64MODUD
2181         OpPPC64MODSD
2182         OpPPC64MODUW
2183         OpPPC64MODSW
2184         OpPPC64FCTIDZ
2185         OpPPC64FCTIWZ
2186         OpPPC64FCFID
2187         OpPPC64FCFIDS
2188         OpPPC64FRSP
2189         OpPPC64MFVSRD
2190         OpPPC64MTVSRD
2191         OpPPC64AND
2192         OpPPC64ANDN
2193         OpPPC64ANDNCC
2194         OpPPC64ANDCC
2195         OpPPC64OR
2196         OpPPC64ORN
2197         OpPPC64ORCC
2198         OpPPC64NOR
2199         OpPPC64NORCC
2200         OpPPC64XOR
2201         OpPPC64XORCC
2202         OpPPC64EQV
2203         OpPPC64NEG
2204         OpPPC64NEGCC
2205         OpPPC64BRD
2206         OpPPC64BRW
2207         OpPPC64BRH
2208         OpPPC64FNEG
2209         OpPPC64FSQRT
2210         OpPPC64FSQRTS
2211         OpPPC64FFLOOR
2212         OpPPC64FCEIL
2213         OpPPC64FTRUNC
2214         OpPPC64FROUND
2215         OpPPC64FABS
2216         OpPPC64FNABS
2217         OpPPC64FCPSGN
2218         OpPPC64ORconst
2219         OpPPC64XORconst
2220         OpPPC64ANDCCconst
2221         OpPPC64MOVBreg
2222         OpPPC64MOVBZreg
2223         OpPPC64MOVHreg
2224         OpPPC64MOVHZreg
2225         OpPPC64MOVWreg
2226         OpPPC64MOVWZreg
2227         OpPPC64MOVBZload
2228         OpPPC64MOVHload
2229         OpPPC64MOVHZload
2230         OpPPC64MOVWload
2231         OpPPC64MOVWZload
2232         OpPPC64MOVDload
2233         OpPPC64MOVDBRload
2234         OpPPC64MOVWBRload
2235         OpPPC64MOVHBRload
2236         OpPPC64MOVBZloadidx
2237         OpPPC64MOVHloadidx
2238         OpPPC64MOVHZloadidx
2239         OpPPC64MOVWloadidx
2240         OpPPC64MOVWZloadidx
2241         OpPPC64MOVDloadidx
2242         OpPPC64MOVHBRloadidx
2243         OpPPC64MOVWBRloadidx
2244         OpPPC64MOVDBRloadidx
2245         OpPPC64FMOVDloadidx
2246         OpPPC64FMOVSloadidx
2247         OpPPC64DCBT
2248         OpPPC64MOVDBRstore
2249         OpPPC64MOVWBRstore
2250         OpPPC64MOVHBRstore
2251         OpPPC64FMOVDload
2252         OpPPC64FMOVSload
2253         OpPPC64MOVBstore
2254         OpPPC64MOVHstore
2255         OpPPC64MOVWstore
2256         OpPPC64MOVDstore
2257         OpPPC64FMOVDstore
2258         OpPPC64FMOVSstore
2259         OpPPC64MOVBstoreidx
2260         OpPPC64MOVHstoreidx
2261         OpPPC64MOVWstoreidx
2262         OpPPC64MOVDstoreidx
2263         OpPPC64FMOVDstoreidx
2264         OpPPC64FMOVSstoreidx
2265         OpPPC64MOVHBRstoreidx
2266         OpPPC64MOVWBRstoreidx
2267         OpPPC64MOVDBRstoreidx
2268         OpPPC64MOVBstorezero
2269         OpPPC64MOVHstorezero
2270         OpPPC64MOVWstorezero
2271         OpPPC64MOVDstorezero
2272         OpPPC64MOVDaddr
2273         OpPPC64MOVDconst
2274         OpPPC64FMOVDconst
2275         OpPPC64FMOVSconst
2276         OpPPC64FCMPU
2277         OpPPC64CMP
2278         OpPPC64CMPU
2279         OpPPC64CMPW
2280         OpPPC64CMPWU
2281         OpPPC64CMPconst
2282         OpPPC64CMPUconst
2283         OpPPC64CMPWconst
2284         OpPPC64CMPWUconst
2285         OpPPC64ISEL
2286         OpPPC64ISELZ
2287         OpPPC64SETBC
2288         OpPPC64SETBCR
2289         OpPPC64Equal
2290         OpPPC64NotEqual
2291         OpPPC64LessThan
2292         OpPPC64FLessThan
2293         OpPPC64LessEqual
2294         OpPPC64FLessEqual
2295         OpPPC64GreaterThan
2296         OpPPC64FGreaterThan
2297         OpPPC64GreaterEqual
2298         OpPPC64FGreaterEqual
2299         OpPPC64LoweredGetClosurePtr
2300         OpPPC64LoweredGetCallerSP
2301         OpPPC64LoweredGetCallerPC
2302         OpPPC64LoweredNilCheck
2303         OpPPC64LoweredRound32F
2304         OpPPC64LoweredRound64F
2305         OpPPC64CALLstatic
2306         OpPPC64CALLtail
2307         OpPPC64CALLclosure
2308         OpPPC64CALLinter
2309         OpPPC64LoweredZero
2310         OpPPC64LoweredZeroShort
2311         OpPPC64LoweredQuadZeroShort
2312         OpPPC64LoweredQuadZero
2313         OpPPC64LoweredMove
2314         OpPPC64LoweredMoveShort
2315         OpPPC64LoweredQuadMove
2316         OpPPC64LoweredQuadMoveShort
2317         OpPPC64LoweredAtomicStore8
2318         OpPPC64LoweredAtomicStore32
2319         OpPPC64LoweredAtomicStore64
2320         OpPPC64LoweredAtomicLoad8
2321         OpPPC64LoweredAtomicLoad32
2322         OpPPC64LoweredAtomicLoad64
2323         OpPPC64LoweredAtomicLoadPtr
2324         OpPPC64LoweredAtomicAdd32
2325         OpPPC64LoweredAtomicAdd64
2326         OpPPC64LoweredAtomicExchange32
2327         OpPPC64LoweredAtomicExchange64
2328         OpPPC64LoweredAtomicCas64
2329         OpPPC64LoweredAtomicCas32
2330         OpPPC64LoweredAtomicAnd8
2331         OpPPC64LoweredAtomicAnd32
2332         OpPPC64LoweredAtomicOr8
2333         OpPPC64LoweredAtomicOr32
2334         OpPPC64LoweredWB
2335         OpPPC64LoweredPubBarrier
2336         OpPPC64LoweredPanicBoundsA
2337         OpPPC64LoweredPanicBoundsB
2338         OpPPC64LoweredPanicBoundsC
2339         OpPPC64InvertFlags
2340         OpPPC64FlagEQ
2341         OpPPC64FlagLT
2342         OpPPC64FlagGT
2343
2344         OpRISCV64ADD
2345         OpRISCV64ADDI
2346         OpRISCV64ADDIW
2347         OpRISCV64NEG
2348         OpRISCV64NEGW
2349         OpRISCV64SUB
2350         OpRISCV64SUBW
2351         OpRISCV64MUL
2352         OpRISCV64MULW
2353         OpRISCV64MULH
2354         OpRISCV64MULHU
2355         OpRISCV64LoweredMuluhilo
2356         OpRISCV64LoweredMuluover
2357         OpRISCV64DIV
2358         OpRISCV64DIVU
2359         OpRISCV64DIVW
2360         OpRISCV64DIVUW
2361         OpRISCV64REM
2362         OpRISCV64REMU
2363         OpRISCV64REMW
2364         OpRISCV64REMUW
2365         OpRISCV64MOVaddr
2366         OpRISCV64MOVDconst
2367         OpRISCV64MOVBload
2368         OpRISCV64MOVHload
2369         OpRISCV64MOVWload
2370         OpRISCV64MOVDload
2371         OpRISCV64MOVBUload
2372         OpRISCV64MOVHUload
2373         OpRISCV64MOVWUload
2374         OpRISCV64MOVBstore
2375         OpRISCV64MOVHstore
2376         OpRISCV64MOVWstore
2377         OpRISCV64MOVDstore
2378         OpRISCV64MOVBstorezero
2379         OpRISCV64MOVHstorezero
2380         OpRISCV64MOVWstorezero
2381         OpRISCV64MOVDstorezero
2382         OpRISCV64MOVBreg
2383         OpRISCV64MOVHreg
2384         OpRISCV64MOVWreg
2385         OpRISCV64MOVDreg
2386         OpRISCV64MOVBUreg
2387         OpRISCV64MOVHUreg
2388         OpRISCV64MOVWUreg
2389         OpRISCV64MOVDnop
2390         OpRISCV64SLL
2391         OpRISCV64SRA
2392         OpRISCV64SRAW
2393         OpRISCV64SRL
2394         OpRISCV64SRLW
2395         OpRISCV64SLLI
2396         OpRISCV64SRAI
2397         OpRISCV64SRAIW
2398         OpRISCV64SRLI
2399         OpRISCV64SRLIW
2400         OpRISCV64XOR
2401         OpRISCV64XORI
2402         OpRISCV64OR
2403         OpRISCV64ORI
2404         OpRISCV64AND
2405         OpRISCV64ANDI
2406         OpRISCV64NOT
2407         OpRISCV64SEQZ
2408         OpRISCV64SNEZ
2409         OpRISCV64SLT
2410         OpRISCV64SLTI
2411         OpRISCV64SLTU
2412         OpRISCV64SLTIU
2413         OpRISCV64LoweredRound32F
2414         OpRISCV64LoweredRound64F
2415         OpRISCV64CALLstatic
2416         OpRISCV64CALLtail
2417         OpRISCV64CALLclosure
2418         OpRISCV64CALLinter
2419         OpRISCV64DUFFZERO
2420         OpRISCV64DUFFCOPY
2421         OpRISCV64LoweredZero
2422         OpRISCV64LoweredMove
2423         OpRISCV64LoweredAtomicLoad8
2424         OpRISCV64LoweredAtomicLoad32
2425         OpRISCV64LoweredAtomicLoad64
2426         OpRISCV64LoweredAtomicStore8
2427         OpRISCV64LoweredAtomicStore32
2428         OpRISCV64LoweredAtomicStore64
2429         OpRISCV64LoweredAtomicExchange32
2430         OpRISCV64LoweredAtomicExchange64
2431         OpRISCV64LoweredAtomicAdd32
2432         OpRISCV64LoweredAtomicAdd64
2433         OpRISCV64LoweredAtomicCas32
2434         OpRISCV64LoweredAtomicCas64
2435         OpRISCV64LoweredAtomicAnd32
2436         OpRISCV64LoweredAtomicOr32
2437         OpRISCV64LoweredNilCheck
2438         OpRISCV64LoweredGetClosurePtr
2439         OpRISCV64LoweredGetCallerSP
2440         OpRISCV64LoweredGetCallerPC
2441         OpRISCV64LoweredWB
2442         OpRISCV64LoweredPubBarrier
2443         OpRISCV64LoweredPanicBoundsA
2444         OpRISCV64LoweredPanicBoundsB
2445         OpRISCV64LoweredPanicBoundsC
2446         OpRISCV64FADDS
2447         OpRISCV64FSUBS
2448         OpRISCV64FMULS
2449         OpRISCV64FDIVS
2450         OpRISCV64FMADDS
2451         OpRISCV64FMSUBS
2452         OpRISCV64FNMADDS
2453         OpRISCV64FNMSUBS
2454         OpRISCV64FSQRTS
2455         OpRISCV64FNEGS
2456         OpRISCV64FMVSX
2457         OpRISCV64FCVTSW
2458         OpRISCV64FCVTSL
2459         OpRISCV64FCVTWS
2460         OpRISCV64FCVTLS
2461         OpRISCV64FMOVWload
2462         OpRISCV64FMOVWstore
2463         OpRISCV64FEQS
2464         OpRISCV64FNES
2465         OpRISCV64FLTS
2466         OpRISCV64FLES
2467         OpRISCV64FADDD
2468         OpRISCV64FSUBD
2469         OpRISCV64FMULD
2470         OpRISCV64FDIVD
2471         OpRISCV64FMADDD
2472         OpRISCV64FMSUBD
2473         OpRISCV64FNMADDD
2474         OpRISCV64FNMSUBD
2475         OpRISCV64FSQRTD
2476         OpRISCV64FNEGD
2477         OpRISCV64FABSD
2478         OpRISCV64FSGNJD
2479         OpRISCV64FMVDX
2480         OpRISCV64FCVTDW
2481         OpRISCV64FCVTDL
2482         OpRISCV64FCVTWD
2483         OpRISCV64FCVTLD
2484         OpRISCV64FCVTDS
2485         OpRISCV64FCVTSD
2486         OpRISCV64FMOVDload
2487         OpRISCV64FMOVDstore
2488         OpRISCV64FEQD
2489         OpRISCV64FNED
2490         OpRISCV64FLTD
2491         OpRISCV64FLED
2492
2493         OpS390XFADDS
2494         OpS390XFADD
2495         OpS390XFSUBS
2496         OpS390XFSUB
2497         OpS390XFMULS
2498         OpS390XFMUL
2499         OpS390XFDIVS
2500         OpS390XFDIV
2501         OpS390XFNEGS
2502         OpS390XFNEG
2503         OpS390XFMADDS
2504         OpS390XFMADD
2505         OpS390XFMSUBS
2506         OpS390XFMSUB
2507         OpS390XLPDFR
2508         OpS390XLNDFR
2509         OpS390XCPSDR
2510         OpS390XFIDBR
2511         OpS390XFMOVSload
2512         OpS390XFMOVDload
2513         OpS390XFMOVSconst
2514         OpS390XFMOVDconst
2515         OpS390XFMOVSloadidx
2516         OpS390XFMOVDloadidx
2517         OpS390XFMOVSstore
2518         OpS390XFMOVDstore
2519         OpS390XFMOVSstoreidx
2520         OpS390XFMOVDstoreidx
2521         OpS390XADD
2522         OpS390XADDW
2523         OpS390XADDconst
2524         OpS390XADDWconst
2525         OpS390XADDload
2526         OpS390XADDWload
2527         OpS390XSUB
2528         OpS390XSUBW
2529         OpS390XSUBconst
2530         OpS390XSUBWconst
2531         OpS390XSUBload
2532         OpS390XSUBWload
2533         OpS390XMULLD
2534         OpS390XMULLW
2535         OpS390XMULLDconst
2536         OpS390XMULLWconst
2537         OpS390XMULLDload
2538         OpS390XMULLWload
2539         OpS390XMULHD
2540         OpS390XMULHDU
2541         OpS390XDIVD
2542         OpS390XDIVW
2543         OpS390XDIVDU
2544         OpS390XDIVWU
2545         OpS390XMODD
2546         OpS390XMODW
2547         OpS390XMODDU
2548         OpS390XMODWU
2549         OpS390XAND
2550         OpS390XANDW
2551         OpS390XANDconst
2552         OpS390XANDWconst
2553         OpS390XANDload
2554         OpS390XANDWload
2555         OpS390XOR
2556         OpS390XORW
2557         OpS390XORconst
2558         OpS390XORWconst
2559         OpS390XORload
2560         OpS390XORWload
2561         OpS390XXOR
2562         OpS390XXORW
2563         OpS390XXORconst
2564         OpS390XXORWconst
2565         OpS390XXORload
2566         OpS390XXORWload
2567         OpS390XADDC
2568         OpS390XADDCconst
2569         OpS390XADDE
2570         OpS390XSUBC
2571         OpS390XSUBE
2572         OpS390XCMP
2573         OpS390XCMPW
2574         OpS390XCMPU
2575         OpS390XCMPWU
2576         OpS390XCMPconst
2577         OpS390XCMPWconst
2578         OpS390XCMPUconst
2579         OpS390XCMPWUconst
2580         OpS390XFCMPS
2581         OpS390XFCMP
2582         OpS390XLTDBR
2583         OpS390XLTEBR
2584         OpS390XSLD
2585         OpS390XSLW
2586         OpS390XSLDconst
2587         OpS390XSLWconst
2588         OpS390XSRD
2589         OpS390XSRW
2590         OpS390XSRDconst
2591         OpS390XSRWconst
2592         OpS390XSRAD
2593         OpS390XSRAW
2594         OpS390XSRADconst
2595         OpS390XSRAWconst
2596         OpS390XRLLG
2597         OpS390XRLL
2598         OpS390XRLLconst
2599         OpS390XRXSBG
2600         OpS390XRISBGZ
2601         OpS390XNEG
2602         OpS390XNEGW
2603         OpS390XNOT
2604         OpS390XNOTW
2605         OpS390XFSQRT
2606         OpS390XFSQRTS
2607         OpS390XLOCGR
2608         OpS390XMOVBreg
2609         OpS390XMOVBZreg
2610         OpS390XMOVHreg
2611         OpS390XMOVHZreg
2612         OpS390XMOVWreg
2613         OpS390XMOVWZreg
2614         OpS390XMOVDconst
2615         OpS390XLDGR
2616         OpS390XLGDR
2617         OpS390XCFDBRA
2618         OpS390XCGDBRA
2619         OpS390XCFEBRA
2620         OpS390XCGEBRA
2621         OpS390XCEFBRA
2622         OpS390XCDFBRA
2623         OpS390XCEGBRA
2624         OpS390XCDGBRA
2625         OpS390XCLFEBR
2626         OpS390XCLFDBR
2627         OpS390XCLGEBR
2628         OpS390XCLGDBR
2629         OpS390XCELFBR
2630         OpS390XCDLFBR
2631         OpS390XCELGBR
2632         OpS390XCDLGBR
2633         OpS390XLEDBR
2634         OpS390XLDEBR
2635         OpS390XMOVDaddr
2636         OpS390XMOVDaddridx
2637         OpS390XMOVBZload
2638         OpS390XMOVBload
2639         OpS390XMOVHZload
2640         OpS390XMOVHload
2641         OpS390XMOVWZload
2642         OpS390XMOVWload
2643         OpS390XMOVDload
2644         OpS390XMOVWBR
2645         OpS390XMOVDBR
2646         OpS390XMOVHBRload
2647         OpS390XMOVWBRload
2648         OpS390XMOVDBRload
2649         OpS390XMOVBstore
2650         OpS390XMOVHstore
2651         OpS390XMOVWstore
2652         OpS390XMOVDstore
2653         OpS390XMOVHBRstore
2654         OpS390XMOVWBRstore
2655         OpS390XMOVDBRstore
2656         OpS390XMVC
2657         OpS390XMOVBZloadidx
2658         OpS390XMOVBloadidx
2659         OpS390XMOVHZloadidx
2660         OpS390XMOVHloadidx
2661         OpS390XMOVWZloadidx
2662         OpS390XMOVWloadidx
2663         OpS390XMOVDloadidx
2664         OpS390XMOVHBRloadidx
2665         OpS390XMOVWBRloadidx
2666         OpS390XMOVDBRloadidx
2667         OpS390XMOVBstoreidx
2668         OpS390XMOVHstoreidx
2669         OpS390XMOVWstoreidx
2670         OpS390XMOVDstoreidx
2671         OpS390XMOVHBRstoreidx
2672         OpS390XMOVWBRstoreidx
2673         OpS390XMOVDBRstoreidx
2674         OpS390XMOVBstoreconst
2675         OpS390XMOVHstoreconst
2676         OpS390XMOVWstoreconst
2677         OpS390XMOVDstoreconst
2678         OpS390XCLEAR
2679         OpS390XCALLstatic
2680         OpS390XCALLtail
2681         OpS390XCALLclosure
2682         OpS390XCALLinter
2683         OpS390XInvertFlags
2684         OpS390XLoweredGetG
2685         OpS390XLoweredGetClosurePtr
2686         OpS390XLoweredGetCallerSP
2687         OpS390XLoweredGetCallerPC
2688         OpS390XLoweredNilCheck
2689         OpS390XLoweredRound32F
2690         OpS390XLoweredRound64F
2691         OpS390XLoweredWB
2692         OpS390XLoweredPanicBoundsA
2693         OpS390XLoweredPanicBoundsB
2694         OpS390XLoweredPanicBoundsC
2695         OpS390XFlagEQ
2696         OpS390XFlagLT
2697         OpS390XFlagGT
2698         OpS390XFlagOV
2699         OpS390XSYNC
2700         OpS390XMOVBZatomicload
2701         OpS390XMOVWZatomicload
2702         OpS390XMOVDatomicload
2703         OpS390XMOVBatomicstore
2704         OpS390XMOVWatomicstore
2705         OpS390XMOVDatomicstore
2706         OpS390XLAA
2707         OpS390XLAAG
2708         OpS390XAddTupleFirst32
2709         OpS390XAddTupleFirst64
2710         OpS390XLAN
2711         OpS390XLANfloor
2712         OpS390XLAO
2713         OpS390XLAOfloor
2714         OpS390XLoweredAtomicCas32
2715         OpS390XLoweredAtomicCas64
2716         OpS390XLoweredAtomicExchange32
2717         OpS390XLoweredAtomicExchange64
2718         OpS390XFLOGR
2719         OpS390XPOPCNT
2720         OpS390XMLGR
2721         OpS390XSumBytes2
2722         OpS390XSumBytes4
2723         OpS390XSumBytes8
2724         OpS390XSTMG2
2725         OpS390XSTMG3
2726         OpS390XSTMG4
2727         OpS390XSTM2
2728         OpS390XSTM3
2729         OpS390XSTM4
2730         OpS390XLoweredMove
2731         OpS390XLoweredZero
2732
2733         OpWasmLoweredStaticCall
2734         OpWasmLoweredTailCall
2735         OpWasmLoweredClosureCall
2736         OpWasmLoweredInterCall
2737         OpWasmLoweredAddr
2738         OpWasmLoweredMove
2739         OpWasmLoweredZero
2740         OpWasmLoweredGetClosurePtr
2741         OpWasmLoweredGetCallerPC
2742         OpWasmLoweredGetCallerSP
2743         OpWasmLoweredNilCheck
2744         OpWasmLoweredWB
2745         OpWasmLoweredConvert
2746         OpWasmSelect
2747         OpWasmI64Load8U
2748         OpWasmI64Load8S
2749         OpWasmI64Load16U
2750         OpWasmI64Load16S
2751         OpWasmI64Load32U
2752         OpWasmI64Load32S
2753         OpWasmI64Load
2754         OpWasmI64Store8
2755         OpWasmI64Store16
2756         OpWasmI64Store32
2757         OpWasmI64Store
2758         OpWasmF32Load
2759         OpWasmF64Load
2760         OpWasmF32Store
2761         OpWasmF64Store
2762         OpWasmI64Const
2763         OpWasmF32Const
2764         OpWasmF64Const
2765         OpWasmI64Eqz
2766         OpWasmI64Eq
2767         OpWasmI64Ne
2768         OpWasmI64LtS
2769         OpWasmI64LtU
2770         OpWasmI64GtS
2771         OpWasmI64GtU
2772         OpWasmI64LeS
2773         OpWasmI64LeU
2774         OpWasmI64GeS
2775         OpWasmI64GeU
2776         OpWasmF32Eq
2777         OpWasmF32Ne
2778         OpWasmF32Lt
2779         OpWasmF32Gt
2780         OpWasmF32Le
2781         OpWasmF32Ge
2782         OpWasmF64Eq
2783         OpWasmF64Ne
2784         OpWasmF64Lt
2785         OpWasmF64Gt
2786         OpWasmF64Le
2787         OpWasmF64Ge
2788         OpWasmI64Add
2789         OpWasmI64AddConst
2790         OpWasmI64Sub
2791         OpWasmI64Mul
2792         OpWasmI64DivS
2793         OpWasmI64DivU
2794         OpWasmI64RemS
2795         OpWasmI64RemU
2796         OpWasmI64And
2797         OpWasmI64Or
2798         OpWasmI64Xor
2799         OpWasmI64Shl
2800         OpWasmI64ShrS
2801         OpWasmI64ShrU
2802         OpWasmF32Neg
2803         OpWasmF32Add
2804         OpWasmF32Sub
2805         OpWasmF32Mul
2806         OpWasmF32Div
2807         OpWasmF64Neg
2808         OpWasmF64Add
2809         OpWasmF64Sub
2810         OpWasmF64Mul
2811         OpWasmF64Div
2812         OpWasmI64TruncSatF64S
2813         OpWasmI64TruncSatF64U
2814         OpWasmI64TruncSatF32S
2815         OpWasmI64TruncSatF32U
2816         OpWasmF32ConvertI64S
2817         OpWasmF32ConvertI64U
2818         OpWasmF64ConvertI64S
2819         OpWasmF64ConvertI64U
2820         OpWasmF32DemoteF64
2821         OpWasmF64PromoteF32
2822         OpWasmI64Extend8S
2823         OpWasmI64Extend16S
2824         OpWasmI64Extend32S
2825         OpWasmF32Sqrt
2826         OpWasmF32Trunc
2827         OpWasmF32Ceil
2828         OpWasmF32Floor
2829         OpWasmF32Nearest
2830         OpWasmF32Abs
2831         OpWasmF32Copysign
2832         OpWasmF64Sqrt
2833         OpWasmF64Trunc
2834         OpWasmF64Ceil
2835         OpWasmF64Floor
2836         OpWasmF64Nearest
2837         OpWasmF64Abs
2838         OpWasmF64Copysign
2839         OpWasmI64Ctz
2840         OpWasmI64Clz
2841         OpWasmI32Rotl
2842         OpWasmI64Rotl
2843         OpWasmI64Popcnt
2844
2845         OpAdd8
2846         OpAdd16
2847         OpAdd32
2848         OpAdd64
2849         OpAddPtr
2850         OpAdd32F
2851         OpAdd64F
2852         OpSub8
2853         OpSub16
2854         OpSub32
2855         OpSub64
2856         OpSubPtr
2857         OpSub32F
2858         OpSub64F
2859         OpMul8
2860         OpMul16
2861         OpMul32
2862         OpMul64
2863         OpMul32F
2864         OpMul64F
2865         OpDiv32F
2866         OpDiv64F
2867         OpHmul32
2868         OpHmul32u
2869         OpHmul64
2870         OpHmul64u
2871         OpMul32uhilo
2872         OpMul64uhilo
2873         OpMul32uover
2874         OpMul64uover
2875         OpAvg32u
2876         OpAvg64u
2877         OpDiv8
2878         OpDiv8u
2879         OpDiv16
2880         OpDiv16u
2881         OpDiv32
2882         OpDiv32u
2883         OpDiv64
2884         OpDiv64u
2885         OpDiv128u
2886         OpMod8
2887         OpMod8u
2888         OpMod16
2889         OpMod16u
2890         OpMod32
2891         OpMod32u
2892         OpMod64
2893         OpMod64u
2894         OpAnd8
2895         OpAnd16
2896         OpAnd32
2897         OpAnd64
2898         OpOr8
2899         OpOr16
2900         OpOr32
2901         OpOr64
2902         OpXor8
2903         OpXor16
2904         OpXor32
2905         OpXor64
2906         OpLsh8x8
2907         OpLsh8x16
2908         OpLsh8x32
2909         OpLsh8x64
2910         OpLsh16x8
2911         OpLsh16x16
2912         OpLsh16x32
2913         OpLsh16x64
2914         OpLsh32x8
2915         OpLsh32x16
2916         OpLsh32x32
2917         OpLsh32x64
2918         OpLsh64x8
2919         OpLsh64x16
2920         OpLsh64x32
2921         OpLsh64x64
2922         OpRsh8x8
2923         OpRsh8x16
2924         OpRsh8x32
2925         OpRsh8x64
2926         OpRsh16x8
2927         OpRsh16x16
2928         OpRsh16x32
2929         OpRsh16x64
2930         OpRsh32x8
2931         OpRsh32x16
2932         OpRsh32x32
2933         OpRsh32x64
2934         OpRsh64x8
2935         OpRsh64x16
2936         OpRsh64x32
2937         OpRsh64x64
2938         OpRsh8Ux8
2939         OpRsh8Ux16
2940         OpRsh8Ux32
2941         OpRsh8Ux64
2942         OpRsh16Ux8
2943         OpRsh16Ux16
2944         OpRsh16Ux32
2945         OpRsh16Ux64
2946         OpRsh32Ux8
2947         OpRsh32Ux16
2948         OpRsh32Ux32
2949         OpRsh32Ux64
2950         OpRsh64Ux8
2951         OpRsh64Ux16
2952         OpRsh64Ux32
2953         OpRsh64Ux64
2954         OpEq8
2955         OpEq16
2956         OpEq32
2957         OpEq64
2958         OpEqPtr
2959         OpEqInter
2960         OpEqSlice
2961         OpEq32F
2962         OpEq64F
2963         OpNeq8
2964         OpNeq16
2965         OpNeq32
2966         OpNeq64
2967         OpNeqPtr
2968         OpNeqInter
2969         OpNeqSlice
2970         OpNeq32F
2971         OpNeq64F
2972         OpLess8
2973         OpLess8U
2974         OpLess16
2975         OpLess16U
2976         OpLess32
2977         OpLess32U
2978         OpLess64
2979         OpLess64U
2980         OpLess32F
2981         OpLess64F
2982         OpLeq8
2983         OpLeq8U
2984         OpLeq16
2985         OpLeq16U
2986         OpLeq32
2987         OpLeq32U
2988         OpLeq64
2989         OpLeq64U
2990         OpLeq32F
2991         OpLeq64F
2992         OpCondSelect
2993         OpAndB
2994         OpOrB
2995         OpEqB
2996         OpNeqB
2997         OpNot
2998         OpNeg8
2999         OpNeg16
3000         OpNeg32
3001         OpNeg64
3002         OpNeg32F
3003         OpNeg64F
3004         OpCom8
3005         OpCom16
3006         OpCom32
3007         OpCom64
3008         OpCtz8
3009         OpCtz16
3010         OpCtz32
3011         OpCtz64
3012         OpCtz8NonZero
3013         OpCtz16NonZero
3014         OpCtz32NonZero
3015         OpCtz64NonZero
3016         OpBitLen8
3017         OpBitLen16
3018         OpBitLen32
3019         OpBitLen64
3020         OpBswap16
3021         OpBswap32
3022         OpBswap64
3023         OpBitRev8
3024         OpBitRev16
3025         OpBitRev32
3026         OpBitRev64
3027         OpPopCount8
3028         OpPopCount16
3029         OpPopCount32
3030         OpPopCount64
3031         OpRotateLeft64
3032         OpRotateLeft32
3033         OpRotateLeft16
3034         OpRotateLeft8
3035         OpSqrt
3036         OpSqrt32
3037         OpFloor
3038         OpCeil
3039         OpTrunc
3040         OpRound
3041         OpRoundToEven
3042         OpAbs
3043         OpCopysign
3044         OpMin64F
3045         OpMin32F
3046         OpMax64F
3047         OpMax32F
3048         OpFMA
3049         OpPhi
3050         OpCopy
3051         OpConvert
3052         OpConstBool
3053         OpConstString
3054         OpConstNil
3055         OpConst8
3056         OpConst16
3057         OpConst32
3058         OpConst64
3059         OpConst32F
3060         OpConst64F
3061         OpConstInterface
3062         OpConstSlice
3063         OpInitMem
3064         OpArg
3065         OpArgIntReg
3066         OpArgFloatReg
3067         OpAddr
3068         OpLocalAddr
3069         OpSP
3070         OpSB
3071         OpSPanchored
3072         OpLoad
3073         OpDereference
3074         OpStore
3075         OpMove
3076         OpZero
3077         OpStoreWB
3078         OpMoveWB
3079         OpZeroWB
3080         OpWBend
3081         OpWB
3082         OpHasCPUFeature
3083         OpPanicBounds
3084         OpPanicExtend
3085         OpClosureCall
3086         OpStaticCall
3087         OpInterCall
3088         OpTailCall
3089         OpClosureLECall
3090         OpStaticLECall
3091         OpInterLECall
3092         OpTailLECall
3093         OpSignExt8to16
3094         OpSignExt8to32
3095         OpSignExt8to64
3096         OpSignExt16to32
3097         OpSignExt16to64
3098         OpSignExt32to64
3099         OpZeroExt8to16
3100         OpZeroExt8to32
3101         OpZeroExt8to64
3102         OpZeroExt16to32
3103         OpZeroExt16to64
3104         OpZeroExt32to64
3105         OpTrunc16to8
3106         OpTrunc32to8
3107         OpTrunc32to16
3108         OpTrunc64to8
3109         OpTrunc64to16
3110         OpTrunc64to32
3111         OpCvt32to32F
3112         OpCvt32to64F
3113         OpCvt64to32F
3114         OpCvt64to64F
3115         OpCvt32Fto32
3116         OpCvt32Fto64
3117         OpCvt64Fto32
3118         OpCvt64Fto64
3119         OpCvt32Fto64F
3120         OpCvt64Fto32F
3121         OpCvtBoolToUint8
3122         OpRound32F
3123         OpRound64F
3124         OpIsNonNil
3125         OpIsInBounds
3126         OpIsSliceInBounds
3127         OpNilCheck
3128         OpGetG
3129         OpGetClosurePtr
3130         OpGetCallerPC
3131         OpGetCallerSP
3132         OpPtrIndex
3133         OpOffPtr
3134         OpSliceMake
3135         OpSlicePtr
3136         OpSliceLen
3137         OpSliceCap
3138         OpSlicePtrUnchecked
3139         OpComplexMake
3140         OpComplexReal
3141         OpComplexImag
3142         OpStringMake
3143         OpStringPtr
3144         OpStringLen
3145         OpIMake
3146         OpITab
3147         OpIData
3148         OpStructMake0
3149         OpStructMake1
3150         OpStructMake2
3151         OpStructMake3
3152         OpStructMake4
3153         OpStructSelect
3154         OpArrayMake0
3155         OpArrayMake1
3156         OpArraySelect
3157         OpStoreReg
3158         OpLoadReg
3159         OpFwdRef
3160         OpUnknown
3161         OpVarDef
3162         OpVarLive
3163         OpKeepAlive
3164         OpInlMark
3165         OpInt64Make
3166         OpInt64Hi
3167         OpInt64Lo
3168         OpAdd32carry
3169         OpAdd32withcarry
3170         OpSub32carry
3171         OpSub32withcarry
3172         OpAdd64carry
3173         OpSub64borrow
3174         OpSignmask
3175         OpZeromask
3176         OpSlicemask
3177         OpSpectreIndex
3178         OpSpectreSliceIndex
3179         OpCvt32Uto32F
3180         OpCvt32Uto64F
3181         OpCvt32Fto32U
3182         OpCvt64Fto32U
3183         OpCvt64Uto32F
3184         OpCvt64Uto64F
3185         OpCvt32Fto64U
3186         OpCvt64Fto64U
3187         OpSelect0
3188         OpSelect1
3189         OpSelectN
3190         OpSelectNAddr
3191         OpMakeResult
3192         OpAtomicLoad8
3193         OpAtomicLoad32
3194         OpAtomicLoad64
3195         OpAtomicLoadPtr
3196         OpAtomicLoadAcq32
3197         OpAtomicLoadAcq64
3198         OpAtomicStore8
3199         OpAtomicStore32
3200         OpAtomicStore64
3201         OpAtomicStorePtrNoWB
3202         OpAtomicStoreRel32
3203         OpAtomicStoreRel64
3204         OpAtomicExchange32
3205         OpAtomicExchange64
3206         OpAtomicAdd32
3207         OpAtomicAdd64
3208         OpAtomicCompareAndSwap32
3209         OpAtomicCompareAndSwap64
3210         OpAtomicCompareAndSwapRel32
3211         OpAtomicAnd8
3212         OpAtomicAnd32
3213         OpAtomicOr8
3214         OpAtomicOr32
3215         OpAtomicAdd32Variant
3216         OpAtomicAdd64Variant
3217         OpAtomicExchange32Variant
3218         OpAtomicExchange64Variant
3219         OpAtomicCompareAndSwap32Variant
3220         OpAtomicCompareAndSwap64Variant
3221         OpAtomicAnd8Variant
3222         OpAtomicAnd32Variant
3223         OpAtomicOr8Variant
3224         OpAtomicOr32Variant
3225         OpPubBarrier
3226         OpClobber
3227         OpClobberReg
3228         OpPrefetchCache
3229         OpPrefetchCacheStreamed
3230 )
3231
3232 var opcodeTable = [...]opInfo{
3233         {name: "OpInvalid"},
3234
3235         {
3236                 name:         "ADDSS",
3237                 argLen:       2,
3238                 commutative:  true,
3239                 resultInArg0: true,
3240                 asm:          x86.AADDSS,
3241                 reg: regInfo{
3242                         inputs: []inputInfo{
3243                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3244                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3245                         },
3246                         outputs: []outputInfo{
3247                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3248                         },
3249                 },
3250         },
3251         {
3252                 name:         "ADDSD",
3253                 argLen:       2,
3254                 commutative:  true,
3255                 resultInArg0: true,
3256                 asm:          x86.AADDSD,
3257                 reg: regInfo{
3258                         inputs: []inputInfo{
3259                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3260                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3261                         },
3262                         outputs: []outputInfo{
3263                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3264                         },
3265                 },
3266         },
3267         {
3268                 name:         "SUBSS",
3269                 argLen:       2,
3270                 resultInArg0: true,
3271                 asm:          x86.ASUBSS,
3272                 reg: regInfo{
3273                         inputs: []inputInfo{
3274                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3275                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3276                         },
3277                         outputs: []outputInfo{
3278                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3279                         },
3280                 },
3281         },
3282         {
3283                 name:         "SUBSD",
3284                 argLen:       2,
3285                 resultInArg0: true,
3286                 asm:          x86.ASUBSD,
3287                 reg: regInfo{
3288                         inputs: []inputInfo{
3289                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3290                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3291                         },
3292                         outputs: []outputInfo{
3293                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3294                         },
3295                 },
3296         },
3297         {
3298                 name:         "MULSS",
3299                 argLen:       2,
3300                 commutative:  true,
3301                 resultInArg0: true,
3302                 asm:          x86.AMULSS,
3303                 reg: regInfo{
3304                         inputs: []inputInfo{
3305                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3306                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3307                         },
3308                         outputs: []outputInfo{
3309                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3310                         },
3311                 },
3312         },
3313         {
3314                 name:         "MULSD",
3315                 argLen:       2,
3316                 commutative:  true,
3317                 resultInArg0: true,
3318                 asm:          x86.AMULSD,
3319                 reg: regInfo{
3320                         inputs: []inputInfo{
3321                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3322                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3323                         },
3324                         outputs: []outputInfo{
3325                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3326                         },
3327                 },
3328         },
3329         {
3330                 name:         "DIVSS",
3331                 argLen:       2,
3332                 resultInArg0: true,
3333                 asm:          x86.ADIVSS,
3334                 reg: regInfo{
3335                         inputs: []inputInfo{
3336                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3337                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3338                         },
3339                         outputs: []outputInfo{
3340                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3341                         },
3342                 },
3343         },
3344         {
3345                 name:         "DIVSD",
3346                 argLen:       2,
3347                 resultInArg0: true,
3348                 asm:          x86.ADIVSD,
3349                 reg: regInfo{
3350                         inputs: []inputInfo{
3351                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3352                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3353                         },
3354                         outputs: []outputInfo{
3355                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3356                         },
3357                 },
3358         },
3359         {
3360                 name:           "MOVSSload",
3361                 auxType:        auxSymOff,
3362                 argLen:         2,
3363                 faultOnNilArg0: true,
3364                 symEffect:      SymRead,
3365                 asm:            x86.AMOVSS,
3366                 reg: regInfo{
3367                         inputs: []inputInfo{
3368                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3369                         },
3370                         outputs: []outputInfo{
3371                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3372                         },
3373                 },
3374         },
3375         {
3376                 name:           "MOVSDload",
3377                 auxType:        auxSymOff,
3378                 argLen:         2,
3379                 faultOnNilArg0: true,
3380                 symEffect:      SymRead,
3381                 asm:            x86.AMOVSD,
3382                 reg: regInfo{
3383                         inputs: []inputInfo{
3384                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3385                         },
3386                         outputs: []outputInfo{
3387                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3388                         },
3389                 },
3390         },
3391         {
3392                 name:              "MOVSSconst",
3393                 auxType:           auxFloat32,
3394                 argLen:            0,
3395                 rematerializeable: true,
3396                 asm:               x86.AMOVSS,
3397                 reg: regInfo{
3398                         outputs: []outputInfo{
3399                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3400                         },
3401                 },
3402         },
3403         {
3404                 name:              "MOVSDconst",
3405                 auxType:           auxFloat64,
3406                 argLen:            0,
3407                 rematerializeable: true,
3408                 asm:               x86.AMOVSD,
3409                 reg: regInfo{
3410                         outputs: []outputInfo{
3411                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3412                         },
3413                 },
3414         },
3415         {
3416                 name:      "MOVSSloadidx1",
3417                 auxType:   auxSymOff,
3418                 argLen:    3,
3419                 symEffect: SymRead,
3420                 asm:       x86.AMOVSS,
3421                 reg: regInfo{
3422                         inputs: []inputInfo{
3423                                 {1, 255},   // AX CX DX BX SP BP SI DI
3424                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3425                         },
3426                         outputs: []outputInfo{
3427                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3428                         },
3429                 },
3430         },
3431         {
3432                 name:      "MOVSSloadidx4",
3433                 auxType:   auxSymOff,
3434                 argLen:    3,
3435                 symEffect: SymRead,
3436                 asm:       x86.AMOVSS,
3437                 reg: regInfo{
3438                         inputs: []inputInfo{
3439                                 {1, 255},   // AX CX DX BX SP BP SI DI
3440                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3441                         },
3442                         outputs: []outputInfo{
3443                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3444                         },
3445                 },
3446         },
3447         {
3448                 name:      "MOVSDloadidx1",
3449                 auxType:   auxSymOff,
3450                 argLen:    3,
3451                 symEffect: SymRead,
3452                 asm:       x86.AMOVSD,
3453                 reg: regInfo{
3454                         inputs: []inputInfo{
3455                                 {1, 255},   // AX CX DX BX SP BP SI DI
3456                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3457                         },
3458                         outputs: []outputInfo{
3459                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3460                         },
3461                 },
3462         },
3463         {
3464                 name:      "MOVSDloadidx8",
3465                 auxType:   auxSymOff,
3466                 argLen:    3,
3467                 symEffect: SymRead,
3468                 asm:       x86.AMOVSD,
3469                 reg: regInfo{
3470                         inputs: []inputInfo{
3471                                 {1, 255},   // AX CX DX BX SP BP SI DI
3472                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3473                         },
3474                         outputs: []outputInfo{
3475                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3476                         },
3477                 },
3478         },
3479         {
3480                 name:           "MOVSSstore",
3481                 auxType:        auxSymOff,
3482                 argLen:         3,
3483                 faultOnNilArg0: true,
3484                 symEffect:      SymWrite,
3485                 asm:            x86.AMOVSS,
3486                 reg: regInfo{
3487                         inputs: []inputInfo{
3488                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3489                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3490                         },
3491                 },
3492         },
3493         {
3494                 name:           "MOVSDstore",
3495                 auxType:        auxSymOff,
3496                 argLen:         3,
3497                 faultOnNilArg0: true,
3498                 symEffect:      SymWrite,
3499                 asm:            x86.AMOVSD,
3500                 reg: regInfo{
3501                         inputs: []inputInfo{
3502                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3503                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3504                         },
3505                 },
3506         },
3507         {
3508                 name:      "MOVSSstoreidx1",
3509                 auxType:   auxSymOff,
3510                 argLen:    4,
3511                 symEffect: SymWrite,
3512                 asm:       x86.AMOVSS,
3513                 reg: regInfo{
3514                         inputs: []inputInfo{
3515                                 {1, 255},   // AX CX DX BX SP BP SI DI
3516                                 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3517                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3518                         },
3519                 },
3520         },
3521         {
3522                 name:      "MOVSSstoreidx4",
3523                 auxType:   auxSymOff,
3524                 argLen:    4,
3525                 symEffect: SymWrite,
3526                 asm:       x86.AMOVSS,
3527                 reg: regInfo{
3528                         inputs: []inputInfo{
3529                                 {1, 255},   // AX CX DX BX SP BP SI DI
3530                                 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3531                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3532                         },
3533                 },
3534         },
3535         {
3536                 name:      "MOVSDstoreidx1",
3537                 auxType:   auxSymOff,
3538                 argLen:    4,
3539                 symEffect: SymWrite,
3540                 asm:       x86.AMOVSD,
3541                 reg: regInfo{
3542                         inputs: []inputInfo{
3543                                 {1, 255},   // AX CX DX BX SP BP SI DI
3544                                 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3545                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3546                         },
3547                 },
3548         },
3549         {
3550                 name:      "MOVSDstoreidx8",
3551                 auxType:   auxSymOff,
3552                 argLen:    4,
3553                 symEffect: SymWrite,
3554                 asm:       x86.AMOVSD,
3555                 reg: regInfo{
3556                         inputs: []inputInfo{
3557                                 {1, 255},   // AX CX DX BX SP BP SI DI
3558                                 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3559                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
3560                         },
3561                 },
3562         },
3563         {
3564                 name:           "ADDSSload",
3565                 auxType:        auxSymOff,
3566                 argLen:         3,
3567                 resultInArg0:   true,
3568                 faultOnNilArg1: true,
3569                 symEffect:      SymRead,
3570                 asm:            x86.AADDSS,
3571                 reg: regInfo{
3572                         inputs: []inputInfo{
3573                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3574                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3575                         },
3576                         outputs: []outputInfo{
3577                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3578                         },
3579                 },
3580         },
3581         {
3582                 name:           "ADDSDload",
3583                 auxType:        auxSymOff,
3584                 argLen:         3,
3585                 resultInArg0:   true,
3586                 faultOnNilArg1: true,
3587                 symEffect:      SymRead,
3588                 asm:            x86.AADDSD,
3589                 reg: regInfo{
3590                         inputs: []inputInfo{
3591                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3592                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3593                         },
3594                         outputs: []outputInfo{
3595                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3596                         },
3597                 },
3598         },
3599         {
3600                 name:           "SUBSSload",
3601                 auxType:        auxSymOff,
3602                 argLen:         3,
3603                 resultInArg0:   true,
3604                 faultOnNilArg1: true,
3605                 symEffect:      SymRead,
3606                 asm:            x86.ASUBSS,
3607                 reg: regInfo{
3608                         inputs: []inputInfo{
3609                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3610                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3611                         },
3612                         outputs: []outputInfo{
3613                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3614                         },
3615                 },
3616         },
3617         {
3618                 name:           "SUBSDload",
3619                 auxType:        auxSymOff,
3620                 argLen:         3,
3621                 resultInArg0:   true,
3622                 faultOnNilArg1: true,
3623                 symEffect:      SymRead,
3624                 asm:            x86.ASUBSD,
3625                 reg: regInfo{
3626                         inputs: []inputInfo{
3627                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3628                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3629                         },
3630                         outputs: []outputInfo{
3631                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3632                         },
3633                 },
3634         },
3635         {
3636                 name:           "MULSSload",
3637                 auxType:        auxSymOff,
3638                 argLen:         3,
3639                 resultInArg0:   true,
3640                 faultOnNilArg1: true,
3641                 symEffect:      SymRead,
3642                 asm:            x86.AMULSS,
3643                 reg: regInfo{
3644                         inputs: []inputInfo{
3645                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3646                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3647                         },
3648                         outputs: []outputInfo{
3649                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3650                         },
3651                 },
3652         },
3653         {
3654                 name:           "MULSDload",
3655                 auxType:        auxSymOff,
3656                 argLen:         3,
3657                 resultInArg0:   true,
3658                 faultOnNilArg1: true,
3659                 symEffect:      SymRead,
3660                 asm:            x86.AMULSD,
3661                 reg: regInfo{
3662                         inputs: []inputInfo{
3663                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3664                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3665                         },
3666                         outputs: []outputInfo{
3667                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3668                         },
3669                 },
3670         },
3671         {
3672                 name:           "DIVSSload",
3673                 auxType:        auxSymOff,
3674                 argLen:         3,
3675                 resultInArg0:   true,
3676                 faultOnNilArg1: true,
3677                 symEffect:      SymRead,
3678                 asm:            x86.ADIVSS,
3679                 reg: regInfo{
3680                         inputs: []inputInfo{
3681                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3682                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3683                         },
3684                         outputs: []outputInfo{
3685                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3686                         },
3687                 },
3688         },
3689         {
3690                 name:           "DIVSDload",
3691                 auxType:        auxSymOff,
3692                 argLen:         3,
3693                 resultInArg0:   true,
3694                 faultOnNilArg1: true,
3695                 symEffect:      SymRead,
3696                 asm:            x86.ADIVSD,
3697                 reg: regInfo{
3698                         inputs: []inputInfo{
3699                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3700                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
3701                         },
3702                         outputs: []outputInfo{
3703                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3704                         },
3705                 },
3706         },
3707         {
3708                 name:         "ADDL",
3709                 argLen:       2,
3710                 commutative:  true,
3711                 clobberFlags: true,
3712                 asm:          x86.AADDL,
3713                 reg: regInfo{
3714                         inputs: []inputInfo{
3715                                 {1, 239}, // AX CX DX BX BP SI DI
3716                                 {0, 255}, // AX CX DX BX SP BP SI DI
3717                         },
3718                         outputs: []outputInfo{
3719                                 {0, 239}, // AX CX DX BX BP SI DI
3720                         },
3721                 },
3722         },
3723         {
3724                 name:         "ADDLconst",
3725                 auxType:      auxInt32,
3726                 argLen:       1,
3727                 clobberFlags: true,
3728                 asm:          x86.AADDL,
3729                 reg: regInfo{
3730                         inputs: []inputInfo{
3731                                 {0, 255}, // AX CX DX BX SP BP SI DI
3732                         },
3733                         outputs: []outputInfo{
3734                                 {0, 239}, // AX CX DX BX BP SI DI
3735                         },
3736                 },
3737         },
3738         {
3739                 name:         "ADDLcarry",
3740                 argLen:       2,
3741                 commutative:  true,
3742                 resultInArg0: true,
3743                 asm:          x86.AADDL,
3744                 reg: regInfo{
3745                         inputs: []inputInfo{
3746                                 {0, 239}, // AX CX DX BX BP SI DI
3747                                 {1, 239}, // AX CX DX BX BP SI DI
3748                         },
3749                         outputs: []outputInfo{
3750                                 {1, 0},
3751                                 {0, 239}, // AX CX DX BX BP SI DI
3752                         },
3753                 },
3754         },
3755         {
3756                 name:         "ADDLconstcarry",
3757                 auxType:      auxInt32,
3758                 argLen:       1,
3759                 resultInArg0: true,
3760                 asm:          x86.AADDL,
3761                 reg: regInfo{
3762                         inputs: []inputInfo{
3763                                 {0, 239}, // AX CX DX BX BP SI DI
3764                         },
3765                         outputs: []outputInfo{
3766                                 {1, 0},
3767                                 {0, 239}, // AX CX DX BX BP SI DI
3768                         },
3769                 },
3770         },
3771         {
3772                 name:         "ADCL",
3773                 argLen:       3,
3774                 commutative:  true,
3775                 resultInArg0: true,
3776                 clobberFlags: true,
3777                 asm:          x86.AADCL,
3778                 reg: regInfo{
3779                         inputs: []inputInfo{
3780                                 {0, 239}, // AX CX DX BX BP SI DI
3781                                 {1, 239}, // AX CX DX BX BP SI DI
3782                         },
3783                         outputs: []outputInfo{
3784                                 {0, 239}, // AX CX DX BX BP SI DI
3785                         },
3786                 },
3787         },
3788         {
3789                 name:         "ADCLconst",
3790                 auxType:      auxInt32,
3791                 argLen:       2,
3792                 resultInArg0: true,
3793                 clobberFlags: true,
3794                 asm:          x86.AADCL,
3795                 reg: regInfo{
3796                         inputs: []inputInfo{
3797                                 {0, 239}, // AX CX DX BX BP SI DI
3798                         },
3799                         outputs: []outputInfo{
3800                                 {0, 239}, // AX CX DX BX BP SI DI
3801                         },
3802                 },
3803         },
3804         {
3805                 name:         "SUBL",
3806                 argLen:       2,
3807                 resultInArg0: true,
3808                 clobberFlags: true,
3809                 asm:          x86.ASUBL,
3810                 reg: regInfo{
3811                         inputs: []inputInfo{
3812                                 {0, 239}, // AX CX DX BX BP SI DI
3813                                 {1, 239}, // AX CX DX BX BP SI DI
3814                         },
3815                         outputs: []outputInfo{
3816                                 {0, 239}, // AX CX DX BX BP SI DI
3817                         },
3818                 },
3819         },
3820         {
3821                 name:         "SUBLconst",
3822                 auxType:      auxInt32,
3823                 argLen:       1,
3824                 resultInArg0: true,
3825                 clobberFlags: true,
3826                 asm:          x86.ASUBL,
3827                 reg: regInfo{
3828                         inputs: []inputInfo{
3829                                 {0, 239}, // AX CX DX BX BP SI DI
3830                         },
3831                         outputs: []outputInfo{
3832                                 {0, 239}, // AX CX DX BX BP SI DI
3833                         },
3834                 },
3835         },
3836         {
3837                 name:         "SUBLcarry",
3838                 argLen:       2,
3839                 resultInArg0: true,
3840                 asm:          x86.ASUBL,
3841                 reg: regInfo{
3842                         inputs: []inputInfo{
3843                                 {0, 239}, // AX CX DX BX BP SI DI
3844                                 {1, 239}, // AX CX DX BX BP SI DI
3845                         },
3846                         outputs: []outputInfo{
3847                                 {1, 0},
3848                                 {0, 239}, // AX CX DX BX BP SI DI
3849                         },
3850                 },
3851         },
3852         {
3853                 name:         "SUBLconstcarry",
3854                 auxType:      auxInt32,
3855                 argLen:       1,
3856                 resultInArg0: true,
3857                 asm:          x86.ASUBL,
3858                 reg: regInfo{
3859                         inputs: []inputInfo{
3860                                 {0, 239}, // AX CX DX BX BP SI DI
3861                         },
3862                         outputs: []outputInfo{
3863                                 {1, 0},
3864                                 {0, 239}, // AX CX DX BX BP SI DI
3865                         },
3866                 },
3867         },
3868         {
3869                 name:         "SBBL",
3870                 argLen:       3,
3871                 resultInArg0: true,
3872                 clobberFlags: true,
3873                 asm:          x86.ASBBL,
3874                 reg: regInfo{
3875                         inputs: []inputInfo{
3876                                 {0, 239}, // AX CX DX BX BP SI DI
3877                                 {1, 239}, // AX CX DX BX BP SI DI
3878                         },
3879                         outputs: []outputInfo{
3880                                 {0, 239}, // AX CX DX BX BP SI DI
3881                         },
3882                 },
3883         },
3884         {
3885                 name:         "SBBLconst",
3886                 auxType:      auxInt32,
3887                 argLen:       2,
3888                 resultInArg0: true,
3889                 clobberFlags: true,
3890                 asm:          x86.ASBBL,
3891                 reg: regInfo{
3892                         inputs: []inputInfo{
3893                                 {0, 239}, // AX CX DX BX BP SI DI
3894                         },
3895                         outputs: []outputInfo{
3896                                 {0, 239}, // AX CX DX BX BP SI DI
3897                         },
3898                 },
3899         },
3900         {
3901                 name:         "MULL",
3902                 argLen:       2,
3903                 commutative:  true,
3904                 resultInArg0: true,
3905                 clobberFlags: true,
3906                 asm:          x86.AIMULL,
3907                 reg: regInfo{
3908                         inputs: []inputInfo{
3909                                 {0, 239}, // AX CX DX BX BP SI DI
3910                                 {1, 239}, // AX CX DX BX BP SI DI
3911                         },
3912                         outputs: []outputInfo{
3913                                 {0, 239}, // AX CX DX BX BP SI DI
3914                         },
3915                 },
3916         },
3917         {
3918                 name:         "MULLconst",
3919                 auxType:      auxInt32,
3920                 argLen:       1,
3921                 clobberFlags: true,
3922                 asm:          x86.AIMUL3L,
3923                 reg: regInfo{
3924                         inputs: []inputInfo{
3925                                 {0, 239}, // AX CX DX BX BP SI DI
3926                         },
3927                         outputs: []outputInfo{
3928                                 {0, 239}, // AX CX DX BX BP SI DI
3929                         },
3930                 },
3931         },
3932         {
3933                 name:         "MULLU",
3934                 argLen:       2,
3935                 commutative:  true,
3936                 clobberFlags: true,
3937                 asm:          x86.AMULL,
3938                 reg: regInfo{
3939                         inputs: []inputInfo{
3940                                 {0, 1},   // AX
3941                                 {1, 255}, // AX CX DX BX SP BP SI DI
3942                         },
3943                         clobbers: 4, // DX
3944                         outputs: []outputInfo{
3945                                 {1, 0},
3946                                 {0, 1}, // AX
3947                         },
3948                 },
3949         },
3950         {
3951                 name:         "HMULL",
3952                 argLen:       2,
3953                 commutative:  true,
3954                 clobberFlags: true,
3955                 asm:          x86.AIMULL,
3956                 reg: regInfo{
3957                         inputs: []inputInfo{
3958                                 {0, 1},   // AX
3959                                 {1, 255}, // AX CX DX BX SP BP SI DI
3960                         },
3961                         clobbers: 1, // AX
3962                         outputs: []outputInfo{
3963                                 {0, 4}, // DX
3964                         },
3965                 },
3966         },
3967         {
3968                 name:         "HMULLU",
3969                 argLen:       2,
3970                 commutative:  true,
3971                 clobberFlags: true,
3972                 asm:          x86.AMULL,
3973                 reg: regInfo{
3974                         inputs: []inputInfo{
3975                                 {0, 1},   // AX
3976                                 {1, 255}, // AX CX DX BX SP BP SI DI
3977                         },
3978                         clobbers: 1, // AX
3979                         outputs: []outputInfo{
3980                                 {0, 4}, // DX
3981                         },
3982                 },
3983         },
3984         {
3985                 name:         "MULLQU",
3986                 argLen:       2,
3987                 commutative:  true,
3988                 clobberFlags: true,
3989                 asm:          x86.AMULL,
3990                 reg: regInfo{
3991                         inputs: []inputInfo{
3992                                 {0, 1},   // AX
3993                                 {1, 255}, // AX CX DX BX SP BP SI DI
3994                         },
3995                         outputs: []outputInfo{
3996                                 {0, 4}, // DX
3997                                 {1, 1}, // AX
3998                         },
3999                 },
4000         },
4001         {
4002                 name:         "AVGLU",
4003                 argLen:       2,
4004                 commutative:  true,
4005                 resultInArg0: true,
4006                 clobberFlags: true,
4007                 reg: regInfo{
4008                         inputs: []inputInfo{
4009                                 {0, 239}, // AX CX DX BX BP SI DI
4010                                 {1, 239}, // AX CX DX BX BP SI DI
4011                         },
4012                         outputs: []outputInfo{
4013                                 {0, 239}, // AX CX DX BX BP SI DI
4014                         },
4015                 },
4016         },
4017         {
4018                 name:         "DIVL",
4019                 auxType:      auxBool,
4020                 argLen:       2,
4021                 clobberFlags: true,
4022                 asm:          x86.AIDIVL,
4023                 reg: regInfo{
4024                         inputs: []inputInfo{
4025                                 {0, 1},   // AX
4026                                 {1, 251}, // AX CX BX SP BP SI DI
4027                         },
4028                         clobbers: 4, // DX
4029                         outputs: []outputInfo{
4030                                 {0, 1}, // AX
4031                         },
4032                 },
4033         },
4034         {
4035                 name:         "DIVW",
4036                 auxType:      auxBool,
4037                 argLen:       2,
4038                 clobberFlags: true,
4039                 asm:          x86.AIDIVW,
4040                 reg: regInfo{
4041                         inputs: []inputInfo{
4042                                 {0, 1},   // AX
4043                                 {1, 251}, // AX CX BX SP BP SI DI
4044                         },
4045                         clobbers: 4, // DX
4046                         outputs: []outputInfo{
4047                                 {0, 1}, // AX
4048                         },
4049                 },
4050         },
4051         {
4052                 name:         "DIVLU",
4053                 argLen:       2,
4054                 clobberFlags: true,
4055                 asm:          x86.ADIVL,
4056                 reg: regInfo{
4057                         inputs: []inputInfo{
4058                                 {0, 1},   // AX
4059                                 {1, 251}, // AX CX BX SP BP SI DI
4060                         },
4061                         clobbers: 4, // DX
4062                         outputs: []outputInfo{
4063                                 {0, 1}, // AX
4064                         },
4065                 },
4066         },
4067         {
4068                 name:         "DIVWU",
4069                 argLen:       2,
4070                 clobberFlags: true,
4071                 asm:          x86.ADIVW,
4072                 reg: regInfo{
4073                         inputs: []inputInfo{
4074                                 {0, 1},   // AX
4075                                 {1, 251}, // AX CX BX SP BP SI DI
4076                         },
4077                         clobbers: 4, // DX
4078                         outputs: []outputInfo{
4079                                 {0, 1}, // AX
4080                         },
4081                 },
4082         },
4083         {
4084                 name:         "MODL",
4085                 auxType:      auxBool,
4086                 argLen:       2,
4087                 clobberFlags: true,
4088                 asm:          x86.AIDIVL,
4089                 reg: regInfo{
4090                         inputs: []inputInfo{
4091                                 {0, 1},   // AX
4092                                 {1, 251}, // AX CX BX SP BP SI DI
4093                         },
4094                         clobbers: 1, // AX
4095                         outputs: []outputInfo{
4096                                 {0, 4}, // DX
4097                         },
4098                 },
4099         },
4100         {
4101                 name:         "MODW",
4102                 auxType:      auxBool,
4103                 argLen:       2,
4104                 clobberFlags: true,
4105                 asm:          x86.AIDIVW,
4106                 reg: regInfo{
4107                         inputs: []inputInfo{
4108                                 {0, 1},   // AX
4109                                 {1, 251}, // AX CX BX SP BP SI DI
4110                         },
4111                         clobbers: 1, // AX
4112                         outputs: []outputInfo{
4113                                 {0, 4}, // DX
4114                         },
4115                 },
4116         },
4117         {
4118                 name:         "MODLU",
4119                 argLen:       2,
4120                 clobberFlags: true,
4121                 asm:          x86.ADIVL,
4122                 reg: regInfo{
4123                         inputs: []inputInfo{
4124                                 {0, 1},   // AX
4125                                 {1, 251}, // AX CX BX SP BP SI DI
4126                         },
4127                         clobbers: 1, // AX
4128                         outputs: []outputInfo{
4129                                 {0, 4}, // DX
4130                         },
4131                 },
4132         },
4133         {
4134                 name:         "MODWU",
4135                 argLen:       2,
4136                 clobberFlags: true,
4137                 asm:          x86.ADIVW,
4138                 reg: regInfo{
4139                         inputs: []inputInfo{
4140                                 {0, 1},   // AX
4141                                 {1, 251}, // AX CX BX SP BP SI DI
4142                         },
4143                         clobbers: 1, // AX
4144                         outputs: []outputInfo{
4145                                 {0, 4}, // DX
4146                         },
4147                 },
4148         },
4149         {
4150                 name:         "ANDL",
4151                 argLen:       2,
4152                 commutative:  true,
4153                 resultInArg0: true,
4154                 clobberFlags: true,
4155                 asm:          x86.AANDL,
4156                 reg: regInfo{
4157                         inputs: []inputInfo{
4158                                 {0, 239}, // AX CX DX BX BP SI DI
4159                                 {1, 239}, // AX CX DX BX BP SI DI
4160                         },
4161                         outputs: []outputInfo{
4162                                 {0, 239}, // AX CX DX BX BP SI DI
4163                         },
4164                 },
4165         },
4166         {
4167                 name:         "ANDLconst",
4168                 auxType:      auxInt32,
4169                 argLen:       1,
4170                 resultInArg0: true,
4171                 clobberFlags: true,
4172                 asm:          x86.AANDL,
4173                 reg: regInfo{
4174                         inputs: []inputInfo{
4175                                 {0, 239}, // AX CX DX BX BP SI DI
4176                         },
4177                         outputs: []outputInfo{
4178                                 {0, 239}, // AX CX DX BX BP SI DI
4179                         },
4180                 },
4181         },
4182         {
4183                 name:         "ORL",
4184                 argLen:       2,
4185                 commutative:  true,
4186                 resultInArg0: true,
4187                 clobberFlags: true,
4188                 asm:          x86.AORL,
4189                 reg: regInfo{
4190                         inputs: []inputInfo{
4191                                 {0, 239}, // AX CX DX BX BP SI DI
4192                                 {1, 239}, // AX CX DX BX BP SI DI
4193                         },
4194                         outputs: []outputInfo{
4195                                 {0, 239}, // AX CX DX BX BP SI DI
4196                         },
4197                 },
4198         },
4199         {
4200                 name:         "ORLconst",
4201                 auxType:      auxInt32,
4202                 argLen:       1,
4203                 resultInArg0: true,
4204                 clobberFlags: true,
4205                 asm:          x86.AORL,
4206                 reg: regInfo{
4207                         inputs: []inputInfo{
4208                                 {0, 239}, // AX CX DX BX BP SI DI
4209                         },
4210                         outputs: []outputInfo{
4211                                 {0, 239}, // AX CX DX BX BP SI DI
4212                         },
4213                 },
4214         },
4215         {
4216                 name:         "XORL",
4217                 argLen:       2,
4218                 commutative:  true,
4219                 resultInArg0: true,
4220                 clobberFlags: true,
4221                 asm:          x86.AXORL,
4222                 reg: regInfo{
4223                         inputs: []inputInfo{
4224                                 {0, 239}, // AX CX DX BX BP SI DI
4225                                 {1, 239}, // AX CX DX BX BP SI DI
4226                         },
4227                         outputs: []outputInfo{
4228                                 {0, 239}, // AX CX DX BX BP SI DI
4229                         },
4230                 },
4231         },
4232         {
4233                 name:         "XORLconst",
4234                 auxType:      auxInt32,
4235                 argLen:       1,
4236                 resultInArg0: true,
4237                 clobberFlags: true,
4238                 asm:          x86.AXORL,
4239                 reg: regInfo{
4240                         inputs: []inputInfo{
4241                                 {0, 239}, // AX CX DX BX BP SI DI
4242                         },
4243                         outputs: []outputInfo{
4244                                 {0, 239}, // AX CX DX BX BP SI DI
4245                         },
4246                 },
4247         },
4248         {
4249                 name:   "CMPL",
4250                 argLen: 2,
4251                 asm:    x86.ACMPL,
4252                 reg: regInfo{
4253                         inputs: []inputInfo{
4254                                 {0, 255}, // AX CX DX BX SP BP SI DI
4255                                 {1, 255}, // AX CX DX BX SP BP SI DI
4256                         },
4257                 },
4258         },
4259         {
4260                 name:   "CMPW",
4261                 argLen: 2,
4262                 asm:    x86.ACMPW,
4263                 reg: regInfo{
4264                         inputs: []inputInfo{
4265                                 {0, 255}, // AX CX DX BX SP BP SI DI
4266                                 {1, 255}, // AX CX DX BX SP BP SI DI
4267                         },
4268                 },
4269         },
4270         {
4271                 name:   "CMPB",
4272                 argLen: 2,
4273                 asm:    x86.ACMPB,
4274                 reg: regInfo{
4275                         inputs: []inputInfo{
4276                                 {0, 255}, // AX CX DX BX SP BP SI DI
4277                                 {1, 255}, // AX CX DX BX SP BP SI DI
4278                         },
4279                 },
4280         },
4281         {
4282                 name:    "CMPLconst",
4283                 auxType: auxInt32,
4284                 argLen:  1,
4285                 asm:     x86.ACMPL,
4286                 reg: regInfo{
4287                         inputs: []inputInfo{
4288                                 {0, 255}, // AX CX DX BX SP BP SI DI
4289                         },
4290                 },
4291         },
4292         {
4293                 name:    "CMPWconst",
4294                 auxType: auxInt16,
4295                 argLen:  1,
4296                 asm:     x86.ACMPW,
4297                 reg: regInfo{
4298                         inputs: []inputInfo{
4299                                 {0, 255}, // AX CX DX BX SP BP SI DI
4300                         },
4301                 },
4302         },
4303         {
4304                 name:    "CMPBconst",
4305                 auxType: auxInt8,
4306                 argLen:  1,
4307                 asm:     x86.ACMPB,
4308                 reg: regInfo{
4309                         inputs: []inputInfo{
4310                                 {0, 255}, // AX CX DX BX SP BP SI DI
4311                         },
4312                 },
4313         },
4314         {
4315                 name:           "CMPLload",
4316                 auxType:        auxSymOff,
4317                 argLen:         3,
4318                 faultOnNilArg0: true,
4319                 symEffect:      SymRead,
4320                 asm:            x86.ACMPL,
4321                 reg: regInfo{
4322                         inputs: []inputInfo{
4323                                 {1, 255},   // AX CX DX BX SP BP SI DI
4324                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4325                         },
4326                 },
4327         },
4328         {
4329                 name:           "CMPWload",
4330                 auxType:        auxSymOff,
4331                 argLen:         3,
4332                 faultOnNilArg0: true,
4333                 symEffect:      SymRead,
4334                 asm:            x86.ACMPW,
4335                 reg: regInfo{
4336                         inputs: []inputInfo{
4337                                 {1, 255},   // AX CX DX BX SP BP SI DI
4338                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4339                         },
4340                 },
4341         },
4342         {
4343                 name:           "CMPBload",
4344                 auxType:        auxSymOff,
4345                 argLen:         3,
4346                 faultOnNilArg0: true,
4347                 symEffect:      SymRead,
4348                 asm:            x86.ACMPB,
4349                 reg: regInfo{
4350                         inputs: []inputInfo{
4351                                 {1, 255},   // AX CX DX BX SP BP SI DI
4352                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4353                         },
4354                 },
4355         },
4356         {
4357                 name:           "CMPLconstload",
4358                 auxType:        auxSymValAndOff,
4359                 argLen:         2,
4360                 faultOnNilArg0: true,
4361                 symEffect:      SymRead,
4362                 asm:            x86.ACMPL,
4363                 reg: regInfo{
4364                         inputs: []inputInfo{
4365                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4366                         },
4367                 },
4368         },
4369         {
4370                 name:           "CMPWconstload",
4371                 auxType:        auxSymValAndOff,
4372                 argLen:         2,
4373                 faultOnNilArg0: true,
4374                 symEffect:      SymRead,
4375                 asm:            x86.ACMPW,
4376                 reg: regInfo{
4377                         inputs: []inputInfo{
4378                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4379                         },
4380                 },
4381         },
4382         {
4383                 name:           "CMPBconstload",
4384                 auxType:        auxSymValAndOff,
4385                 argLen:         2,
4386                 faultOnNilArg0: true,
4387                 symEffect:      SymRead,
4388                 asm:            x86.ACMPB,
4389                 reg: regInfo{
4390                         inputs: []inputInfo{
4391                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
4392                         },
4393                 },
4394         },
4395         {
4396                 name:   "UCOMISS",
4397                 argLen: 2,
4398                 asm:    x86.AUCOMISS,
4399                 reg: regInfo{
4400                         inputs: []inputInfo{
4401                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4402                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4403                         },
4404                 },
4405         },
4406         {
4407                 name:   "UCOMISD",
4408                 argLen: 2,
4409                 asm:    x86.AUCOMISD,
4410                 reg: regInfo{
4411                         inputs: []inputInfo{
4412                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4413                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4414                         },
4415                 },
4416         },
4417         {
4418                 name:        "TESTL",
4419                 argLen:      2,
4420                 commutative: true,
4421                 asm:         x86.ATESTL,
4422                 reg: regInfo{
4423                         inputs: []inputInfo{
4424                                 {0, 255}, // AX CX DX BX SP BP SI DI
4425                                 {1, 255}, // AX CX DX BX SP BP SI DI
4426                         },
4427                 },
4428         },
4429         {
4430                 name:        "TESTW",
4431                 argLen:      2,
4432                 commutative: true,
4433                 asm:         x86.ATESTW,
4434                 reg: regInfo{
4435                         inputs: []inputInfo{
4436                                 {0, 255}, // AX CX DX BX SP BP SI DI
4437                                 {1, 255}, // AX CX DX BX SP BP SI DI
4438                         },
4439                 },
4440         },
4441         {
4442                 name:        "TESTB",
4443                 argLen:      2,
4444                 commutative: true,
4445                 asm:         x86.ATESTB,
4446                 reg: regInfo{
4447                         inputs: []inputInfo{
4448                                 {0, 255}, // AX CX DX BX SP BP SI DI
4449                                 {1, 255}, // AX CX DX BX SP BP SI DI
4450                         },
4451                 },
4452         },
4453         {
4454                 name:    "TESTLconst",
4455                 auxType: auxInt32,
4456                 argLen:  1,
4457                 asm:     x86.ATESTL,
4458                 reg: regInfo{
4459                         inputs: []inputInfo{
4460                                 {0, 255}, // AX CX DX BX SP BP SI DI
4461                         },
4462                 },
4463         },
4464         {
4465                 name:    "TESTWconst",
4466                 auxType: auxInt16,
4467                 argLen:  1,
4468                 asm:     x86.ATESTW,
4469                 reg: regInfo{
4470                         inputs: []inputInfo{
4471                                 {0, 255}, // AX CX DX BX SP BP SI DI
4472                         },
4473                 },
4474         },
4475         {
4476                 name:    "TESTBconst",
4477                 auxType: auxInt8,
4478                 argLen:  1,
4479                 asm:     x86.ATESTB,
4480                 reg: regInfo{
4481                         inputs: []inputInfo{
4482                                 {0, 255}, // AX CX DX BX SP BP SI DI
4483                         },
4484                 },
4485         },
4486         {
4487                 name:         "SHLL",
4488                 argLen:       2,
4489                 resultInArg0: true,
4490                 clobberFlags: true,
4491                 asm:          x86.ASHLL,
4492                 reg: regInfo{
4493                         inputs: []inputInfo{
4494                                 {1, 2},   // CX
4495                                 {0, 239}, // AX CX DX BX BP SI DI
4496                         },
4497                         outputs: []outputInfo{
4498                                 {0, 239}, // AX CX DX BX BP SI DI
4499                         },
4500                 },
4501         },
4502         {
4503                 name:         "SHLLconst",
4504                 auxType:      auxInt32,
4505                 argLen:       1,
4506                 resultInArg0: true,
4507                 clobberFlags: true,
4508                 asm:          x86.ASHLL,
4509                 reg: regInfo{
4510                         inputs: []inputInfo{
4511                                 {0, 239}, // AX CX DX BX BP SI DI
4512                         },
4513                         outputs: []outputInfo{
4514                                 {0, 239}, // AX CX DX BX BP SI DI
4515                         },
4516                 },
4517         },
4518         {
4519                 name:         "SHRL",
4520                 argLen:       2,
4521                 resultInArg0: true,
4522                 clobberFlags: true,
4523                 asm:          x86.ASHRL,
4524                 reg: regInfo{
4525                         inputs: []inputInfo{
4526                                 {1, 2},   // CX
4527                                 {0, 239}, // AX CX DX BX BP SI DI
4528                         },
4529                         outputs: []outputInfo{
4530                                 {0, 239}, // AX CX DX BX BP SI DI
4531                         },
4532                 },
4533         },
4534         {
4535                 name:         "SHRW",
4536                 argLen:       2,
4537                 resultInArg0: true,
4538                 clobberFlags: true,
4539                 asm:          x86.ASHRW,
4540                 reg: regInfo{
4541                         inputs: []inputInfo{
4542                                 {1, 2},   // CX
4543                                 {0, 239}, // AX CX DX BX BP SI DI
4544                         },
4545                         outputs: []outputInfo{
4546                                 {0, 239}, // AX CX DX BX BP SI DI
4547                         },
4548                 },
4549         },
4550         {
4551                 name:         "SHRB",
4552                 argLen:       2,
4553                 resultInArg0: true,
4554                 clobberFlags: true,
4555                 asm:          x86.ASHRB,
4556                 reg: regInfo{
4557                         inputs: []inputInfo{
4558                                 {1, 2},   // CX
4559                                 {0, 239}, // AX CX DX BX BP SI DI
4560                         },
4561                         outputs: []outputInfo{
4562                                 {0, 239}, // AX CX DX BX BP SI DI
4563                         },
4564                 },
4565         },
4566         {
4567                 name:         "SHRLconst",
4568                 auxType:      auxInt32,
4569                 argLen:       1,
4570                 resultInArg0: true,
4571                 clobberFlags: true,
4572                 asm:          x86.ASHRL,
4573                 reg: regInfo{
4574                         inputs: []inputInfo{
4575                                 {0, 239}, // AX CX DX BX BP SI DI
4576                         },
4577                         outputs: []outputInfo{
4578                                 {0, 239}, // AX CX DX BX BP SI DI
4579                         },
4580                 },
4581         },
4582         {
4583                 name:         "SHRWconst",
4584                 auxType:      auxInt16,
4585                 argLen:       1,
4586                 resultInArg0: true,
4587                 clobberFlags: true,
4588                 asm:          x86.ASHRW,
4589                 reg: regInfo{
4590                         inputs: []inputInfo{
4591                                 {0, 239}, // AX CX DX BX BP SI DI
4592                         },
4593                         outputs: []outputInfo{
4594                                 {0, 239}, // AX CX DX BX BP SI DI
4595                         },
4596                 },
4597         },
4598         {
4599                 name:         "SHRBconst",
4600                 auxType:      auxInt8,
4601                 argLen:       1,
4602                 resultInArg0: true,
4603                 clobberFlags: true,
4604                 asm:          x86.ASHRB,
4605                 reg: regInfo{
4606                         inputs: []inputInfo{
4607                                 {0, 239}, // AX CX DX BX BP SI DI
4608                         },
4609                         outputs: []outputInfo{
4610                                 {0, 239}, // AX CX DX BX BP SI DI
4611                         },
4612                 },
4613         },
4614         {
4615                 name:         "SARL",
4616                 argLen:       2,
4617                 resultInArg0: true,
4618                 clobberFlags: true,
4619                 asm:          x86.ASARL,
4620                 reg: regInfo{
4621                         inputs: []inputInfo{
4622                                 {1, 2},   // CX
4623                                 {0, 239}, // AX CX DX BX BP SI DI
4624                         },
4625                         outputs: []outputInfo{
4626                                 {0, 239}, // AX CX DX BX BP SI DI
4627                         },
4628                 },
4629         },
4630         {
4631                 name:         "SARW",
4632                 argLen:       2,
4633                 resultInArg0: true,
4634                 clobberFlags: true,
4635                 asm:          x86.ASARW,
4636                 reg: regInfo{
4637                         inputs: []inputInfo{
4638                                 {1, 2},   // CX
4639                                 {0, 239}, // AX CX DX BX BP SI DI
4640                         },
4641                         outputs: []outputInfo{
4642                                 {0, 239}, // AX CX DX BX BP SI DI
4643                         },
4644                 },
4645         },
4646         {
4647                 name:         "SARB",
4648                 argLen:       2,
4649                 resultInArg0: true,
4650                 clobberFlags: true,
4651                 asm:          x86.ASARB,
4652                 reg: regInfo{
4653                         inputs: []inputInfo{
4654                                 {1, 2},   // CX
4655                                 {0, 239}, // AX CX DX BX BP SI DI
4656                         },
4657                         outputs: []outputInfo{
4658                                 {0, 239}, // AX CX DX BX BP SI DI
4659                         },
4660                 },
4661         },
4662         {
4663                 name:         "SARLconst",
4664                 auxType:      auxInt32,
4665                 argLen:       1,
4666                 resultInArg0: true,
4667                 clobberFlags: true,
4668                 asm:          x86.ASARL,
4669                 reg: regInfo{
4670                         inputs: []inputInfo{
4671                                 {0, 239}, // AX CX DX BX BP SI DI
4672                         },
4673                         outputs: []outputInfo{
4674                                 {0, 239}, // AX CX DX BX BP SI DI
4675                         },
4676                 },
4677         },
4678         {
4679                 name:         "SARWconst",
4680                 auxType:      auxInt16,
4681                 argLen:       1,
4682                 resultInArg0: true,
4683                 clobberFlags: true,
4684                 asm:          x86.ASARW,
4685                 reg: regInfo{
4686                         inputs: []inputInfo{
4687                                 {0, 239}, // AX CX DX BX BP SI DI
4688                         },
4689                         outputs: []outputInfo{
4690                                 {0, 239}, // AX CX DX BX BP SI DI
4691                         },
4692                 },
4693         },
4694         {
4695                 name:         "SARBconst",
4696                 auxType:      auxInt8,
4697                 argLen:       1,
4698                 resultInArg0: true,
4699                 clobberFlags: true,
4700                 asm:          x86.ASARB,
4701                 reg: regInfo{
4702                         inputs: []inputInfo{
4703                                 {0, 239}, // AX CX DX BX BP SI DI
4704                         },
4705                         outputs: []outputInfo{
4706                                 {0, 239}, // AX CX DX BX BP SI DI
4707                         },
4708                 },
4709         },
4710         {
4711                 name:         "ROLL",
4712                 argLen:       2,
4713                 resultInArg0: true,
4714                 clobberFlags: true,
4715                 asm:          x86.AROLL,
4716                 reg: regInfo{
4717                         inputs: []inputInfo{
4718                                 {1, 2},   // CX
4719                                 {0, 239}, // AX CX DX BX BP SI DI
4720                         },
4721                         outputs: []outputInfo{
4722                                 {0, 239}, // AX CX DX BX BP SI DI
4723                         },
4724                 },
4725         },
4726         {
4727                 name:         "ROLW",
4728                 argLen:       2,
4729                 resultInArg0: true,
4730                 clobberFlags: true,
4731                 asm:          x86.AROLW,
4732                 reg: regInfo{
4733                         inputs: []inputInfo{
4734                                 {1, 2},   // CX
4735                                 {0, 239}, // AX CX DX BX BP SI DI
4736                         },
4737                         outputs: []outputInfo{
4738                                 {0, 239}, // AX CX DX BX BP SI DI
4739                         },
4740                 },
4741         },
4742         {
4743                 name:         "ROLB",
4744                 argLen:       2,
4745                 resultInArg0: true,
4746                 clobberFlags: true,
4747                 asm:          x86.AROLB,
4748                 reg: regInfo{
4749                         inputs: []inputInfo{
4750                                 {1, 2},   // CX
4751                                 {0, 239}, // AX CX DX BX BP SI DI
4752                         },
4753                         outputs: []outputInfo{
4754                                 {0, 239}, // AX CX DX BX BP SI DI
4755                         },
4756                 },
4757         },
4758         {
4759                 name:         "ROLLconst",
4760                 auxType:      auxInt32,
4761                 argLen:       1,
4762                 resultInArg0: true,
4763                 clobberFlags: true,
4764                 asm:          x86.AROLL,
4765                 reg: regInfo{
4766                         inputs: []inputInfo{
4767                                 {0, 239}, // AX CX DX BX BP SI DI
4768                         },
4769                         outputs: []outputInfo{
4770                                 {0, 239}, // AX CX DX BX BP SI DI
4771                         },
4772                 },
4773         },
4774         {
4775                 name:         "ROLWconst",
4776                 auxType:      auxInt16,
4777                 argLen:       1,
4778                 resultInArg0: true,
4779                 clobberFlags: true,
4780                 asm:          x86.AROLW,
4781                 reg: regInfo{
4782                         inputs: []inputInfo{
4783                                 {0, 239}, // AX CX DX BX BP SI DI
4784                         },
4785                         outputs: []outputInfo{
4786                                 {0, 239}, // AX CX DX BX BP SI DI
4787                         },
4788                 },
4789         },
4790         {
4791                 name:         "ROLBconst",
4792                 auxType:      auxInt8,
4793                 argLen:       1,
4794                 resultInArg0: true,
4795                 clobberFlags: true,
4796                 asm:          x86.AROLB,
4797                 reg: regInfo{
4798                         inputs: []inputInfo{
4799                                 {0, 239}, // AX CX DX BX BP SI DI
4800                         },
4801                         outputs: []outputInfo{
4802                                 {0, 239}, // AX CX DX BX BP SI DI
4803                         },
4804                 },
4805         },
4806         {
4807                 name:           "ADDLload",
4808                 auxType:        auxSymOff,
4809                 argLen:         3,
4810                 resultInArg0:   true,
4811                 clobberFlags:   true,
4812                 faultOnNilArg1: true,
4813                 symEffect:      SymRead,
4814                 asm:            x86.AADDL,
4815                 reg: regInfo{
4816                         inputs: []inputInfo{
4817                                 {0, 239},   // AX CX DX BX BP SI DI
4818                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4819                         },
4820                         outputs: []outputInfo{
4821                                 {0, 239}, // AX CX DX BX BP SI DI
4822                         },
4823                 },
4824         },
4825         {
4826                 name:           "SUBLload",
4827                 auxType:        auxSymOff,
4828                 argLen:         3,
4829                 resultInArg0:   true,
4830                 clobberFlags:   true,
4831                 faultOnNilArg1: true,
4832                 symEffect:      SymRead,
4833                 asm:            x86.ASUBL,
4834                 reg: regInfo{
4835                         inputs: []inputInfo{
4836                                 {0, 239},   // AX CX DX BX BP SI DI
4837                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4838                         },
4839                         outputs: []outputInfo{
4840                                 {0, 239}, // AX CX DX BX BP SI DI
4841                         },
4842                 },
4843         },
4844         {
4845                 name:           "MULLload",
4846                 auxType:        auxSymOff,
4847                 argLen:         3,
4848                 resultInArg0:   true,
4849                 clobberFlags:   true,
4850                 faultOnNilArg1: true,
4851                 symEffect:      SymRead,
4852                 asm:            x86.AIMULL,
4853                 reg: regInfo{
4854                         inputs: []inputInfo{
4855                                 {0, 239},   // AX CX DX BX BP SI DI
4856                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4857                         },
4858                         outputs: []outputInfo{
4859                                 {0, 239}, // AX CX DX BX BP SI DI
4860                         },
4861                 },
4862         },
4863         {
4864                 name:           "ANDLload",
4865                 auxType:        auxSymOff,
4866                 argLen:         3,
4867                 resultInArg0:   true,
4868                 clobberFlags:   true,
4869                 faultOnNilArg1: true,
4870                 symEffect:      SymRead,
4871                 asm:            x86.AANDL,
4872                 reg: regInfo{
4873                         inputs: []inputInfo{
4874                                 {0, 239},   // AX CX DX BX BP SI DI
4875                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4876                         },
4877                         outputs: []outputInfo{
4878                                 {0, 239}, // AX CX DX BX BP SI DI
4879                         },
4880                 },
4881         },
4882         {
4883                 name:           "ORLload",
4884                 auxType:        auxSymOff,
4885                 argLen:         3,
4886                 resultInArg0:   true,
4887                 clobberFlags:   true,
4888                 faultOnNilArg1: true,
4889                 symEffect:      SymRead,
4890                 asm:            x86.AORL,
4891                 reg: regInfo{
4892                         inputs: []inputInfo{
4893                                 {0, 239},   // AX CX DX BX BP SI DI
4894                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4895                         },
4896                         outputs: []outputInfo{
4897                                 {0, 239}, // AX CX DX BX BP SI DI
4898                         },
4899                 },
4900         },
4901         {
4902                 name:           "XORLload",
4903                 auxType:        auxSymOff,
4904                 argLen:         3,
4905                 resultInArg0:   true,
4906                 clobberFlags:   true,
4907                 faultOnNilArg1: true,
4908                 symEffect:      SymRead,
4909                 asm:            x86.AXORL,
4910                 reg: regInfo{
4911                         inputs: []inputInfo{
4912                                 {0, 239},   // AX CX DX BX BP SI DI
4913                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4914                         },
4915                         outputs: []outputInfo{
4916                                 {0, 239}, // AX CX DX BX BP SI DI
4917                         },
4918                 },
4919         },
4920         {
4921                 name:         "ADDLloadidx4",
4922                 auxType:      auxSymOff,
4923                 argLen:       4,
4924                 resultInArg0: true,
4925                 clobberFlags: true,
4926                 symEffect:    SymRead,
4927                 asm:          x86.AADDL,
4928                 reg: regInfo{
4929                         inputs: []inputInfo{
4930                                 {0, 239},   // AX CX DX BX BP SI DI
4931                                 {2, 255},   // AX CX DX BX SP BP SI DI
4932                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4933                         },
4934                         outputs: []outputInfo{
4935                                 {0, 239}, // AX CX DX BX BP SI DI
4936                         },
4937                 },
4938         },
4939         {
4940                 name:         "SUBLloadidx4",
4941                 auxType:      auxSymOff,
4942                 argLen:       4,
4943                 resultInArg0: true,
4944                 clobberFlags: true,
4945                 symEffect:    SymRead,
4946                 asm:          x86.ASUBL,
4947                 reg: regInfo{
4948                         inputs: []inputInfo{
4949                                 {0, 239},   // AX CX DX BX BP SI DI
4950                                 {2, 255},   // AX CX DX BX SP BP SI DI
4951                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4952                         },
4953                         outputs: []outputInfo{
4954                                 {0, 239}, // AX CX DX BX BP SI DI
4955                         },
4956                 },
4957         },
4958         {
4959                 name:         "MULLloadidx4",
4960                 auxType:      auxSymOff,
4961                 argLen:       4,
4962                 resultInArg0: true,
4963                 clobberFlags: true,
4964                 symEffect:    SymRead,
4965                 asm:          x86.AIMULL,
4966                 reg: regInfo{
4967                         inputs: []inputInfo{
4968                                 {0, 239},   // AX CX DX BX BP SI DI
4969                                 {2, 255},   // AX CX DX BX SP BP SI DI
4970                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4971                         },
4972                         outputs: []outputInfo{
4973                                 {0, 239}, // AX CX DX BX BP SI DI
4974                         },
4975                 },
4976         },
4977         {
4978                 name:         "ANDLloadidx4",
4979                 auxType:      auxSymOff,
4980                 argLen:       4,
4981                 resultInArg0: true,
4982                 clobberFlags: true,
4983                 symEffect:    SymRead,
4984                 asm:          x86.AANDL,
4985                 reg: regInfo{
4986                         inputs: []inputInfo{
4987                                 {0, 239},   // AX CX DX BX BP SI DI
4988                                 {2, 255},   // AX CX DX BX SP BP SI DI
4989                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
4990                         },
4991                         outputs: []outputInfo{
4992                                 {0, 239}, // AX CX DX BX BP SI DI
4993                         },
4994                 },
4995         },
4996         {
4997                 name:         "ORLloadidx4",
4998                 auxType:      auxSymOff,
4999                 argLen:       4,
5000                 resultInArg0: true,
5001                 clobberFlags: true,
5002                 symEffect:    SymRead,
5003                 asm:          x86.AORL,
5004                 reg: regInfo{
5005                         inputs: []inputInfo{
5006                                 {0, 239},   // AX CX DX BX BP SI DI
5007                                 {2, 255},   // AX CX DX BX SP BP SI DI
5008                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
5009                         },
5010                         outputs: []outputInfo{
5011                                 {0, 239}, // AX CX DX BX BP SI DI
5012                         },
5013                 },
5014         },
5015         {
5016                 name:         "XORLloadidx4",
5017                 auxType:      auxSymOff,
5018                 argLen:       4,
5019                 resultInArg0: true,
5020                 clobberFlags: true,
5021                 symEffect:    SymRead,
5022                 asm:          x86.AXORL,
5023                 reg: regInfo{
5024                         inputs: []inputInfo{
5025                                 {0, 239},   // AX CX DX BX BP SI DI
5026                                 {2, 255},   // AX CX DX BX SP BP SI DI
5027                                 {1, 65791}, // AX CX DX BX SP BP SI DI SB
5028                         },
5029                         outputs: []outputInfo{
5030                                 {0, 239}, // AX CX DX BX BP SI DI
5031                         },
5032                 },
5033         },
5034         {
5035                 name:         "NEGL",
5036                 argLen:       1,
5037                 resultInArg0: true,
5038                 clobberFlags: true,
5039                 asm:          x86.ANEGL,
5040                 reg: regInfo{
5041                         inputs: []inputInfo{
5042                                 {0, 239}, // AX CX DX BX BP SI DI
5043                         },
5044                         outputs: []outputInfo{
5045                                 {0, 239}, // AX CX DX BX BP SI DI
5046                         },
5047                 },
5048         },
5049         {
5050                 name:         "NOTL",
5051                 argLen:       1,
5052                 resultInArg0: true,
5053                 asm:          x86.ANOTL,
5054                 reg: regInfo{
5055                         inputs: []inputInfo{
5056                                 {0, 239}, // AX CX DX BX BP SI DI
5057                         },
5058                         outputs: []outputInfo{
5059                                 {0, 239}, // AX CX DX BX BP SI DI
5060                         },
5061                 },
5062         },
5063         {
5064                 name:         "BSFL",
5065                 argLen:       1,
5066                 clobberFlags: true,
5067                 asm:          x86.ABSFL,
5068                 reg: regInfo{
5069                         inputs: []inputInfo{
5070                                 {0, 239}, // AX CX DX BX BP SI DI
5071                         },
5072                         outputs: []outputInfo{
5073                                 {0, 239}, // AX CX DX BX BP SI DI
5074                         },
5075                 },
5076         },
5077         {
5078                 name:         "BSFW",
5079                 argLen:       1,
5080                 clobberFlags: true,
5081                 asm:          x86.ABSFW,
5082                 reg: regInfo{
5083                         inputs: []inputInfo{
5084                                 {0, 239}, // AX CX DX BX BP SI DI
5085                         },
5086                         outputs: []outputInfo{
5087                                 {0, 239}, // AX CX DX BX BP SI DI
5088                         },
5089                 },
5090         },
5091         {
5092                 name:         "LoweredCtz32",
5093                 argLen:       1,
5094                 clobberFlags: true,
5095                 reg: regInfo{
5096                         inputs: []inputInfo{
5097                                 {0, 239}, // AX CX DX BX BP SI DI
5098                         },
5099                         outputs: []outputInfo{
5100                                 {0, 239}, // AX CX DX BX BP SI DI
5101                         },
5102                 },
5103         },
5104         {
5105                 name:         "BSRL",
5106                 argLen:       1,
5107                 clobberFlags: true,
5108                 asm:          x86.ABSRL,
5109                 reg: regInfo{
5110                         inputs: []inputInfo{
5111                                 {0, 239}, // AX CX DX BX BP SI DI
5112                         },
5113                         outputs: []outputInfo{
5114                                 {0, 239}, // AX CX DX BX BP SI DI
5115                         },
5116                 },
5117         },
5118         {
5119                 name:         "BSRW",
5120                 argLen:       1,
5121                 clobberFlags: true,
5122                 asm:          x86.ABSRW,
5123                 reg: regInfo{
5124                         inputs: []inputInfo{
5125                                 {0, 239}, // AX CX DX BX BP SI DI
5126                         },
5127                         outputs: []outputInfo{
5128                                 {0, 239}, // AX CX DX BX BP SI DI
5129                         },
5130                 },
5131         },
5132         {
5133                 name:         "BSWAPL",
5134                 argLen:       1,
5135                 resultInArg0: true,
5136                 asm:          x86.ABSWAPL,
5137                 reg: regInfo{
5138                         inputs: []inputInfo{
5139                                 {0, 239}, // AX CX DX BX BP SI DI
5140                         },
5141                         outputs: []outputInfo{
5142                                 {0, 239}, // AX CX DX BX BP SI DI
5143                         },
5144                 },
5145         },
5146         {
5147                 name:   "SQRTSD",
5148                 argLen: 1,
5149                 asm:    x86.ASQRTSD,
5150                 reg: regInfo{
5151                         inputs: []inputInfo{
5152                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5153                         },
5154                         outputs: []outputInfo{
5155                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5156                         },
5157                 },
5158         },
5159         {
5160                 name:   "SQRTSS",
5161                 argLen: 1,
5162                 asm:    x86.ASQRTSS,
5163                 reg: regInfo{
5164                         inputs: []inputInfo{
5165                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5166                         },
5167                         outputs: []outputInfo{
5168                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5169                         },
5170                 },
5171         },
5172         {
5173                 name:   "SBBLcarrymask",
5174                 argLen: 1,
5175                 asm:    x86.ASBBL,
5176                 reg: regInfo{
5177                         outputs: []outputInfo{
5178                                 {0, 239}, // AX CX DX BX BP SI DI
5179                         },
5180                 },
5181         },
5182         {
5183                 name:   "SETEQ",
5184                 argLen: 1,
5185                 asm:    x86.ASETEQ,
5186                 reg: regInfo{
5187                         outputs: []outputInfo{
5188                                 {0, 239}, // AX CX DX BX BP SI DI
5189                         },
5190                 },
5191         },
5192         {
5193                 name:   "SETNE",
5194                 argLen: 1,
5195                 asm:    x86.ASETNE,
5196                 reg: regInfo{
5197                         outputs: []outputInfo{
5198                                 {0, 239}, // AX CX DX BX BP SI DI
5199                         },
5200                 },
5201         },
5202         {
5203                 name:   "SETL",
5204                 argLen: 1,
5205                 asm:    x86.ASETLT,
5206                 reg: regInfo{
5207                         outputs: []outputInfo{
5208                                 {0, 239}, // AX CX DX BX BP SI DI
5209                         },
5210                 },
5211         },
5212         {
5213                 name:   "SETLE",
5214                 argLen: 1,
5215                 asm:    x86.ASETLE,
5216                 reg: regInfo{
5217                         outputs: []outputInfo{
5218                                 {0, 239}, // AX CX DX BX BP SI DI
5219                         },
5220                 },
5221         },
5222         {
5223                 name:   "SETG",
5224                 argLen: 1,
5225                 asm:    x86.ASETGT,
5226                 reg: regInfo{
5227                         outputs: []outputInfo{
5228                                 {0, 239}, // AX CX DX BX BP SI DI
5229                         },
5230                 },
5231         },
5232         {
5233                 name:   "SETGE",
5234                 argLen: 1,
5235                 asm:    x86.ASETGE,
5236                 reg: regInfo{
5237                         outputs: []outputInfo{
5238                                 {0, 239}, // AX CX DX BX BP SI DI
5239                         },
5240                 },
5241         },
5242         {
5243                 name:   "SETB",
5244                 argLen: 1,
5245                 asm:    x86.ASETCS,
5246                 reg: regInfo{
5247                         outputs: []outputInfo{
5248                                 {0, 239}, // AX CX DX BX BP SI DI
5249                         },
5250                 },
5251         },
5252         {
5253                 name:   "SETBE",
5254                 argLen: 1,
5255                 asm:    x86.ASETLS,
5256                 reg: regInfo{
5257                         outputs: []outputInfo{
5258                                 {0, 239}, // AX CX DX BX BP SI DI
5259                         },
5260                 },
5261         },
5262         {
5263                 name:   "SETA",
5264                 argLen: 1,
5265                 asm:    x86.ASETHI,
5266                 reg: regInfo{
5267                         outputs: []outputInfo{
5268                                 {0, 239}, // AX CX DX BX BP SI DI
5269                         },
5270                 },
5271         },
5272         {
5273                 name:   "SETAE",
5274                 argLen: 1,
5275                 asm:    x86.ASETCC,
5276                 reg: regInfo{
5277                         outputs: []outputInfo{
5278                                 {0, 239}, // AX CX DX BX BP SI DI
5279                         },
5280                 },
5281         },
5282         {
5283                 name:   "SETO",
5284                 argLen: 1,
5285                 asm:    x86.ASETOS,
5286                 reg: regInfo{
5287                         outputs: []outputInfo{
5288                                 {0, 239}, // AX CX DX BX BP SI DI
5289                         },
5290                 },
5291         },
5292         {
5293                 name:         "SETEQF",
5294                 argLen:       1,
5295                 clobberFlags: true,
5296                 asm:          x86.ASETEQ,
5297                 reg: regInfo{
5298                         clobbers: 1, // AX
5299                         outputs: []outputInfo{
5300                                 {0, 238}, // CX DX BX BP SI DI
5301                         },
5302                 },
5303         },
5304         {
5305                 name:         "SETNEF",
5306                 argLen:       1,
5307                 clobberFlags: true,
5308                 asm:          x86.ASETNE,
5309                 reg: regInfo{
5310                         clobbers: 1, // AX
5311                         outputs: []outputInfo{
5312                                 {0, 238}, // CX DX BX BP SI DI
5313                         },
5314                 },
5315         },
5316         {
5317                 name:   "SETORD",
5318                 argLen: 1,
5319                 asm:    x86.ASETPC,
5320                 reg: regInfo{
5321                         outputs: []outputInfo{
5322                                 {0, 239}, // AX CX DX BX BP SI DI
5323                         },
5324                 },
5325         },
5326         {
5327                 name:   "SETNAN",
5328                 argLen: 1,
5329                 asm:    x86.ASETPS,
5330                 reg: regInfo{
5331                         outputs: []outputInfo{
5332                                 {0, 239}, // AX CX DX BX BP SI DI
5333                         },
5334                 },
5335         },
5336         {
5337                 name:   "SETGF",
5338                 argLen: 1,
5339                 asm:    x86.ASETHI,
5340                 reg: regInfo{
5341                         outputs: []outputInfo{
5342                                 {0, 239}, // AX CX DX BX BP SI DI
5343                         },
5344                 },
5345         },
5346         {
5347                 name:   "SETGEF",
5348                 argLen: 1,
5349                 asm:    x86.ASETCC,
5350                 reg: regInfo{
5351                         outputs: []outputInfo{
5352                                 {0, 239}, // AX CX DX BX BP SI DI
5353                         },
5354                 },
5355         },
5356         {
5357                 name:   "MOVBLSX",
5358                 argLen: 1,
5359                 asm:    x86.AMOVBLSX,
5360                 reg: regInfo{
5361                         inputs: []inputInfo{
5362                                 {0, 239}, // AX CX DX BX BP SI DI
5363                         },
5364                         outputs: []outputInfo{
5365                                 {0, 239}, // AX CX DX BX BP SI DI
5366                         },
5367                 },
5368         },
5369         {
5370                 name:   "MOVBLZX",
5371                 argLen: 1,
5372                 asm:    x86.AMOVBLZX,
5373                 reg: regInfo{
5374                         inputs: []inputInfo{
5375                                 {0, 239}, // AX CX DX BX BP SI DI
5376                         },
5377                         outputs: []outputInfo{
5378                                 {0, 239}, // AX CX DX BX BP SI DI
5379                         },
5380                 },
5381         },
5382         {
5383                 name:   "MOVWLSX",
5384                 argLen: 1,
5385                 asm:    x86.AMOVWLSX,
5386                 reg: regInfo{
5387                         inputs: []inputInfo{
5388                                 {0, 239}, // AX CX DX BX BP SI DI
5389                         },
5390                         outputs: []outputInfo{
5391                                 {0, 239}, // AX CX DX BX BP SI DI
5392                         },
5393                 },
5394         },
5395         {
5396                 name:   "MOVWLZX",
5397                 argLen: 1,
5398                 asm:    x86.AMOVWLZX,
5399                 reg: regInfo{
5400                         inputs: []inputInfo{
5401                                 {0, 239}, // AX CX DX BX BP SI DI
5402                         },
5403                         outputs: []outputInfo{
5404                                 {0, 239}, // AX CX DX BX BP SI DI
5405                         },
5406                 },
5407         },
5408         {
5409                 name:              "MOVLconst",
5410                 auxType:           auxInt32,
5411                 argLen:            0,
5412                 rematerializeable: true,
5413                 asm:               x86.AMOVL,
5414                 reg: regInfo{
5415                         outputs: []outputInfo{
5416                                 {0, 239}, // AX CX DX BX BP SI DI
5417                         },
5418                 },
5419         },
5420         {
5421                 name:   "CVTTSD2SL",
5422                 argLen: 1,
5423                 asm:    x86.ACVTTSD2SL,
5424                 reg: regInfo{
5425                         inputs: []inputInfo{
5426                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5427                         },
5428                         outputs: []outputInfo{
5429                                 {0, 239}, // AX CX DX BX BP SI DI
5430                         },
5431                 },
5432         },
5433         {
5434                 name:   "CVTTSS2SL",
5435                 argLen: 1,
5436                 asm:    x86.ACVTTSS2SL,
5437                 reg: regInfo{
5438                         inputs: []inputInfo{
5439                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5440                         },
5441                         outputs: []outputInfo{
5442                                 {0, 239}, // AX CX DX BX BP SI DI
5443                         },
5444                 },
5445         },
5446         {
5447                 name:   "CVTSL2SS",
5448                 argLen: 1,
5449                 asm:    x86.ACVTSL2SS,
5450                 reg: regInfo{
5451                         inputs: []inputInfo{
5452                                 {0, 239}, // AX CX DX BX BP SI DI
5453                         },
5454                         outputs: []outputInfo{
5455                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5456                         },
5457                 },
5458         },
5459         {
5460                 name:   "CVTSL2SD",
5461                 argLen: 1,
5462                 asm:    x86.ACVTSL2SD,
5463                 reg: regInfo{
5464                         inputs: []inputInfo{
5465                                 {0, 239}, // AX CX DX BX BP SI DI
5466                         },
5467                         outputs: []outputInfo{
5468                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5469                         },
5470                 },
5471         },
5472         {
5473                 name:   "CVTSD2SS",
5474                 argLen: 1,
5475                 asm:    x86.ACVTSD2SS,
5476                 reg: regInfo{
5477                         inputs: []inputInfo{
5478                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5479                         },
5480                         outputs: []outputInfo{
5481                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5482                         },
5483                 },
5484         },
5485         {
5486                 name:   "CVTSS2SD",
5487                 argLen: 1,
5488                 asm:    x86.ACVTSS2SD,
5489                 reg: regInfo{
5490                         inputs: []inputInfo{
5491                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5492                         },
5493                         outputs: []outputInfo{
5494                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5495                         },
5496                 },
5497         },
5498         {
5499                 name:         "PXOR",
5500                 argLen:       2,
5501                 commutative:  true,
5502                 resultInArg0: true,
5503                 asm:          x86.APXOR,
5504                 reg: regInfo{
5505                         inputs: []inputInfo{
5506                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5507                                 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5508                         },
5509                         outputs: []outputInfo{
5510                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5511                         },
5512                 },
5513         },
5514         {
5515                 name:              "LEAL",
5516                 auxType:           auxSymOff,
5517                 argLen:            1,
5518                 rematerializeable: true,
5519                 symEffect:         SymAddr,
5520                 reg: regInfo{
5521                         inputs: []inputInfo{
5522                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5523                         },
5524                         outputs: []outputInfo{
5525                                 {0, 239}, // AX CX DX BX BP SI DI
5526                         },
5527                 },
5528         },
5529         {
5530                 name:        "LEAL1",
5531                 auxType:     auxSymOff,
5532                 argLen:      2,
5533                 commutative: true,
5534                 symEffect:   SymAddr,
5535                 reg: regInfo{
5536                         inputs: []inputInfo{
5537                                 {1, 255},   // AX CX DX BX SP BP SI DI
5538                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5539                         },
5540                         outputs: []outputInfo{
5541                                 {0, 239}, // AX CX DX BX BP SI DI
5542                         },
5543                 },
5544         },
5545         {
5546                 name:      "LEAL2",
5547                 auxType:   auxSymOff,
5548                 argLen:    2,
5549                 symEffect: SymAddr,
5550                 reg: regInfo{
5551                         inputs: []inputInfo{
5552                                 {1, 255},   // AX CX DX BX SP BP SI DI
5553                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5554                         },
5555                         outputs: []outputInfo{
5556                                 {0, 239}, // AX CX DX BX BP SI DI
5557                         },
5558                 },
5559         },
5560         {
5561                 name:      "LEAL4",
5562                 auxType:   auxSymOff,
5563                 argLen:    2,
5564                 symEffect: SymAddr,
5565                 reg: regInfo{
5566                         inputs: []inputInfo{
5567                                 {1, 255},   // AX CX DX BX SP BP SI DI
5568                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5569                         },
5570                         outputs: []outputInfo{
5571                                 {0, 239}, // AX CX DX BX BP SI DI
5572                         },
5573                 },
5574         },
5575         {
5576                 name:      "LEAL8",
5577                 auxType:   auxSymOff,
5578                 argLen:    2,
5579                 symEffect: SymAddr,
5580                 reg: regInfo{
5581                         inputs: []inputInfo{
5582                                 {1, 255},   // AX CX DX BX SP BP SI DI
5583                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5584                         },
5585                         outputs: []outputInfo{
5586                                 {0, 239}, // AX CX DX BX BP SI DI
5587                         },
5588                 },
5589         },
5590         {
5591                 name:           "MOVBload",
5592                 auxType:        auxSymOff,
5593                 argLen:         2,
5594                 faultOnNilArg0: true,
5595                 symEffect:      SymRead,
5596                 asm:            x86.AMOVBLZX,
5597                 reg: regInfo{
5598                         inputs: []inputInfo{
5599                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5600                         },
5601                         outputs: []outputInfo{
5602                                 {0, 239}, // AX CX DX BX BP SI DI
5603                         },
5604                 },
5605         },
5606         {
5607                 name:           "MOVBLSXload",
5608                 auxType:        auxSymOff,
5609                 argLen:         2,
5610                 faultOnNilArg0: true,
5611                 symEffect:      SymRead,
5612                 asm:            x86.AMOVBLSX,
5613                 reg: regInfo{
5614                         inputs: []inputInfo{
5615                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5616                         },
5617                         outputs: []outputInfo{
5618                                 {0, 239}, // AX CX DX BX BP SI DI
5619                         },
5620                 },
5621         },
5622         {
5623                 name:           "MOVWload",
5624                 auxType:        auxSymOff,
5625                 argLen:         2,
5626                 faultOnNilArg0: true,
5627                 symEffect:      SymRead,
5628                 asm:            x86.AMOVWLZX,
5629                 reg: regInfo{
5630                         inputs: []inputInfo{
5631                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5632                         },
5633                         outputs: []outputInfo{
5634                                 {0, 239}, // AX CX DX BX BP SI DI
5635                         },
5636                 },
5637         },
5638         {
5639                 name:           "MOVWLSXload",
5640                 auxType:        auxSymOff,
5641                 argLen:         2,
5642                 faultOnNilArg0: true,
5643                 symEffect:      SymRead,
5644                 asm:            x86.AMOVWLSX,
5645                 reg: regInfo{
5646                         inputs: []inputInfo{
5647                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5648                         },
5649                         outputs: []outputInfo{
5650                                 {0, 239}, // AX CX DX BX BP SI DI
5651                         },
5652                 },
5653         },
5654         {
5655                 name:           "MOVLload",
5656                 auxType:        auxSymOff,
5657                 argLen:         2,
5658                 faultOnNilArg0: true,
5659                 symEffect:      SymRead,
5660                 asm:            x86.AMOVL,
5661                 reg: regInfo{
5662                         inputs: []inputInfo{
5663                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5664                         },
5665                         outputs: []outputInfo{
5666                                 {0, 239}, // AX CX DX BX BP SI DI
5667                         },
5668                 },
5669         },
5670         {
5671                 name:           "MOVBstore",
5672                 auxType:        auxSymOff,
5673                 argLen:         3,
5674                 faultOnNilArg0: true,
5675                 symEffect:      SymWrite,
5676                 asm:            x86.AMOVB,
5677                 reg: regInfo{
5678                         inputs: []inputInfo{
5679                                 {1, 255},   // AX CX DX BX SP BP SI DI
5680                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5681                         },
5682                 },
5683         },
5684         {
5685                 name:           "MOVWstore",
5686                 auxType:        auxSymOff,
5687                 argLen:         3,
5688                 faultOnNilArg0: true,
5689                 symEffect:      SymWrite,
5690                 asm:            x86.AMOVW,
5691                 reg: regInfo{
5692                         inputs: []inputInfo{
5693                                 {1, 255},   // AX CX DX BX SP BP SI DI
5694                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5695                         },
5696                 },
5697         },
5698         {
5699                 name:           "MOVLstore",
5700                 auxType:        auxSymOff,
5701                 argLen:         3,
5702                 faultOnNilArg0: true,
5703                 symEffect:      SymWrite,
5704                 asm:            x86.AMOVL,
5705                 reg: regInfo{
5706                         inputs: []inputInfo{
5707                                 {1, 255},   // AX CX DX BX SP BP SI DI
5708                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5709                         },
5710                 },
5711         },
5712         {
5713                 name:           "ADDLmodify",
5714                 auxType:        auxSymOff,
5715                 argLen:         3,
5716                 clobberFlags:   true,
5717                 faultOnNilArg0: true,
5718                 symEffect:      SymRead | SymWrite,
5719                 asm:            x86.AADDL,
5720                 reg: regInfo{
5721                         inputs: []inputInfo{
5722                                 {1, 255},   // AX CX DX BX SP BP SI DI
5723                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5724                         },
5725                 },
5726         },
5727         {
5728                 name:           "SUBLmodify",
5729                 auxType:        auxSymOff,
5730                 argLen:         3,
5731                 clobberFlags:   true,
5732                 faultOnNilArg0: true,
5733                 symEffect:      SymRead | SymWrite,
5734                 asm:            x86.ASUBL,
5735                 reg: regInfo{
5736                         inputs: []inputInfo{
5737                                 {1, 255},   // AX CX DX BX SP BP SI DI
5738                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5739                         },
5740                 },
5741         },
5742         {
5743                 name:           "ANDLmodify",
5744                 auxType:        auxSymOff,
5745                 argLen:         3,
5746                 clobberFlags:   true,
5747                 faultOnNilArg0: true,
5748                 symEffect:      SymRead | SymWrite,
5749                 asm:            x86.AANDL,
5750                 reg: regInfo{
5751                         inputs: []inputInfo{
5752                                 {1, 255},   // AX CX DX BX SP BP SI DI
5753                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5754                         },
5755                 },
5756         },
5757         {
5758                 name:           "ORLmodify",
5759                 auxType:        auxSymOff,
5760                 argLen:         3,
5761                 clobberFlags:   true,
5762                 faultOnNilArg0: true,
5763                 symEffect:      SymRead | SymWrite,
5764                 asm:            x86.AORL,
5765                 reg: regInfo{
5766                         inputs: []inputInfo{
5767                                 {1, 255},   // AX CX DX BX SP BP SI DI
5768                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5769                         },
5770                 },
5771         },
5772         {
5773                 name:           "XORLmodify",
5774                 auxType:        auxSymOff,
5775                 argLen:         3,
5776                 clobberFlags:   true,
5777                 faultOnNilArg0: true,
5778                 symEffect:      SymRead | SymWrite,
5779                 asm:            x86.AXORL,
5780                 reg: regInfo{
5781                         inputs: []inputInfo{
5782                                 {1, 255},   // AX CX DX BX SP BP SI DI
5783                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5784                         },
5785                 },
5786         },
5787         {
5788                 name:         "ADDLmodifyidx4",
5789                 auxType:      auxSymOff,
5790                 argLen:       4,
5791                 clobberFlags: true,
5792                 symEffect:    SymRead | SymWrite,
5793                 asm:          x86.AADDL,
5794                 reg: regInfo{
5795                         inputs: []inputInfo{
5796                                 {1, 255},   // AX CX DX BX SP BP SI DI
5797                                 {2, 255},   // AX CX DX BX SP BP SI DI
5798                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5799                         },
5800                 },
5801         },
5802         {
5803                 name:         "SUBLmodifyidx4",
5804                 auxType:      auxSymOff,
5805                 argLen:       4,
5806                 clobberFlags: true,
5807                 symEffect:    SymRead | SymWrite,
5808                 asm:          x86.ASUBL,
5809                 reg: regInfo{
5810                         inputs: []inputInfo{
5811                                 {1, 255},   // AX CX DX BX SP BP SI DI
5812                                 {2, 255},   // AX CX DX BX SP BP SI DI
5813                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5814                         },
5815                 },
5816         },
5817         {
5818                 name:         "ANDLmodifyidx4",
5819                 auxType:      auxSymOff,
5820                 argLen:       4,
5821                 clobberFlags: true,
5822                 symEffect:    SymRead | SymWrite,
5823                 asm:          x86.AANDL,
5824                 reg: regInfo{
5825                         inputs: []inputInfo{
5826                                 {1, 255},   // AX CX DX BX SP BP SI DI
5827                                 {2, 255},   // AX CX DX BX SP BP SI DI
5828                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5829                         },
5830                 },
5831         },
5832         {
5833                 name:         "ORLmodifyidx4",
5834                 auxType:      auxSymOff,
5835                 argLen:       4,
5836                 clobberFlags: true,
5837                 symEffect:    SymRead | SymWrite,
5838                 asm:          x86.AORL,
5839                 reg: regInfo{
5840                         inputs: []inputInfo{
5841                                 {1, 255},   // AX CX DX BX SP BP SI DI
5842                                 {2, 255},   // AX CX DX BX SP BP SI DI
5843                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5844                         },
5845                 },
5846         },
5847         {
5848                 name:         "XORLmodifyidx4",
5849                 auxType:      auxSymOff,
5850                 argLen:       4,
5851                 clobberFlags: true,
5852                 symEffect:    SymRead | SymWrite,
5853                 asm:          x86.AXORL,
5854                 reg: regInfo{
5855                         inputs: []inputInfo{
5856                                 {1, 255},   // AX CX DX BX SP BP SI DI
5857                                 {2, 255},   // AX CX DX BX SP BP SI DI
5858                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5859                         },
5860                 },
5861         },
5862         {
5863                 name:           "ADDLconstmodify",
5864                 auxType:        auxSymValAndOff,
5865                 argLen:         2,
5866                 clobberFlags:   true,
5867                 faultOnNilArg0: true,
5868                 symEffect:      SymRead | SymWrite,
5869                 asm:            x86.AADDL,
5870                 reg: regInfo{
5871                         inputs: []inputInfo{
5872                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5873                         },
5874                 },
5875         },
5876         {
5877                 name:           "ANDLconstmodify",
5878                 auxType:        auxSymValAndOff,
5879                 argLen:         2,
5880                 clobberFlags:   true,
5881                 faultOnNilArg0: true,
5882                 symEffect:      SymRead | SymWrite,
5883                 asm:            x86.AANDL,
5884                 reg: regInfo{
5885                         inputs: []inputInfo{
5886                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5887                         },
5888                 },
5889         },
5890         {
5891                 name:           "ORLconstmodify",
5892                 auxType:        auxSymValAndOff,
5893                 argLen:         2,
5894                 clobberFlags:   true,
5895                 faultOnNilArg0: true,
5896                 symEffect:      SymRead | SymWrite,
5897                 asm:            x86.AORL,
5898                 reg: regInfo{
5899                         inputs: []inputInfo{
5900                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5901                         },
5902                 },
5903         },
5904         {
5905                 name:           "XORLconstmodify",
5906                 auxType:        auxSymValAndOff,
5907                 argLen:         2,
5908                 clobberFlags:   true,
5909                 faultOnNilArg0: true,
5910                 symEffect:      SymRead | SymWrite,
5911                 asm:            x86.AXORL,
5912                 reg: regInfo{
5913                         inputs: []inputInfo{
5914                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5915                         },
5916                 },
5917         },
5918         {
5919                 name:         "ADDLconstmodifyidx4",
5920                 auxType:      auxSymValAndOff,
5921                 argLen:       3,
5922                 clobberFlags: true,
5923                 symEffect:    SymRead | SymWrite,
5924                 asm:          x86.AADDL,
5925                 reg: regInfo{
5926                         inputs: []inputInfo{
5927                                 {1, 255},   // AX CX DX BX SP BP SI DI
5928                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5929                         },
5930                 },
5931         },
5932         {
5933                 name:         "ANDLconstmodifyidx4",
5934                 auxType:      auxSymValAndOff,
5935                 argLen:       3,
5936                 clobberFlags: true,
5937                 symEffect:    SymRead | SymWrite,
5938                 asm:          x86.AANDL,
5939                 reg: regInfo{
5940                         inputs: []inputInfo{
5941                                 {1, 255},   // AX CX DX BX SP BP SI DI
5942                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5943                         },
5944                 },
5945         },
5946         {
5947                 name:         "ORLconstmodifyidx4",
5948                 auxType:      auxSymValAndOff,
5949                 argLen:       3,
5950                 clobberFlags: true,
5951                 symEffect:    SymRead | SymWrite,
5952                 asm:          x86.AORL,
5953                 reg: regInfo{
5954                         inputs: []inputInfo{
5955                                 {1, 255},   // AX CX DX BX SP BP SI DI
5956                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5957                         },
5958                 },
5959         },
5960         {
5961                 name:         "XORLconstmodifyidx4",
5962                 auxType:      auxSymValAndOff,
5963                 argLen:       3,
5964                 clobberFlags: true,
5965                 symEffect:    SymRead | SymWrite,
5966                 asm:          x86.AXORL,
5967                 reg: regInfo{
5968                         inputs: []inputInfo{
5969                                 {1, 255},   // AX CX DX BX SP BP SI DI
5970                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5971                         },
5972                 },
5973         },
5974         {
5975                 name:        "MOVBloadidx1",
5976                 auxType:     auxSymOff,
5977                 argLen:      3,
5978                 commutative: true,
5979                 symEffect:   SymRead,
5980                 asm:         x86.AMOVBLZX,
5981                 reg: regInfo{
5982                         inputs: []inputInfo{
5983                                 {1, 255},   // AX CX DX BX SP BP SI DI
5984                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
5985                         },
5986                         outputs: []outputInfo{
5987                                 {0, 239}, // AX CX DX BX BP SI DI
5988                         },
5989                 },
5990         },
5991         {
5992                 name:        "MOVWloadidx1",
5993                 auxType:     auxSymOff,
5994                 argLen:      3,
5995                 commutative: true,
5996                 symEffect:   SymRead,
5997                 asm:         x86.AMOVWLZX,
5998                 reg: regInfo{
5999                         inputs: []inputInfo{
6000                                 {1, 255},   // AX CX DX BX SP BP SI DI
6001                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6002                         },
6003                         outputs: []outputInfo{
6004                                 {0, 239}, // AX CX DX BX BP SI DI
6005                         },
6006                 },
6007         },
6008         {
6009                 name:      "MOVWloadidx2",
6010                 auxType:   auxSymOff,
6011                 argLen:    3,
6012                 symEffect: SymRead,
6013                 asm:       x86.AMOVWLZX,
6014                 reg: regInfo{
6015                         inputs: []inputInfo{
6016                                 {1, 255},   // AX CX DX BX SP BP SI DI
6017                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6018                         },
6019                         outputs: []outputInfo{
6020                                 {0, 239}, // AX CX DX BX BP SI DI
6021                         },
6022                 },
6023         },
6024         {
6025                 name:        "MOVLloadidx1",
6026                 auxType:     auxSymOff,
6027                 argLen:      3,
6028                 commutative: true,
6029                 symEffect:   SymRead,
6030                 asm:         x86.AMOVL,
6031                 reg: regInfo{
6032                         inputs: []inputInfo{
6033                                 {1, 255},   // AX CX DX BX SP BP SI DI
6034                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6035                         },
6036                         outputs: []outputInfo{
6037                                 {0, 239}, // AX CX DX BX BP SI DI
6038                         },
6039                 },
6040         },
6041         {
6042                 name:      "MOVLloadidx4",
6043                 auxType:   auxSymOff,
6044                 argLen:    3,
6045                 symEffect: SymRead,
6046                 asm:       x86.AMOVL,
6047                 reg: regInfo{
6048                         inputs: []inputInfo{
6049                                 {1, 255},   // AX CX DX BX SP BP SI DI
6050                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6051                         },
6052                         outputs: []outputInfo{
6053                                 {0, 239}, // AX CX DX BX BP SI DI
6054                         },
6055                 },
6056         },
6057         {
6058                 name:        "MOVBstoreidx1",
6059                 auxType:     auxSymOff,
6060                 argLen:      4,
6061                 commutative: true,
6062                 symEffect:   SymWrite,
6063                 asm:         x86.AMOVB,
6064                 reg: regInfo{
6065                         inputs: []inputInfo{
6066                                 {1, 255},   // AX CX DX BX SP BP SI DI
6067                                 {2, 255},   // AX CX DX BX SP BP SI DI
6068                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6069                         },
6070                 },
6071         },
6072         {
6073                 name:        "MOVWstoreidx1",
6074                 auxType:     auxSymOff,
6075                 argLen:      4,
6076                 commutative: true,
6077                 symEffect:   SymWrite,
6078                 asm:         x86.AMOVW,
6079                 reg: regInfo{
6080                         inputs: []inputInfo{
6081                                 {1, 255},   // AX CX DX BX SP BP SI DI
6082                                 {2, 255},   // AX CX DX BX SP BP SI DI
6083                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6084                         },
6085                 },
6086         },
6087         {
6088                 name:      "MOVWstoreidx2",
6089                 auxType:   auxSymOff,
6090                 argLen:    4,
6091                 symEffect: SymWrite,
6092                 asm:       x86.AMOVW,
6093                 reg: regInfo{
6094                         inputs: []inputInfo{
6095                                 {1, 255},   // AX CX DX BX SP BP SI DI
6096                                 {2, 255},   // AX CX DX BX SP BP SI DI
6097                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6098                         },
6099                 },
6100         },
6101         {
6102                 name:        "MOVLstoreidx1",
6103                 auxType:     auxSymOff,
6104                 argLen:      4,
6105                 commutative: true,
6106                 symEffect:   SymWrite,
6107                 asm:         x86.AMOVL,
6108                 reg: regInfo{
6109                         inputs: []inputInfo{
6110                                 {1, 255},   // AX CX DX BX SP BP SI DI
6111                                 {2, 255},   // AX CX DX BX SP BP SI DI
6112                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6113                         },
6114                 },
6115         },
6116         {
6117                 name:      "MOVLstoreidx4",
6118                 auxType:   auxSymOff,
6119                 argLen:    4,
6120                 symEffect: SymWrite,
6121                 asm:       x86.AMOVL,
6122                 reg: regInfo{
6123                         inputs: []inputInfo{
6124                                 {1, 255},   // AX CX DX BX SP BP SI DI
6125                                 {2, 255},   // AX CX DX BX SP BP SI DI
6126                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6127                         },
6128                 },
6129         },
6130         {
6131                 name:           "MOVBstoreconst",
6132                 auxType:        auxSymValAndOff,
6133                 argLen:         2,
6134                 faultOnNilArg0: true,
6135                 symEffect:      SymWrite,
6136                 asm:            x86.AMOVB,
6137                 reg: regInfo{
6138                         inputs: []inputInfo{
6139                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6140                         },
6141                 },
6142         },
6143         {
6144                 name:           "MOVWstoreconst",
6145                 auxType:        auxSymValAndOff,
6146                 argLen:         2,
6147                 faultOnNilArg0: true,
6148                 symEffect:      SymWrite,
6149                 asm:            x86.AMOVW,
6150                 reg: regInfo{
6151                         inputs: []inputInfo{
6152                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6153                         },
6154                 },
6155         },
6156         {
6157                 name:           "MOVLstoreconst",
6158                 auxType:        auxSymValAndOff,
6159                 argLen:         2,
6160                 faultOnNilArg0: true,
6161                 symEffect:      SymWrite,
6162                 asm:            x86.AMOVL,
6163                 reg: regInfo{
6164                         inputs: []inputInfo{
6165                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6166                         },
6167                 },
6168         },
6169         {
6170                 name:      "MOVBstoreconstidx1",
6171                 auxType:   auxSymValAndOff,
6172                 argLen:    3,
6173                 symEffect: SymWrite,
6174                 asm:       x86.AMOVB,
6175                 reg: regInfo{
6176                         inputs: []inputInfo{
6177                                 {1, 255},   // AX CX DX BX SP BP SI DI
6178                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6179                         },
6180                 },
6181         },
6182         {
6183                 name:      "MOVWstoreconstidx1",
6184                 auxType:   auxSymValAndOff,
6185                 argLen:    3,
6186                 symEffect: SymWrite,
6187                 asm:       x86.AMOVW,
6188                 reg: regInfo{
6189                         inputs: []inputInfo{
6190                                 {1, 255},   // AX CX DX BX SP BP SI DI
6191                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6192                         },
6193                 },
6194         },
6195         {
6196                 name:      "MOVWstoreconstidx2",
6197                 auxType:   auxSymValAndOff,
6198                 argLen:    3,
6199                 symEffect: SymWrite,
6200                 asm:       x86.AMOVW,
6201                 reg: regInfo{
6202                         inputs: []inputInfo{
6203                                 {1, 255},   // AX CX DX BX SP BP SI DI
6204                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6205                         },
6206                 },
6207         },
6208         {
6209                 name:      "MOVLstoreconstidx1",
6210                 auxType:   auxSymValAndOff,
6211                 argLen:    3,
6212                 symEffect: SymWrite,
6213                 asm:       x86.AMOVL,
6214                 reg: regInfo{
6215                         inputs: []inputInfo{
6216                                 {1, 255},   // AX CX DX BX SP BP SI DI
6217                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6218                         },
6219                 },
6220         },
6221         {
6222                 name:      "MOVLstoreconstidx4",
6223                 auxType:   auxSymValAndOff,
6224                 argLen:    3,
6225                 symEffect: SymWrite,
6226                 asm:       x86.AMOVL,
6227                 reg: regInfo{
6228                         inputs: []inputInfo{
6229                                 {1, 255},   // AX CX DX BX SP BP SI DI
6230                                 {0, 65791}, // AX CX DX BX SP BP SI DI SB
6231                         },
6232                 },
6233         },
6234         {
6235                 name:           "DUFFZERO",
6236                 auxType:        auxInt64,
6237                 argLen:         3,
6238                 faultOnNilArg0: true,
6239                 reg: regInfo{
6240                         inputs: []inputInfo{
6241                                 {0, 128}, // DI
6242                                 {1, 1},   // AX
6243                         },
6244                         clobbers: 130, // CX DI
6245                 },
6246         },
6247         {
6248                 name:           "REPSTOSL",
6249                 argLen:         4,
6250                 faultOnNilArg0: true,
6251                 reg: regInfo{
6252                         inputs: []inputInfo{
6253                                 {0, 128}, // DI
6254                                 {1, 2},   // CX
6255                                 {2, 1},   // AX
6256                         },
6257                         clobbers: 130, // CX DI
6258                 },
6259         },
6260         {
6261                 name:         "CALLstatic",
6262                 auxType:      auxCallOff,
6263                 argLen:       1,
6264                 clobberFlags: true,
6265                 call:         true,
6266                 reg: regInfo{
6267                         clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
6268                 },
6269         },
6270         {
6271                 name:         "CALLtail",
6272                 auxType:      auxCallOff,
6273                 argLen:       1,
6274                 clobberFlags: true,
6275                 call:         true,
6276                 tailCall:     true,
6277                 reg: regInfo{
6278                         clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
6279                 },
6280         },
6281         {
6282                 name:         "CALLclosure",
6283                 auxType:      auxCallOff,
6284                 argLen:       3,
6285                 clobberFlags: true,
6286                 call:         true,
6287                 reg: regInfo{
6288                         inputs: []inputInfo{
6289                                 {1, 4},   // DX
6290                                 {0, 255}, // AX CX DX BX SP BP SI DI
6291                         },
6292                         clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
6293                 },
6294         },
6295         {
6296                 name:         "CALLinter",
6297                 auxType:      auxCallOff,
6298                 argLen:       2,
6299                 clobberFlags: true,
6300                 call:         true,
6301                 reg: regInfo{
6302                         inputs: []inputInfo{
6303                                 {0, 239}, // AX CX DX BX BP SI DI
6304                         },
6305                         clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
6306                 },
6307         },
6308         {
6309                 name:           "DUFFCOPY",
6310                 auxType:        auxInt64,
6311                 argLen:         3,
6312                 clobberFlags:   true,
6313                 faultOnNilArg0: true,
6314                 faultOnNilArg1: true,
6315                 reg: regInfo{
6316                         inputs: []inputInfo{
6317                                 {0, 128}, // DI
6318                                 {1, 64},  // SI
6319                         },
6320                         clobbers: 194, // CX SI DI
6321                 },
6322         },
6323         {
6324                 name:           "REPMOVSL",
6325                 argLen:         4,
6326                 faultOnNilArg0: true,
6327                 faultOnNilArg1: true,
6328                 reg: regInfo{
6329                         inputs: []inputInfo{
6330                                 {0, 128}, // DI
6331                                 {1, 64},  // SI
6332                                 {2, 2},   // CX
6333                         },
6334                         clobbers: 194, // CX SI DI
6335                 },
6336         },
6337         {
6338                 name:   "InvertFlags",
6339                 argLen: 1,
6340                 reg:    regInfo{},
6341         },
6342         {
6343                 name:   "LoweredGetG",
6344                 argLen: 1,
6345                 reg: regInfo{
6346                         outputs: []outputInfo{
6347                                 {0, 239}, // AX CX DX BX BP SI DI
6348                         },
6349                 },
6350         },
6351         {
6352                 name:      "LoweredGetClosurePtr",
6353                 argLen:    0,
6354                 zeroWidth: true,
6355                 reg: regInfo{
6356                         outputs: []outputInfo{
6357                                 {0, 4}, // DX
6358                         },
6359                 },
6360         },
6361         {
6362                 name:              "LoweredGetCallerPC",
6363                 argLen:            0,
6364                 rematerializeable: true,
6365                 reg: regInfo{
6366                         outputs: []outputInfo{
6367                                 {0, 239}, // AX CX DX BX BP SI DI
6368                         },
6369                 },
6370         },
6371         {
6372                 name:              "LoweredGetCallerSP",
6373                 argLen:            1,
6374                 rematerializeable: true,
6375                 reg: regInfo{
6376                         outputs: []outputInfo{
6377                                 {0, 239}, // AX CX DX BX BP SI DI
6378                         },
6379                 },
6380         },
6381         {
6382                 name:           "LoweredNilCheck",
6383                 argLen:         2,
6384                 clobberFlags:   true,
6385                 nilCheck:       true,
6386                 faultOnNilArg0: true,
6387                 reg: regInfo{
6388                         inputs: []inputInfo{
6389                                 {0, 255}, // AX CX DX BX SP BP SI DI
6390                         },
6391                 },
6392         },
6393         {
6394                 name:         "LoweredWB",
6395                 auxType:      auxInt64,
6396                 argLen:       1,
6397                 clobberFlags: true,
6398                 reg: regInfo{
6399                         clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7
6400                         outputs: []outputInfo{
6401                                 {0, 128}, // DI
6402                         },
6403                 },
6404         },
6405         {
6406                 name:    "LoweredPanicBoundsA",
6407                 auxType: auxInt64,
6408                 argLen:  3,
6409                 call:    true,
6410                 reg: regInfo{
6411                         inputs: []inputInfo{
6412                                 {0, 4}, // DX
6413                                 {1, 8}, // BX
6414                         },
6415                 },
6416         },
6417         {
6418                 name:    "LoweredPanicBoundsB",
6419                 auxType: auxInt64,
6420                 argLen:  3,
6421                 call:    true,
6422                 reg: regInfo{
6423                         inputs: []inputInfo{
6424                                 {0, 2}, // CX
6425                                 {1, 4}, // DX
6426                         },
6427                 },
6428         },
6429         {
6430                 name:    "LoweredPanicBoundsC",
6431                 auxType: auxInt64,
6432                 argLen:  3,
6433                 call:    true,
6434                 reg: regInfo{
6435                         inputs: []inputInfo{
6436                                 {0, 1}, // AX
6437                                 {1, 2}, // CX
6438                         },
6439                 },
6440         },
6441         {
6442                 name:    "LoweredPanicExtendA",
6443                 auxType: auxInt64,
6444                 argLen:  4,
6445                 call:    true,
6446                 reg: regInfo{
6447                         inputs: []inputInfo{
6448                                 {0, 64}, // SI
6449                                 {1, 4},  // DX
6450                                 {2, 8},  // BX
6451                         },
6452                 },
6453         },
6454         {
6455                 name:    "LoweredPanicExtendB",
6456                 auxType: auxInt64,
6457                 argLen:  4,
6458                 call:    true,
6459                 reg: regInfo{
6460                         inputs: []inputInfo{
6461                                 {0, 64}, // SI
6462                                 {1, 2},  // CX
6463                                 {2, 4},  // DX
6464                         },
6465                 },
6466         },
6467         {
6468                 name:    "LoweredPanicExtendC",
6469                 auxType: auxInt64,
6470                 argLen:  4,
6471                 call:    true,
6472                 reg: regInfo{
6473                         inputs: []inputInfo{
6474                                 {0, 64}, // SI
6475                                 {1, 1},  // AX
6476                                 {2, 2},  // CX
6477                         },
6478                 },
6479         },
6480         {
6481                 name:   "FlagEQ",
6482                 argLen: 0,
6483                 reg:    regInfo{},
6484         },
6485         {
6486                 name:   "FlagLT_ULT",
6487                 argLen: 0,
6488                 reg:    regInfo{},
6489         },
6490         {
6491                 name:   "FlagLT_UGT",
6492                 argLen: 0,
6493                 reg:    regInfo{},
6494         },
6495         {
6496                 name:   "FlagGT_UGT",
6497                 argLen: 0,
6498                 reg:    regInfo{},
6499         },
6500         {
6501                 name:   "FlagGT_ULT",
6502                 argLen: 0,
6503                 reg:    regInfo{},
6504         },
6505         {
6506                 name:    "MOVSSconst1",
6507                 auxType: auxFloat32,
6508                 argLen:  0,
6509                 reg: regInfo{
6510                         outputs: []outputInfo{
6511                                 {0, 239}, // AX CX DX BX BP SI DI
6512                         },
6513                 },
6514         },
6515         {
6516                 name:    "MOVSDconst1",
6517                 auxType: auxFloat64,
6518                 argLen:  0,
6519                 reg: regInfo{
6520                         outputs: []outputInfo{
6521                                 {0, 239}, // AX CX DX BX BP SI DI
6522                         },
6523                 },
6524         },
6525         {
6526                 name:   "MOVSSconst2",
6527                 argLen: 1,
6528                 asm:    x86.AMOVSS,
6529                 reg: regInfo{
6530                         inputs: []inputInfo{
6531                                 {0, 239}, // AX CX DX BX BP SI DI
6532                         },
6533                         outputs: []outputInfo{
6534                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
6535                         },
6536                 },
6537         },
6538         {
6539                 name:   "MOVSDconst2",
6540                 argLen: 1,
6541                 asm:    x86.AMOVSD,
6542                 reg: regInfo{
6543                         inputs: []inputInfo{
6544                                 {0, 239}, // AX CX DX BX BP SI DI
6545                         },
6546                         outputs: []outputInfo{
6547                                 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
6548                         },
6549                 },
6550         },
6551
6552         {
6553                 name:         "ADDSS",
6554                 argLen:       2,
6555                 commutative:  true,
6556                 resultInArg0: true,
6557                 asm:          x86.AADDSS,
6558                 reg: regInfo{
6559                         inputs: []inputInfo{
6560                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6561                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6562                         },
6563                         outputs: []outputInfo{
6564                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6565                         },
6566                 },
6567         },
6568         {
6569                 name:         "ADDSD",
6570                 argLen:       2,
6571                 commutative:  true,
6572                 resultInArg0: true,
6573                 asm:          x86.AADDSD,
6574                 reg: regInfo{
6575                         inputs: []inputInfo{
6576                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6577                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6578                         },
6579                         outputs: []outputInfo{
6580                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6581                         },
6582                 },
6583         },
6584         {
6585                 name:         "SUBSS",
6586                 argLen:       2,
6587                 resultInArg0: true,
6588                 asm:          x86.ASUBSS,
6589                 reg: regInfo{
6590                         inputs: []inputInfo{
6591                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6592                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6593                         },
6594                         outputs: []outputInfo{
6595                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6596                         },
6597                 },
6598         },
6599         {
6600                 name:         "SUBSD",
6601                 argLen:       2,
6602                 resultInArg0: true,
6603                 asm:          x86.ASUBSD,
6604                 reg: regInfo{
6605                         inputs: []inputInfo{
6606                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6607                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6608                         },
6609                         outputs: []outputInfo{
6610                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6611                         },
6612                 },
6613         },
6614         {
6615                 name:         "MULSS",
6616                 argLen:       2,
6617                 commutative:  true,
6618                 resultInArg0: true,
6619                 asm:          x86.AMULSS,
6620                 reg: regInfo{
6621                         inputs: []inputInfo{
6622                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6623                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6624                         },
6625                         outputs: []outputInfo{
6626                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6627                         },
6628                 },
6629         },
6630         {
6631                 name:         "MULSD",
6632                 argLen:       2,
6633                 commutative:  true,
6634                 resultInArg0: true,
6635                 asm:          x86.AMULSD,
6636                 reg: regInfo{
6637                         inputs: []inputInfo{
6638                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6639                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6640                         },
6641                         outputs: []outputInfo{
6642                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6643                         },
6644                 },
6645         },
6646         {
6647                 name:         "DIVSS",
6648                 argLen:       2,
6649                 resultInArg0: true,
6650                 asm:          x86.ADIVSS,
6651                 reg: regInfo{
6652                         inputs: []inputInfo{
6653                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6654                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6655                         },
6656                         outputs: []outputInfo{
6657                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6658                         },
6659                 },
6660         },
6661         {
6662                 name:         "DIVSD",
6663                 argLen:       2,
6664                 resultInArg0: true,
6665                 asm:          x86.ADIVSD,
6666                 reg: regInfo{
6667                         inputs: []inputInfo{
6668                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6669                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6670                         },
6671                         outputs: []outputInfo{
6672                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6673                         },
6674                 },
6675         },
6676         {
6677                 name:           "MOVSSload",
6678                 auxType:        auxSymOff,
6679                 argLen:         2,
6680                 faultOnNilArg0: true,
6681                 symEffect:      SymRead,
6682                 asm:            x86.AMOVSS,
6683                 reg: regInfo{
6684                         inputs: []inputInfo{
6685                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6686                         },
6687                         outputs: []outputInfo{
6688                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6689                         },
6690                 },
6691         },
6692         {
6693                 name:           "MOVSDload",
6694                 auxType:        auxSymOff,
6695                 argLen:         2,
6696                 faultOnNilArg0: true,
6697                 symEffect:      SymRead,
6698                 asm:            x86.AMOVSD,
6699                 reg: regInfo{
6700                         inputs: []inputInfo{
6701                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6702                         },
6703                         outputs: []outputInfo{
6704                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6705                         },
6706                 },
6707         },
6708         {
6709                 name:              "MOVSSconst",
6710                 auxType:           auxFloat32,
6711                 argLen:            0,
6712                 rematerializeable: true,
6713                 asm:               x86.AMOVSS,
6714                 reg: regInfo{
6715                         outputs: []outputInfo{
6716                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6717                         },
6718                 },
6719         },
6720         {
6721                 name:              "MOVSDconst",
6722                 auxType:           auxFloat64,
6723                 argLen:            0,
6724                 rematerializeable: true,
6725                 asm:               x86.AMOVSD,
6726                 reg: regInfo{
6727                         outputs: []outputInfo{
6728                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6729                         },
6730                 },
6731         },
6732         {
6733                 name:      "MOVSSloadidx1",
6734                 auxType:   auxSymOff,
6735                 argLen:    3,
6736                 symEffect: SymRead,
6737                 asm:       x86.AMOVSS,
6738                 scale:     1,
6739                 reg: regInfo{
6740                         inputs: []inputInfo{
6741                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6742                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6743                         },
6744                         outputs: []outputInfo{
6745                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6746                         },
6747                 },
6748         },
6749         {
6750                 name:      "MOVSSloadidx4",
6751                 auxType:   auxSymOff,
6752                 argLen:    3,
6753                 symEffect: SymRead,
6754                 asm:       x86.AMOVSS,
6755                 scale:     4,
6756                 reg: regInfo{
6757                         inputs: []inputInfo{
6758                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6759                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6760                         },
6761                         outputs: []outputInfo{
6762                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6763                         },
6764                 },
6765         },
6766         {
6767                 name:      "MOVSDloadidx1",
6768                 auxType:   auxSymOff,
6769                 argLen:    3,
6770                 symEffect: SymRead,
6771                 asm:       x86.AMOVSD,
6772                 scale:     1,
6773                 reg: regInfo{
6774                         inputs: []inputInfo{
6775                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6776                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6777                         },
6778                         outputs: []outputInfo{
6779                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6780                         },
6781                 },
6782         },
6783         {
6784                 name:      "MOVSDloadidx8",
6785                 auxType:   auxSymOff,
6786                 argLen:    3,
6787                 symEffect: SymRead,
6788                 asm:       x86.AMOVSD,
6789                 scale:     8,
6790                 reg: regInfo{
6791                         inputs: []inputInfo{
6792                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6793                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6794                         },
6795                         outputs: []outputInfo{
6796                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6797                         },
6798                 },
6799         },
6800         {
6801                 name:           "MOVSSstore",
6802                 auxType:        auxSymOff,
6803                 argLen:         3,
6804                 faultOnNilArg0: true,
6805                 symEffect:      SymWrite,
6806                 asm:            x86.AMOVSS,
6807                 reg: regInfo{
6808                         inputs: []inputInfo{
6809                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6810                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6811                         },
6812                 },
6813         },
6814         {
6815                 name:           "MOVSDstore",
6816                 auxType:        auxSymOff,
6817                 argLen:         3,
6818                 faultOnNilArg0: true,
6819                 symEffect:      SymWrite,
6820                 asm:            x86.AMOVSD,
6821                 reg: regInfo{
6822                         inputs: []inputInfo{
6823                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6824                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6825                         },
6826                 },
6827         },
6828         {
6829                 name:      "MOVSSstoreidx1",
6830                 auxType:   auxSymOff,
6831                 argLen:    4,
6832                 symEffect: SymWrite,
6833                 asm:       x86.AMOVSS,
6834                 scale:     1,
6835                 reg: regInfo{
6836                         inputs: []inputInfo{
6837                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6838                                 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6839                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6840                         },
6841                 },
6842         },
6843         {
6844                 name:      "MOVSSstoreidx4",
6845                 auxType:   auxSymOff,
6846                 argLen:    4,
6847                 symEffect: SymWrite,
6848                 asm:       x86.AMOVSS,
6849                 scale:     4,
6850                 reg: regInfo{
6851                         inputs: []inputInfo{
6852                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6853                                 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6854                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6855                         },
6856                 },
6857         },
6858         {
6859                 name:      "MOVSDstoreidx1",
6860                 auxType:   auxSymOff,
6861                 argLen:    4,
6862                 symEffect: SymWrite,
6863                 asm:       x86.AMOVSD,
6864                 scale:     1,
6865                 reg: regInfo{
6866                         inputs: []inputInfo{
6867                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6868                                 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6869                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6870                         },
6871                 },
6872         },
6873         {
6874                 name:      "MOVSDstoreidx8",
6875                 auxType:   auxSymOff,
6876                 argLen:    4,
6877                 symEffect: SymWrite,
6878                 asm:       x86.AMOVSD,
6879                 scale:     8,
6880                 reg: regInfo{
6881                         inputs: []inputInfo{
6882                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6883                                 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6884                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6885                         },
6886                 },
6887         },
6888         {
6889                 name:           "ADDSSload",
6890                 auxType:        auxSymOff,
6891                 argLen:         3,
6892                 resultInArg0:   true,
6893                 faultOnNilArg1: true,
6894                 symEffect:      SymRead,
6895                 asm:            x86.AADDSS,
6896                 reg: regInfo{
6897                         inputs: []inputInfo{
6898                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6899                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6900                         },
6901                         outputs: []outputInfo{
6902                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6903                         },
6904                 },
6905         },
6906         {
6907                 name:           "ADDSDload",
6908                 auxType:        auxSymOff,
6909                 argLen:         3,
6910                 resultInArg0:   true,
6911                 faultOnNilArg1: true,
6912                 symEffect:      SymRead,
6913                 asm:            x86.AADDSD,
6914                 reg: regInfo{
6915                         inputs: []inputInfo{
6916                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6917                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6918                         },
6919                         outputs: []outputInfo{
6920                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6921                         },
6922                 },
6923         },
6924         {
6925                 name:           "SUBSSload",
6926                 auxType:        auxSymOff,
6927                 argLen:         3,
6928                 resultInArg0:   true,
6929                 faultOnNilArg1: true,
6930                 symEffect:      SymRead,
6931                 asm:            x86.ASUBSS,
6932                 reg: regInfo{
6933                         inputs: []inputInfo{
6934                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6935                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6936                         },
6937                         outputs: []outputInfo{
6938                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6939                         },
6940                 },
6941         },
6942         {
6943                 name:           "SUBSDload",
6944                 auxType:        auxSymOff,
6945                 argLen:         3,
6946                 resultInArg0:   true,
6947                 faultOnNilArg1: true,
6948                 symEffect:      SymRead,
6949                 asm:            x86.ASUBSD,
6950                 reg: regInfo{
6951                         inputs: []inputInfo{
6952                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6953                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6954                         },
6955                         outputs: []outputInfo{
6956                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6957                         },
6958                 },
6959         },
6960         {
6961                 name:           "MULSSload",
6962                 auxType:        auxSymOff,
6963                 argLen:         3,
6964                 resultInArg0:   true,
6965                 faultOnNilArg1: true,
6966                 symEffect:      SymRead,
6967                 asm:            x86.AMULSS,
6968                 reg: regInfo{
6969                         inputs: []inputInfo{
6970                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6971                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6972                         },
6973                         outputs: []outputInfo{
6974                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6975                         },
6976                 },
6977         },
6978         {
6979                 name:           "MULSDload",
6980                 auxType:        auxSymOff,
6981                 argLen:         3,
6982                 resultInArg0:   true,
6983                 faultOnNilArg1: true,
6984                 symEffect:      SymRead,
6985                 asm:            x86.AMULSD,
6986                 reg: regInfo{
6987                         inputs: []inputInfo{
6988                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6989                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6990                         },
6991                         outputs: []outputInfo{
6992                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6993                         },
6994                 },
6995         },
6996         {
6997                 name:           "DIVSSload",
6998                 auxType:        auxSymOff,
6999                 argLen:         3,
7000                 resultInArg0:   true,
7001                 faultOnNilArg1: true,
7002                 symEffect:      SymRead,
7003                 asm:            x86.ADIVSS,
7004                 reg: regInfo{
7005                         inputs: []inputInfo{
7006                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7007                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7008                         },
7009                         outputs: []outputInfo{
7010                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7011                         },
7012                 },
7013         },
7014         {
7015                 name:           "DIVSDload",
7016                 auxType:        auxSymOff,
7017                 argLen:         3,
7018                 resultInArg0:   true,
7019                 faultOnNilArg1: true,
7020                 symEffect:      SymRead,
7021                 asm:            x86.ADIVSD,
7022                 reg: regInfo{
7023                         inputs: []inputInfo{
7024                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7025                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7026                         },
7027                         outputs: []outputInfo{
7028                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7029                         },
7030                 },
7031         },
7032         {
7033                 name:         "ADDSSloadidx1",
7034                 auxType:      auxSymOff,
7035                 argLen:       4,
7036                 resultInArg0: true,
7037                 symEffect:    SymRead,
7038                 asm:          x86.AADDSS,
7039                 scale:        1,
7040                 reg: regInfo{
7041                         inputs: []inputInfo{
7042                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7043                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7044                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7045                         },
7046                         outputs: []outputInfo{
7047                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7048                         },
7049                 },
7050         },
7051         {
7052                 name:         "ADDSSloadidx4",
7053                 auxType:      auxSymOff,
7054                 argLen:       4,
7055                 resultInArg0: true,
7056                 symEffect:    SymRead,
7057                 asm:          x86.AADDSS,
7058                 scale:        4,
7059                 reg: regInfo{
7060                         inputs: []inputInfo{
7061                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7062                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7063                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7064                         },
7065                         outputs: []outputInfo{
7066                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7067                         },
7068                 },
7069         },
7070         {
7071                 name:         "ADDSDloadidx1",
7072                 auxType:      auxSymOff,
7073                 argLen:       4,
7074                 resultInArg0: true,
7075                 symEffect:    SymRead,
7076                 asm:          x86.AADDSD,
7077                 scale:        1,
7078                 reg: regInfo{
7079                         inputs: []inputInfo{
7080                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7081                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7082                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7083                         },
7084                         outputs: []outputInfo{
7085                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7086                         },
7087                 },
7088         },
7089         {
7090                 name:         "ADDSDloadidx8",
7091                 auxType:      auxSymOff,
7092                 argLen:       4,
7093                 resultInArg0: true,
7094                 symEffect:    SymRead,
7095                 asm:          x86.AADDSD,
7096                 scale:        8,
7097                 reg: regInfo{
7098                         inputs: []inputInfo{
7099                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7100                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7101                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7102                         },
7103                         outputs: []outputInfo{
7104                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7105                         },
7106                 },
7107         },
7108         {
7109                 name:         "SUBSSloadidx1",
7110                 auxType:      auxSymOff,
7111                 argLen:       4,
7112                 resultInArg0: true,
7113                 symEffect:    SymRead,
7114                 asm:          x86.ASUBSS,
7115                 scale:        1,
7116                 reg: regInfo{
7117                         inputs: []inputInfo{
7118                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7119                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7120                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7121                         },
7122                         outputs: []outputInfo{
7123                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7124                         },
7125                 },
7126         },
7127         {
7128                 name:         "SUBSSloadidx4",
7129                 auxType:      auxSymOff,
7130                 argLen:       4,
7131                 resultInArg0: true,
7132                 symEffect:    SymRead,
7133                 asm:          x86.ASUBSS,
7134                 scale:        4,
7135                 reg: regInfo{
7136                         inputs: []inputInfo{
7137                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7138                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7139                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7140                         },
7141                         outputs: []outputInfo{
7142                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7143                         },
7144                 },
7145         },
7146         {
7147                 name:         "SUBSDloadidx1",
7148                 auxType:      auxSymOff,
7149                 argLen:       4,
7150                 resultInArg0: true,
7151                 symEffect:    SymRead,
7152                 asm:          x86.ASUBSD,
7153                 scale:        1,
7154                 reg: regInfo{
7155                         inputs: []inputInfo{
7156                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7157                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7158                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7159                         },
7160                         outputs: []outputInfo{
7161                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7162                         },
7163                 },
7164         },
7165         {
7166                 name:         "SUBSDloadidx8",
7167                 auxType:      auxSymOff,
7168                 argLen:       4,
7169                 resultInArg0: true,
7170                 symEffect:    SymRead,
7171                 asm:          x86.ASUBSD,
7172                 scale:        8,
7173                 reg: regInfo{
7174                         inputs: []inputInfo{
7175                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7176                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7177                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7178                         },
7179                         outputs: []outputInfo{
7180                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7181                         },
7182                 },
7183         },
7184         {
7185                 name:         "MULSSloadidx1",
7186                 auxType:      auxSymOff,
7187                 argLen:       4,
7188                 resultInArg0: true,
7189                 symEffect:    SymRead,
7190                 asm:          x86.AMULSS,
7191                 scale:        1,
7192                 reg: regInfo{
7193                         inputs: []inputInfo{
7194                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7195                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7196                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7197                         },
7198                         outputs: []outputInfo{
7199                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7200                         },
7201                 },
7202         },
7203         {
7204                 name:         "MULSSloadidx4",
7205                 auxType:      auxSymOff,
7206                 argLen:       4,
7207                 resultInArg0: true,
7208                 symEffect:    SymRead,
7209                 asm:          x86.AMULSS,
7210                 scale:        4,
7211                 reg: regInfo{
7212                         inputs: []inputInfo{
7213                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7214                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7215                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7216                         },
7217                         outputs: []outputInfo{
7218                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7219                         },
7220                 },
7221         },
7222         {
7223                 name:         "MULSDloadidx1",
7224                 auxType:      auxSymOff,
7225                 argLen:       4,
7226                 resultInArg0: true,
7227                 symEffect:    SymRead,
7228                 asm:          x86.AMULSD,
7229                 scale:        1,
7230                 reg: regInfo{
7231                         inputs: []inputInfo{
7232                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7233                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7234                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7235                         },
7236                         outputs: []outputInfo{
7237                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7238                         },
7239                 },
7240         },
7241         {
7242                 name:         "MULSDloadidx8",
7243                 auxType:      auxSymOff,
7244                 argLen:       4,
7245                 resultInArg0: true,
7246                 symEffect:    SymRead,
7247                 asm:          x86.AMULSD,
7248                 scale:        8,
7249                 reg: regInfo{
7250                         inputs: []inputInfo{
7251                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7252                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7253                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7254                         },
7255                         outputs: []outputInfo{
7256                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7257                         },
7258                 },
7259         },
7260         {
7261                 name:         "DIVSSloadidx1",
7262                 auxType:      auxSymOff,
7263                 argLen:       4,
7264                 resultInArg0: true,
7265                 symEffect:    SymRead,
7266                 asm:          x86.ADIVSS,
7267                 scale:        1,
7268                 reg: regInfo{
7269                         inputs: []inputInfo{
7270                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7271                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7272                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7273                         },
7274                         outputs: []outputInfo{
7275                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7276                         },
7277                 },
7278         },
7279         {
7280                 name:         "DIVSSloadidx4",
7281                 auxType:      auxSymOff,
7282                 argLen:       4,
7283                 resultInArg0: true,
7284                 symEffect:    SymRead,
7285                 asm:          x86.ADIVSS,
7286                 scale:        4,
7287                 reg: regInfo{
7288                         inputs: []inputInfo{
7289                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7290                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7291                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7292                         },
7293                         outputs: []outputInfo{
7294                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7295                         },
7296                 },
7297         },
7298         {
7299                 name:         "DIVSDloadidx1",
7300                 auxType:      auxSymOff,
7301                 argLen:       4,
7302                 resultInArg0: true,
7303                 symEffect:    SymRead,
7304                 asm:          x86.ADIVSD,
7305                 scale:        1,
7306                 reg: regInfo{
7307                         inputs: []inputInfo{
7308                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7309                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7310                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7311                         },
7312                         outputs: []outputInfo{
7313                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7314                         },
7315                 },
7316         },
7317         {
7318                 name:         "DIVSDloadidx8",
7319                 auxType:      auxSymOff,
7320                 argLen:       4,
7321                 resultInArg0: true,
7322                 symEffect:    SymRead,
7323                 asm:          x86.ADIVSD,
7324                 scale:        8,
7325                 reg: regInfo{
7326                         inputs: []inputInfo{
7327                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7328                                 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7329                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7330                         },
7331                         outputs: []outputInfo{
7332                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7333                         },
7334                 },
7335         },
7336         {
7337                 name:         "ADDQ",
7338                 argLen:       2,
7339                 commutative:  true,
7340                 clobberFlags: true,
7341                 asm:          x86.AADDQ,
7342                 reg: regInfo{
7343                         inputs: []inputInfo{
7344                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7345                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7346                         },
7347                         outputs: []outputInfo{
7348                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7349                         },
7350                 },
7351         },
7352         {
7353                 name:         "ADDL",
7354                 argLen:       2,
7355                 commutative:  true,
7356                 clobberFlags: true,
7357                 asm:          x86.AADDL,
7358                 reg: regInfo{
7359                         inputs: []inputInfo{
7360                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7361                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7362                         },
7363                         outputs: []outputInfo{
7364                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7365                         },
7366                 },
7367         },
7368         {
7369                 name:         "ADDQconst",
7370                 auxType:      auxInt32,
7371                 argLen:       1,
7372                 clobberFlags: true,
7373                 asm:          x86.AADDQ,
7374                 reg: regInfo{
7375                         inputs: []inputInfo{
7376                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7377                         },
7378                         outputs: []outputInfo{
7379                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7380                         },
7381                 },
7382         },
7383         {
7384                 name:         "ADDLconst",
7385                 auxType:      auxInt32,
7386                 argLen:       1,
7387                 clobberFlags: true,
7388                 asm:          x86.AADDL,
7389                 reg: regInfo{
7390                         inputs: []inputInfo{
7391                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7392                         },
7393                         outputs: []outputInfo{
7394                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7395                         },
7396                 },
7397         },
7398         {
7399                 name:           "ADDQconstmodify",
7400                 auxType:        auxSymValAndOff,
7401                 argLen:         2,
7402                 clobberFlags:   true,
7403                 faultOnNilArg0: true,
7404                 symEffect:      SymRead | SymWrite,
7405                 asm:            x86.AADDQ,
7406                 reg: regInfo{
7407                         inputs: []inputInfo{
7408                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7409                         },
7410                 },
7411         },
7412         {
7413                 name:           "ADDLconstmodify",
7414                 auxType:        auxSymValAndOff,
7415                 argLen:         2,
7416                 clobberFlags:   true,
7417                 faultOnNilArg0: true,
7418                 symEffect:      SymRead | SymWrite,
7419                 asm:            x86.AADDL,
7420                 reg: regInfo{
7421                         inputs: []inputInfo{
7422                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7423                         },
7424                 },
7425         },
7426         {
7427                 name:         "SUBQ",
7428                 argLen:       2,
7429                 resultInArg0: true,
7430                 clobberFlags: true,
7431                 asm:          x86.ASUBQ,
7432                 reg: regInfo{
7433                         inputs: []inputInfo{
7434                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7435                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7436                         },
7437                         outputs: []outputInfo{
7438                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7439                         },
7440                 },
7441         },
7442         {
7443                 name:         "SUBL",
7444                 argLen:       2,
7445                 resultInArg0: true,
7446                 clobberFlags: true,
7447                 asm:          x86.ASUBL,
7448                 reg: regInfo{
7449                         inputs: []inputInfo{
7450                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7451                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7452                         },
7453                         outputs: []outputInfo{
7454                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7455                         },
7456                 },
7457         },
7458         {
7459                 name:         "SUBQconst",
7460                 auxType:      auxInt32,
7461                 argLen:       1,
7462                 resultInArg0: true,
7463                 clobberFlags: true,
7464                 asm:          x86.ASUBQ,
7465                 reg: regInfo{
7466                         inputs: []inputInfo{
7467                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7468                         },
7469                         outputs: []outputInfo{
7470                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7471                         },
7472                 },
7473         },
7474         {
7475                 name:         "SUBLconst",
7476                 auxType:      auxInt32,
7477                 argLen:       1,
7478                 resultInArg0: true,
7479                 clobberFlags: true,
7480                 asm:          x86.ASUBL,
7481                 reg: regInfo{
7482                         inputs: []inputInfo{
7483                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7484                         },
7485                         outputs: []outputInfo{
7486                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7487                         },
7488                 },
7489         },
7490         {
7491                 name:         "MULQ",
7492                 argLen:       2,
7493                 commutative:  true,
7494                 resultInArg0: true,
7495                 clobberFlags: true,
7496                 asm:          x86.AIMULQ,
7497                 reg: regInfo{
7498                         inputs: []inputInfo{
7499                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7500                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7501                         },
7502                         outputs: []outputInfo{
7503                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7504                         },
7505                 },
7506         },
7507         {
7508                 name:         "MULL",
7509                 argLen:       2,
7510                 commutative:  true,
7511                 resultInArg0: true,
7512                 clobberFlags: true,
7513                 asm:          x86.AIMULL,
7514                 reg: regInfo{
7515                         inputs: []inputInfo{
7516                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7517                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7518                         },
7519                         outputs: []outputInfo{
7520                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7521                         },
7522                 },
7523         },
7524         {
7525                 name:         "MULQconst",
7526                 auxType:      auxInt32,
7527                 argLen:       1,
7528                 clobberFlags: true,
7529                 asm:          x86.AIMUL3Q,
7530                 reg: regInfo{
7531                         inputs: []inputInfo{
7532                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7533                         },
7534                         outputs: []outputInfo{
7535                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7536                         },
7537                 },
7538         },
7539         {
7540                 name:         "MULLconst",
7541                 auxType:      auxInt32,
7542                 argLen:       1,
7543                 clobberFlags: true,
7544                 asm:          x86.AIMUL3L,
7545                 reg: regInfo{
7546                         inputs: []inputInfo{
7547                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7548                         },
7549                         outputs: []outputInfo{
7550                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7551                         },
7552                 },
7553         },
7554         {
7555                 name:         "MULLU",
7556                 argLen:       2,
7557                 commutative:  true,
7558                 clobberFlags: true,
7559                 asm:          x86.AMULL,
7560                 reg: regInfo{
7561                         inputs: []inputInfo{
7562                                 {0, 1},     // AX
7563                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7564                         },
7565                         clobbers: 4, // DX
7566                         outputs: []outputInfo{
7567                                 {1, 0},
7568                                 {0, 1}, // AX
7569                         },
7570                 },
7571         },
7572         {
7573                 name:         "MULQU",
7574                 argLen:       2,
7575                 commutative:  true,
7576                 clobberFlags: true,
7577                 asm:          x86.AMULQ,
7578                 reg: regInfo{
7579                         inputs: []inputInfo{
7580                                 {0, 1},     // AX
7581                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7582                         },
7583                         clobbers: 4, // DX
7584                         outputs: []outputInfo{
7585                                 {1, 0},
7586                                 {0, 1}, // AX
7587                         },
7588                 },
7589         },
7590         {
7591                 name:         "HMULQ",
7592                 argLen:       2,
7593                 clobberFlags: true,
7594                 asm:          x86.AIMULQ,
7595                 reg: regInfo{
7596                         inputs: []inputInfo{
7597                                 {0, 1},     // AX
7598                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7599                         },
7600                         clobbers: 1, // AX
7601                         outputs: []outputInfo{
7602                                 {0, 4}, // DX
7603                         },
7604                 },
7605         },
7606         {
7607                 name:         "HMULL",
7608                 argLen:       2,
7609                 clobberFlags: true,
7610                 asm:          x86.AIMULL,
7611                 reg: regInfo{
7612                         inputs: []inputInfo{
7613                                 {0, 1},     // AX
7614                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7615                         },
7616                         clobbers: 1, // AX
7617                         outputs: []outputInfo{
7618                                 {0, 4}, // DX
7619                         },
7620                 },
7621         },
7622         {
7623                 name:         "HMULQU",
7624                 argLen:       2,
7625                 clobberFlags: true,
7626                 asm:          x86.AMULQ,
7627                 reg: regInfo{
7628                         inputs: []inputInfo{
7629                                 {0, 1},     // AX
7630                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7631                         },
7632                         clobbers: 1, // AX
7633                         outputs: []outputInfo{
7634                                 {0, 4}, // DX
7635                         },
7636                 },
7637         },
7638         {
7639                 name:         "HMULLU",
7640                 argLen:       2,
7641                 clobberFlags: true,
7642                 asm:          x86.AMULL,
7643                 reg: regInfo{
7644                         inputs: []inputInfo{
7645                                 {0, 1},     // AX
7646                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7647                         },
7648                         clobbers: 1, // AX
7649                         outputs: []outputInfo{
7650                                 {0, 4}, // DX
7651                         },
7652                 },
7653         },
7654         {
7655                 name:         "AVGQU",
7656                 argLen:       2,
7657                 commutative:  true,
7658                 resultInArg0: true,
7659                 clobberFlags: true,
7660                 reg: regInfo{
7661                         inputs: []inputInfo{
7662                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7663                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7664                         },
7665                         outputs: []outputInfo{
7666                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7667                         },
7668                 },
7669         },
7670         {
7671                 name:         "DIVQ",
7672                 auxType:      auxBool,
7673                 argLen:       2,
7674                 clobberFlags: true,
7675                 asm:          x86.AIDIVQ,
7676                 reg: regInfo{
7677                         inputs: []inputInfo{
7678                                 {0, 1},     // AX
7679                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7680                         },
7681                         outputs: []outputInfo{
7682                                 {0, 1}, // AX
7683                                 {1, 4}, // DX
7684                         },
7685                 },
7686         },
7687         {
7688                 name:         "DIVL",
7689                 auxType:      auxBool,
7690                 argLen:       2,
7691                 clobberFlags: true,
7692                 asm:          x86.AIDIVL,
7693                 reg: regInfo{
7694                         inputs: []inputInfo{
7695                                 {0, 1},     // AX
7696                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7697                         },
7698                         outputs: []outputInfo{
7699                                 {0, 1}, // AX
7700                                 {1, 4}, // DX
7701                         },
7702                 },
7703         },
7704         {
7705                 name:         "DIVW",
7706                 auxType:      auxBool,
7707                 argLen:       2,
7708                 clobberFlags: true,
7709                 asm:          x86.AIDIVW,
7710                 reg: regInfo{
7711                         inputs: []inputInfo{
7712                                 {0, 1},     // AX
7713                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7714                         },
7715                         outputs: []outputInfo{
7716                                 {0, 1}, // AX
7717                                 {1, 4}, // DX
7718                         },
7719                 },
7720         },
7721         {
7722                 name:         "DIVQU",
7723                 argLen:       2,
7724                 clobberFlags: true,
7725                 asm:          x86.ADIVQ,
7726                 reg: regInfo{
7727                         inputs: []inputInfo{
7728                                 {0, 1},     // AX
7729                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7730                         },
7731                         outputs: []outputInfo{
7732                                 {0, 1}, // AX
7733                                 {1, 4}, // DX
7734                         },
7735                 },
7736         },
7737         {
7738                 name:         "DIVLU",
7739                 argLen:       2,
7740                 clobberFlags: true,
7741                 asm:          x86.ADIVL,
7742                 reg: regInfo{
7743                         inputs: []inputInfo{
7744                                 {0, 1},     // AX
7745                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7746                         },
7747                         outputs: []outputInfo{
7748                                 {0, 1}, // AX
7749                                 {1, 4}, // DX
7750                         },
7751                 },
7752         },
7753         {
7754                 name:         "DIVWU",
7755                 argLen:       2,
7756                 clobberFlags: true,
7757                 asm:          x86.ADIVW,
7758                 reg: regInfo{
7759                         inputs: []inputInfo{
7760                                 {0, 1},     // AX
7761                                 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7762                         },
7763                         outputs: []outputInfo{
7764                                 {0, 1}, // AX
7765                                 {1, 4}, // DX
7766                         },
7767                 },
7768         },
7769         {
7770                 name:         "NEGLflags",
7771                 argLen:       1,
7772                 resultInArg0: true,
7773                 asm:          x86.ANEGL,
7774                 reg: regInfo{
7775                         inputs: []inputInfo{
7776                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7777                         },
7778                         outputs: []outputInfo{
7779                                 {1, 0},
7780                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7781                         },
7782                 },
7783         },
7784         {
7785                 name:         "ADDQcarry",
7786                 argLen:       2,
7787                 commutative:  true,
7788                 resultInArg0: true,
7789                 asm:          x86.AADDQ,
7790                 reg: regInfo{
7791                         inputs: []inputInfo{
7792                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7793                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7794                         },
7795                         outputs: []outputInfo{
7796                                 {1, 0},
7797                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7798                         },
7799                 },
7800         },
7801         {
7802                 name:         "ADCQ",
7803                 argLen:       3,
7804                 commutative:  true,
7805                 resultInArg0: true,
7806                 asm:          x86.AADCQ,
7807                 reg: regInfo{
7808                         inputs: []inputInfo{
7809                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7810                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7811                         },
7812                         outputs: []outputInfo{
7813                                 {1, 0},
7814                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7815                         },
7816                 },
7817         },
7818         {
7819                 name:         "ADDQconstcarry",
7820                 auxType:      auxInt32,
7821                 argLen:       1,
7822                 resultInArg0: true,
7823                 asm:          x86.AADDQ,
7824                 reg: regInfo{
7825                         inputs: []inputInfo{
7826                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7827                         },
7828                         outputs: []outputInfo{
7829                                 {1, 0},
7830                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7831                         },
7832                 },
7833         },
7834         {
7835                 name:         "ADCQconst",
7836                 auxType:      auxInt32,
7837                 argLen:       2,
7838                 resultInArg0: true,
7839                 asm:          x86.AADCQ,
7840                 reg: regInfo{
7841                         inputs: []inputInfo{
7842                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7843                         },
7844                         outputs: []outputInfo{
7845                                 {1, 0},
7846                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7847                         },
7848                 },
7849         },
7850         {
7851                 name:         "SUBQborrow",
7852                 argLen:       2,
7853                 resultInArg0: true,
7854                 asm:          x86.ASUBQ,
7855                 reg: regInfo{
7856                         inputs: []inputInfo{
7857                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7858                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7859                         },
7860                         outputs: []outputInfo{
7861                                 {1, 0},
7862                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7863                         },
7864                 },
7865         },
7866         {
7867                 name:         "SBBQ",
7868                 argLen:       3,
7869                 resultInArg0: true,
7870                 asm:          x86.ASBBQ,
7871                 reg: regInfo{
7872                         inputs: []inputInfo{
7873                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7874                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7875                         },
7876                         outputs: []outputInfo{
7877                                 {1, 0},
7878                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7879                         },
7880                 },
7881         },
7882         {
7883                 name:         "SUBQconstborrow",
7884                 auxType:      auxInt32,
7885                 argLen:       1,
7886                 resultInArg0: true,
7887                 asm:          x86.ASUBQ,
7888                 reg: regInfo{
7889                         inputs: []inputInfo{
7890                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7891                         },
7892                         outputs: []outputInfo{
7893                                 {1, 0},
7894                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7895                         },
7896                 },
7897         },
7898         {
7899                 name:         "SBBQconst",
7900                 auxType:      auxInt32,
7901                 argLen:       2,
7902                 resultInArg0: true,
7903                 asm:          x86.ASBBQ,
7904                 reg: regInfo{
7905                         inputs: []inputInfo{
7906                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7907                         },
7908                         outputs: []outputInfo{
7909                                 {1, 0},
7910                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7911                         },
7912                 },
7913         },
7914         {
7915                 name:         "MULQU2",
7916                 argLen:       2,
7917                 commutative:  true,
7918                 clobberFlags: true,
7919                 asm:          x86.AMULQ,
7920                 reg: regInfo{
7921                         inputs: []inputInfo{
7922                                 {0, 1},     // AX
7923                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7924                         },
7925                         outputs: []outputInfo{
7926                                 {0, 4}, // DX
7927                                 {1, 1}, // AX
7928                         },
7929                 },
7930         },
7931         {
7932                 name:         "DIVQU2",
7933                 argLen:       3,
7934                 clobberFlags: true,
7935                 asm:          x86.ADIVQ,
7936                 reg: regInfo{
7937                         inputs: []inputInfo{
7938                                 {0, 4},     // DX
7939                                 {1, 1},     // AX
7940                                 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7941                         },
7942                         outputs: []outputInfo{
7943                                 {0, 1}, // AX
7944                                 {1, 4}, // DX
7945                         },
7946                 },
7947         },
7948         {
7949                 name:         "ANDQ",
7950                 argLen:       2,
7951                 commutative:  true,
7952                 resultInArg0: true,
7953                 clobberFlags: true,
7954                 asm:          x86.AANDQ,
7955                 reg: regInfo{
7956                         inputs: []inputInfo{
7957                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7958                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7959                         },
7960                         outputs: []outputInfo{
7961                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7962                         },
7963                 },
7964         },
7965         {
7966                 name:         "ANDL",
7967                 argLen:       2,
7968                 commutative:  true,
7969                 resultInArg0: true,
7970                 clobberFlags: true,
7971                 asm:          x86.AANDL,
7972                 reg: regInfo{
7973                         inputs: []inputInfo{
7974                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7975                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7976                         },
7977                         outputs: []outputInfo{
7978                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7979                         },
7980                 },
7981         },
7982         {
7983                 name:         "ANDQconst",
7984                 auxType:      auxInt32,
7985                 argLen:       1,
7986                 resultInArg0: true,
7987                 clobberFlags: true,
7988                 asm:          x86.AANDQ,
7989                 reg: regInfo{
7990                         inputs: []inputInfo{
7991                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7992                         },
7993                         outputs: []outputInfo{
7994                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7995                         },
7996                 },
7997         },
7998         {
7999                 name:         "ANDLconst",
8000                 auxType:      auxInt32,
8001                 argLen:       1,
8002                 resultInArg0: true,
8003                 clobberFlags: true,
8004                 asm:          x86.AANDL,
8005                 reg: regInfo{
8006                         inputs: []inputInfo{
8007                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8008                         },
8009                         outputs: []outputInfo{
8010                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8011                         },
8012                 },
8013         },
8014         {
8015                 name:           "ANDQconstmodify",
8016                 auxType:        auxSymValAndOff,
8017                 argLen:         2,
8018                 clobberFlags:   true,
8019                 faultOnNilArg0: true,
8020                 symEffect:      SymRead | SymWrite,
8021                 asm:            x86.AANDQ,
8022                 reg: regInfo{
8023                         inputs: []inputInfo{
8024                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8025                         },
8026                 },
8027         },
8028         {
8029                 name:           "ANDLconstmodify",
8030                 auxType:        auxSymValAndOff,
8031                 argLen:         2,
8032                 clobberFlags:   true,
8033                 faultOnNilArg0: true,
8034                 symEffect:      SymRead | SymWrite,
8035                 asm:            x86.AANDL,
8036                 reg: regInfo{
8037                         inputs: []inputInfo{
8038                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8039                         },
8040                 },
8041         },
8042         {
8043                 name:         "ORQ",
8044                 argLen:       2,
8045                 commutative:  true,
8046                 resultInArg0: true,
8047                 clobberFlags: true,
8048                 asm:          x86.AORQ,
8049                 reg: regInfo{
8050                         inputs: []inputInfo{
8051                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8052                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8053                         },
8054                         outputs: []outputInfo{
8055                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8056                         },
8057                 },
8058         },
8059         {
8060                 name:         "ORL",
8061                 argLen:       2,
8062                 commutative:  true,
8063                 resultInArg0: true,
8064                 clobberFlags: true,
8065                 asm:          x86.AORL,
8066                 reg: regInfo{
8067                         inputs: []inputInfo{
8068                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8069                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8070                         },
8071                         outputs: []outputInfo{
8072                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8073                         },
8074                 },
8075         },
8076         {
8077                 name:         "ORQconst",
8078                 auxType:      auxInt32,
8079                 argLen:       1,
8080                 resultInArg0: true,
8081                 clobberFlags: true,
8082                 asm:          x86.AORQ,
8083                 reg: regInfo{
8084                         inputs: []inputInfo{
8085                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8086                         },
8087                         outputs: []outputInfo{
8088                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8089                         },
8090                 },
8091         },
8092         {
8093                 name:         "ORLconst",
8094                 auxType:      auxInt32,
8095                 argLen:       1,
8096                 resultInArg0: true,
8097                 clobberFlags: true,
8098                 asm:          x86.AORL,
8099                 reg: regInfo{
8100                         inputs: []inputInfo{
8101                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8102                         },
8103                         outputs: []outputInfo{
8104                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8105                         },
8106                 },
8107         },
8108         {
8109                 name:           "ORQconstmodify",
8110                 auxType:        auxSymValAndOff,
8111                 argLen:         2,
8112                 clobberFlags:   true,
8113                 faultOnNilArg0: true,
8114                 symEffect:      SymRead | SymWrite,
8115                 asm:            x86.AORQ,
8116                 reg: regInfo{
8117                         inputs: []inputInfo{
8118                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8119                         },
8120                 },
8121         },
8122         {
8123                 name:           "ORLconstmodify",
8124                 auxType:        auxSymValAndOff,
8125                 argLen:         2,
8126                 clobberFlags:   true,
8127                 faultOnNilArg0: true,
8128                 symEffect:      SymRead | SymWrite,
8129                 asm:            x86.AORL,
8130                 reg: regInfo{
8131                         inputs: []inputInfo{
8132                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8133                         },
8134                 },
8135         },
8136         {
8137                 name:         "XORQ",
8138                 argLen:       2,
8139                 commutative:  true,
8140                 resultInArg0: true,
8141                 clobberFlags: true,
8142                 asm:          x86.AXORQ,
8143                 reg: regInfo{
8144                         inputs: []inputInfo{
8145                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8146                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8147                         },
8148                         outputs: []outputInfo{
8149                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8150                         },
8151                 },
8152         },
8153         {
8154                 name:         "XORL",
8155                 argLen:       2,
8156                 commutative:  true,
8157                 resultInArg0: true,
8158                 clobberFlags: true,
8159                 asm:          x86.AXORL,
8160                 reg: regInfo{
8161                         inputs: []inputInfo{
8162                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8163                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8164                         },
8165                         outputs: []outputInfo{
8166                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8167                         },
8168                 },
8169         },
8170         {
8171                 name:         "XORQconst",
8172                 auxType:      auxInt32,
8173                 argLen:       1,
8174                 resultInArg0: true,
8175                 clobberFlags: true,
8176                 asm:          x86.AXORQ,
8177                 reg: regInfo{
8178                         inputs: []inputInfo{
8179                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8180                         },
8181                         outputs: []outputInfo{
8182                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8183                         },
8184                 },
8185         },
8186         {
8187                 name:         "XORLconst",
8188                 auxType:      auxInt32,
8189                 argLen:       1,
8190                 resultInArg0: true,
8191                 clobberFlags: true,
8192                 asm:          x86.AXORL,
8193                 reg: regInfo{
8194                         inputs: []inputInfo{
8195                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8196                         },
8197                         outputs: []outputInfo{
8198                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8199                         },
8200                 },
8201         },
8202         {
8203                 name:           "XORQconstmodify",
8204                 auxType:        auxSymValAndOff,
8205                 argLen:         2,
8206                 clobberFlags:   true,
8207                 faultOnNilArg0: true,
8208                 symEffect:      SymRead | SymWrite,
8209                 asm:            x86.AXORQ,
8210                 reg: regInfo{
8211                         inputs: []inputInfo{
8212                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8213                         },
8214                 },
8215         },
8216         {
8217                 name:           "XORLconstmodify",
8218                 auxType:        auxSymValAndOff,
8219                 argLen:         2,
8220                 clobberFlags:   true,
8221                 faultOnNilArg0: true,
8222                 symEffect:      SymRead | SymWrite,
8223                 asm:            x86.AXORL,
8224                 reg: regInfo{
8225                         inputs: []inputInfo{
8226                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8227                         },
8228                 },
8229         },
8230         {
8231                 name:   "CMPQ",
8232                 argLen: 2,
8233                 asm:    x86.ACMPQ,
8234                 reg: regInfo{
8235                         inputs: []inputInfo{
8236                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8237                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8238                         },
8239                 },
8240         },
8241         {
8242                 name:   "CMPL",
8243                 argLen: 2,
8244                 asm:    x86.ACMPL,
8245                 reg: regInfo{
8246                         inputs: []inputInfo{
8247                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8248                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8249                         },
8250                 },
8251         },
8252         {
8253                 name:   "CMPW",
8254                 argLen: 2,
8255                 asm:    x86.ACMPW,
8256                 reg: regInfo{
8257                         inputs: []inputInfo{
8258                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8259                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8260                         },
8261                 },
8262         },
8263         {
8264                 name:   "CMPB",
8265                 argLen: 2,
8266                 asm:    x86.ACMPB,
8267                 reg: regInfo{
8268                         inputs: []inputInfo{
8269                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8270                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8271                         },
8272                 },
8273         },
8274         {
8275                 name:    "CMPQconst",
8276                 auxType: auxInt32,
8277                 argLen:  1,
8278                 asm:     x86.ACMPQ,
8279                 reg: regInfo{
8280                         inputs: []inputInfo{
8281                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8282                         },
8283                 },
8284         },
8285         {
8286                 name:    "CMPLconst",
8287                 auxType: auxInt32,
8288                 argLen:  1,
8289                 asm:     x86.ACMPL,
8290                 reg: regInfo{
8291                         inputs: []inputInfo{
8292                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8293                         },
8294                 },
8295         },
8296         {
8297                 name:    "CMPWconst",
8298                 auxType: auxInt16,
8299                 argLen:  1,
8300                 asm:     x86.ACMPW,
8301                 reg: regInfo{
8302                         inputs: []inputInfo{
8303                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8304                         },
8305                 },
8306         },
8307         {
8308                 name:    "CMPBconst",
8309                 auxType: auxInt8,
8310                 argLen:  1,
8311                 asm:     x86.ACMPB,
8312                 reg: regInfo{
8313                         inputs: []inputInfo{
8314                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8315                         },
8316                 },
8317         },
8318         {
8319                 name:           "CMPQload",
8320                 auxType:        auxSymOff,
8321                 argLen:         3,
8322                 faultOnNilArg0: true,
8323                 symEffect:      SymRead,
8324                 asm:            x86.ACMPQ,
8325                 reg: regInfo{
8326                         inputs: []inputInfo{
8327                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8328                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8329                         },
8330                 },
8331         },
8332         {
8333                 name:           "CMPLload",
8334                 auxType:        auxSymOff,
8335                 argLen:         3,
8336                 faultOnNilArg0: true,
8337                 symEffect:      SymRead,
8338                 asm:            x86.ACMPL,
8339                 reg: regInfo{
8340                         inputs: []inputInfo{
8341                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8342                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8343                         },
8344                 },
8345         },
8346         {
8347                 name:           "CMPWload",
8348                 auxType:        auxSymOff,
8349                 argLen:         3,
8350                 faultOnNilArg0: true,
8351                 symEffect:      SymRead,
8352                 asm:            x86.ACMPW,
8353                 reg: regInfo{
8354                         inputs: []inputInfo{
8355                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8356                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8357                         },
8358                 },
8359         },
8360         {
8361                 name:           "CMPBload",
8362                 auxType:        auxSymOff,
8363                 argLen:         3,
8364                 faultOnNilArg0: true,
8365                 symEffect:      SymRead,
8366                 asm:            x86.ACMPB,
8367                 reg: regInfo{
8368                         inputs: []inputInfo{
8369                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8370                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8371                         },
8372                 },
8373         },
8374         {
8375                 name:           "CMPQconstload",
8376                 auxType:        auxSymValAndOff,
8377                 argLen:         2,
8378                 faultOnNilArg0: true,
8379                 symEffect:      SymRead,
8380                 asm:            x86.ACMPQ,
8381                 reg: regInfo{
8382                         inputs: []inputInfo{
8383                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8384                         },
8385                 },
8386         },
8387         {
8388                 name:           "CMPLconstload",
8389                 auxType:        auxSymValAndOff,
8390                 argLen:         2,
8391                 faultOnNilArg0: true,
8392                 symEffect:      SymRead,
8393                 asm:            x86.ACMPL,
8394                 reg: regInfo{
8395                         inputs: []inputInfo{
8396                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8397                         },
8398                 },
8399         },
8400         {
8401                 name:           "CMPWconstload",
8402                 auxType:        auxSymValAndOff,
8403                 argLen:         2,
8404                 faultOnNilArg0: true,
8405                 symEffect:      SymRead,
8406                 asm:            x86.ACMPW,
8407                 reg: regInfo{
8408                         inputs: []inputInfo{
8409                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8410                         },
8411                 },
8412         },
8413         {
8414                 name:           "CMPBconstload",
8415                 auxType:        auxSymValAndOff,
8416                 argLen:         2,
8417                 faultOnNilArg0: true,
8418                 symEffect:      SymRead,
8419                 asm:            x86.ACMPB,
8420                 reg: regInfo{
8421                         inputs: []inputInfo{
8422                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8423                         },
8424                 },
8425         },
8426         {
8427                 name:      "CMPQloadidx8",
8428                 auxType:   auxSymOff,
8429                 argLen:    4,
8430                 symEffect: SymRead,
8431                 asm:       x86.ACMPQ,
8432                 scale:     8,
8433                 reg: regInfo{
8434                         inputs: []inputInfo{
8435                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8436                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8437                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8438                         },
8439                 },
8440         },
8441         {
8442                 name:        "CMPQloadidx1",
8443                 auxType:     auxSymOff,
8444                 argLen:      4,
8445                 commutative: true,
8446                 symEffect:   SymRead,
8447                 asm:         x86.ACMPQ,
8448                 scale:       1,
8449                 reg: regInfo{
8450                         inputs: []inputInfo{
8451                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8452                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8453                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8454                         },
8455                 },
8456         },
8457         {
8458                 name:      "CMPLloadidx4",
8459                 auxType:   auxSymOff,
8460                 argLen:    4,
8461                 symEffect: SymRead,
8462                 asm:       x86.ACMPL,
8463                 scale:     4,
8464                 reg: regInfo{
8465                         inputs: []inputInfo{
8466                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8467                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8468                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8469                         },
8470                 },
8471         },
8472         {
8473                 name:        "CMPLloadidx1",
8474                 auxType:     auxSymOff,
8475                 argLen:      4,
8476                 commutative: true,
8477                 symEffect:   SymRead,
8478                 asm:         x86.ACMPL,
8479                 scale:       1,
8480                 reg: regInfo{
8481                         inputs: []inputInfo{
8482                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8483                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8484                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8485                         },
8486                 },
8487         },
8488         {
8489                 name:      "CMPWloadidx2",
8490                 auxType:   auxSymOff,
8491                 argLen:    4,
8492                 symEffect: SymRead,
8493                 asm:       x86.ACMPW,
8494                 scale:     2,
8495                 reg: regInfo{
8496                         inputs: []inputInfo{
8497                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8498                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8499                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8500                         },
8501                 },
8502         },
8503         {
8504                 name:        "CMPWloadidx1",
8505                 auxType:     auxSymOff,
8506                 argLen:      4,
8507                 commutative: true,
8508                 symEffect:   SymRead,
8509                 asm:         x86.ACMPW,
8510                 scale:       1,
8511                 reg: regInfo{
8512                         inputs: []inputInfo{
8513                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8514                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8515                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8516                         },
8517                 },
8518         },
8519         {
8520                 name:        "CMPBloadidx1",
8521                 auxType:     auxSymOff,
8522                 argLen:      4,
8523                 commutative: true,
8524                 symEffect:   SymRead,
8525                 asm:         x86.ACMPB,
8526                 scale:       1,
8527                 reg: regInfo{
8528                         inputs: []inputInfo{
8529                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8530                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8531                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8532                         },
8533                 },
8534         },
8535         {
8536                 name:      "CMPQconstloadidx8",
8537                 auxType:   auxSymValAndOff,
8538                 argLen:    3,
8539                 symEffect: SymRead,
8540                 asm:       x86.ACMPQ,
8541                 scale:     8,
8542                 reg: regInfo{
8543                         inputs: []inputInfo{
8544                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8545                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8546                         },
8547                 },
8548         },
8549         {
8550                 name:        "CMPQconstloadidx1",
8551                 auxType:     auxSymValAndOff,
8552                 argLen:      3,
8553                 commutative: true,
8554                 symEffect:   SymRead,
8555                 asm:         x86.ACMPQ,
8556                 scale:       1,
8557                 reg: regInfo{
8558                         inputs: []inputInfo{
8559                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8560                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8561                         },
8562                 },
8563         },
8564         {
8565                 name:      "CMPLconstloadidx4",
8566                 auxType:   auxSymValAndOff,
8567                 argLen:    3,
8568                 symEffect: SymRead,
8569                 asm:       x86.ACMPL,
8570                 scale:     4,
8571                 reg: regInfo{
8572                         inputs: []inputInfo{
8573                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8574                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8575                         },
8576                 },
8577         },
8578         {
8579                 name:        "CMPLconstloadidx1",
8580                 auxType:     auxSymValAndOff,
8581                 argLen:      3,
8582                 commutative: true,
8583                 symEffect:   SymRead,
8584                 asm:         x86.ACMPL,
8585                 scale:       1,
8586                 reg: regInfo{
8587                         inputs: []inputInfo{
8588                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8589                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8590                         },
8591                 },
8592         },
8593         {
8594                 name:      "CMPWconstloadidx2",
8595                 auxType:   auxSymValAndOff,
8596                 argLen:    3,
8597                 symEffect: SymRead,
8598                 asm:       x86.ACMPW,
8599                 scale:     2,
8600                 reg: regInfo{
8601                         inputs: []inputInfo{
8602                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8603                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8604                         },
8605                 },
8606         },
8607         {
8608                 name:        "CMPWconstloadidx1",
8609                 auxType:     auxSymValAndOff,
8610                 argLen:      3,
8611                 commutative: true,
8612                 symEffect:   SymRead,
8613                 asm:         x86.ACMPW,
8614                 scale:       1,
8615                 reg: regInfo{
8616                         inputs: []inputInfo{
8617                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8618                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8619                         },
8620                 },
8621         },
8622         {
8623                 name:        "CMPBconstloadidx1",
8624                 auxType:     auxSymValAndOff,
8625                 argLen:      3,
8626                 commutative: true,
8627                 symEffect:   SymRead,
8628                 asm:         x86.ACMPB,
8629                 scale:       1,
8630                 reg: regInfo{
8631                         inputs: []inputInfo{
8632                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8633                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8634                         },
8635                 },
8636         },
8637         {
8638                 name:   "UCOMISS",
8639                 argLen: 2,
8640                 asm:    x86.AUCOMISS,
8641                 reg: regInfo{
8642                         inputs: []inputInfo{
8643                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8644                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8645                         },
8646                 },
8647         },
8648         {
8649                 name:   "UCOMISD",
8650                 argLen: 2,
8651                 asm:    x86.AUCOMISD,
8652                 reg: regInfo{
8653                         inputs: []inputInfo{
8654                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8655                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8656                         },
8657                 },
8658         },
8659         {
8660                 name:   "BTL",
8661                 argLen: 2,
8662                 asm:    x86.ABTL,
8663                 reg: regInfo{
8664                         inputs: []inputInfo{
8665                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8666                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8667                         },
8668                 },
8669         },
8670         {
8671                 name:   "BTQ",
8672                 argLen: 2,
8673                 asm:    x86.ABTQ,
8674                 reg: regInfo{
8675                         inputs: []inputInfo{
8676                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8677                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8678                         },
8679                 },
8680         },
8681         {
8682                 name:         "BTCL",
8683                 argLen:       2,
8684                 resultInArg0: true,
8685                 clobberFlags: true,
8686                 asm:          x86.ABTCL,
8687                 reg: regInfo{
8688                         inputs: []inputInfo{
8689                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8690                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8691                         },
8692                         outputs: []outputInfo{
8693                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8694                         },
8695                 },
8696         },
8697         {
8698                 name:         "BTCQ",
8699                 argLen:       2,
8700                 resultInArg0: true,
8701                 clobberFlags: true,
8702                 asm:          x86.ABTCQ,
8703                 reg: regInfo{
8704                         inputs: []inputInfo{
8705                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8706                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8707                         },
8708                         outputs: []outputInfo{
8709                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8710                         },
8711                 },
8712         },
8713         {
8714                 name:         "BTRL",
8715                 argLen:       2,
8716                 resultInArg0: true,
8717                 clobberFlags: true,
8718                 asm:          x86.ABTRL,
8719                 reg: regInfo{
8720                         inputs: []inputInfo{
8721                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8722                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8723                         },
8724                         outputs: []outputInfo{
8725                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8726                         },
8727                 },
8728         },
8729         {
8730                 name:         "BTRQ",
8731                 argLen:       2,
8732                 resultInArg0: true,
8733                 clobberFlags: true,
8734                 asm:          x86.ABTRQ,
8735                 reg: regInfo{
8736                         inputs: []inputInfo{
8737                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8738                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8739                         },
8740                         outputs: []outputInfo{
8741                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8742                         },
8743                 },
8744         },
8745         {
8746                 name:         "BTSL",
8747                 argLen:       2,
8748                 resultInArg0: true,
8749                 clobberFlags: true,
8750                 asm:          x86.ABTSL,
8751                 reg: regInfo{
8752                         inputs: []inputInfo{
8753                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8754                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8755                         },
8756                         outputs: []outputInfo{
8757                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8758                         },
8759                 },
8760         },
8761         {
8762                 name:         "BTSQ",
8763                 argLen:       2,
8764                 resultInArg0: true,
8765                 clobberFlags: true,
8766                 asm:          x86.ABTSQ,
8767                 reg: regInfo{
8768                         inputs: []inputInfo{
8769                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8770                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8771                         },
8772                         outputs: []outputInfo{
8773                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8774                         },
8775                 },
8776         },
8777         {
8778                 name:    "BTLconst",
8779                 auxType: auxInt8,
8780                 argLen:  1,
8781                 asm:     x86.ABTL,
8782                 reg: regInfo{
8783                         inputs: []inputInfo{
8784                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8785                         },
8786                 },
8787         },
8788         {
8789                 name:    "BTQconst",
8790                 auxType: auxInt8,
8791                 argLen:  1,
8792                 asm:     x86.ABTQ,
8793                 reg: regInfo{
8794                         inputs: []inputInfo{
8795                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8796                         },
8797                 },
8798         },
8799         {
8800                 name:         "BTCQconst",
8801                 auxType:      auxInt8,
8802                 argLen:       1,
8803                 resultInArg0: true,
8804                 clobberFlags: true,
8805                 asm:          x86.ABTCQ,
8806                 reg: regInfo{
8807                         inputs: []inputInfo{
8808                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8809                         },
8810                         outputs: []outputInfo{
8811                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8812                         },
8813                 },
8814         },
8815         {
8816                 name:         "BTRQconst",
8817                 auxType:      auxInt8,
8818                 argLen:       1,
8819                 resultInArg0: true,
8820                 clobberFlags: true,
8821                 asm:          x86.ABTRQ,
8822                 reg: regInfo{
8823                         inputs: []inputInfo{
8824                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8825                         },
8826                         outputs: []outputInfo{
8827                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8828                         },
8829                 },
8830         },
8831         {
8832                 name:         "BTSQconst",
8833                 auxType:      auxInt8,
8834                 argLen:       1,
8835                 resultInArg0: true,
8836                 clobberFlags: true,
8837                 asm:          x86.ABTSQ,
8838                 reg: regInfo{
8839                         inputs: []inputInfo{
8840                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8841                         },
8842                         outputs: []outputInfo{
8843                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8844                         },
8845                 },
8846         },
8847         {
8848                 name:           "BTSQconstmodify",
8849                 auxType:        auxSymValAndOff,
8850                 argLen:         2,
8851                 clobberFlags:   true,
8852                 faultOnNilArg0: true,
8853                 symEffect:      SymRead | SymWrite,
8854                 asm:            x86.ABTSQ,
8855                 reg: regInfo{
8856                         inputs: []inputInfo{
8857                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8858                         },
8859                 },
8860         },
8861         {
8862                 name:           "BTRQconstmodify",
8863                 auxType:        auxSymValAndOff,
8864                 argLen:         2,
8865                 clobberFlags:   true,
8866                 faultOnNilArg0: true,
8867                 symEffect:      SymRead | SymWrite,
8868                 asm:            x86.ABTRQ,
8869                 reg: regInfo{
8870                         inputs: []inputInfo{
8871                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8872                         },
8873                 },
8874         },
8875         {
8876                 name:           "BTCQconstmodify",
8877                 auxType:        auxSymValAndOff,
8878                 argLen:         2,
8879                 clobberFlags:   true,
8880                 faultOnNilArg0: true,
8881                 symEffect:      SymRead | SymWrite,
8882                 asm:            x86.ABTCQ,
8883                 reg: regInfo{
8884                         inputs: []inputInfo{
8885                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8886                         },
8887                 },
8888         },
8889         {
8890                 name:        "TESTQ",
8891                 argLen:      2,
8892                 commutative: true,
8893                 asm:         x86.ATESTQ,
8894                 reg: regInfo{
8895                         inputs: []inputInfo{
8896                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8897                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8898                         },
8899                 },
8900         },
8901         {
8902                 name:        "TESTL",
8903                 argLen:      2,
8904                 commutative: true,
8905                 asm:         x86.ATESTL,
8906                 reg: regInfo{
8907                         inputs: []inputInfo{
8908                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8909                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8910                         },
8911                 },
8912         },
8913         {
8914                 name:        "TESTW",
8915                 argLen:      2,
8916                 commutative: true,
8917                 asm:         x86.ATESTW,
8918                 reg: regInfo{
8919                         inputs: []inputInfo{
8920                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8921                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8922                         },
8923                 },
8924         },
8925         {
8926                 name:        "TESTB",
8927                 argLen:      2,
8928                 commutative: true,
8929                 asm:         x86.ATESTB,
8930                 reg: regInfo{
8931                         inputs: []inputInfo{
8932                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8933                                 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8934                         },
8935                 },
8936         },
8937         {
8938                 name:    "TESTQconst",
8939                 auxType: auxInt32,
8940                 argLen:  1,
8941                 asm:     x86.ATESTQ,
8942                 reg: regInfo{
8943                         inputs: []inputInfo{
8944                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8945                         },
8946                 },
8947         },
8948         {
8949                 name:    "TESTLconst",
8950                 auxType: auxInt32,
8951                 argLen:  1,
8952                 asm:     x86.ATESTL,
8953                 reg: regInfo{
8954                         inputs: []inputInfo{
8955                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8956                         },
8957                 },
8958         },
8959         {
8960                 name:    "TESTWconst",
8961                 auxType: auxInt16,
8962                 argLen:  1,
8963                 asm:     x86.ATESTW,
8964                 reg: regInfo{
8965                         inputs: []inputInfo{
8966                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8967                         },
8968                 },
8969         },
8970         {
8971                 name:    "TESTBconst",
8972                 auxType: auxInt8,
8973                 argLen:  1,
8974                 asm:     x86.ATESTB,
8975                 reg: regInfo{
8976                         inputs: []inputInfo{
8977                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8978                         },
8979                 },
8980         },
8981         {
8982                 name:         "SHLQ",
8983                 argLen:       2,
8984                 resultInArg0: true,
8985                 clobberFlags: true,
8986                 asm:          x86.ASHLQ,
8987                 reg: regInfo{
8988                         inputs: []inputInfo{
8989                                 {1, 2},     // CX
8990                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8991                         },
8992                         outputs: []outputInfo{
8993                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8994                         },
8995                 },
8996         },
8997         {
8998                 name:         "SHLL",
8999                 argLen:       2,
9000                 resultInArg0: true,
9001                 clobberFlags: true,
9002                 asm:          x86.ASHLL,
9003                 reg: regInfo{
9004                         inputs: []inputInfo{
9005                                 {1, 2},     // CX
9006                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9007                         },
9008                         outputs: []outputInfo{
9009                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9010                         },
9011                 },
9012         },
9013         {
9014                 name:         "SHLQconst",
9015                 auxType:      auxInt8,
9016                 argLen:       1,
9017                 resultInArg0: true,
9018                 clobberFlags: true,
9019                 asm:          x86.ASHLQ,
9020                 reg: regInfo{
9021                         inputs: []inputInfo{
9022                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9023                         },
9024                         outputs: []outputInfo{
9025                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9026                         },
9027                 },
9028         },
9029         {
9030                 name:         "SHLLconst",
9031                 auxType:      auxInt8,
9032                 argLen:       1,
9033                 resultInArg0: true,
9034                 clobberFlags: true,
9035                 asm:          x86.ASHLL,
9036                 reg: regInfo{
9037                         inputs: []inputInfo{
9038                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9039                         },
9040                         outputs: []outputInfo{
9041                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9042                         },
9043                 },
9044         },
9045         {
9046                 name:         "SHRQ",
9047                 argLen:       2,
9048                 resultInArg0: true,
9049                 clobberFlags: true,
9050                 asm:          x86.ASHRQ,
9051                 reg: regInfo{
9052                         inputs: []inputInfo{
9053                                 {1, 2},     // CX
9054                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9055                         },
9056                         outputs: []outputInfo{
9057                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9058                         },
9059                 },
9060         },
9061         {
9062                 name:         "SHRL",
9063                 argLen:       2,
9064                 resultInArg0: true,
9065                 clobberFlags: true,
9066                 asm:          x86.ASHRL,
9067                 reg: regInfo{
9068                         inputs: []inputInfo{
9069                                 {1, 2},     // CX
9070                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9071                         },
9072                         outputs: []outputInfo{
9073                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9074                         },
9075                 },
9076         },
9077         {
9078                 name:         "SHRW",
9079                 argLen:       2,
9080                 resultInArg0: true,
9081                 clobberFlags: true,
9082                 asm:          x86.ASHRW,
9083                 reg: regInfo{
9084                         inputs: []inputInfo{
9085                                 {1, 2},     // CX
9086                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9087                         },
9088                         outputs: []outputInfo{
9089                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9090                         },
9091                 },
9092         },
9093         {
9094                 name:         "SHRB",
9095                 argLen:       2,
9096                 resultInArg0: true,
9097                 clobberFlags: true,
9098                 asm:          x86.ASHRB,
9099                 reg: regInfo{
9100                         inputs: []inputInfo{
9101                                 {1, 2},     // CX
9102                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9103                         },
9104                         outputs: []outputInfo{
9105                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9106                         },
9107                 },
9108         },
9109         {
9110                 name:         "SHRQconst",
9111                 auxType:      auxInt8,
9112                 argLen:       1,
9113                 resultInArg0: true,
9114                 clobberFlags: true,
9115                 asm:          x86.ASHRQ,
9116                 reg: regInfo{
9117                         inputs: []inputInfo{
9118                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9119                         },
9120                         outputs: []outputInfo{
9121                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9122                         },
9123                 },
9124         },
9125         {
9126                 name:         "SHRLconst",
9127                 auxType:      auxInt8,
9128                 argLen:       1,
9129                 resultInArg0: true,
9130                 clobberFlags: true,
9131                 asm:          x86.ASHRL,
9132                 reg: regInfo{
9133                         inputs: []inputInfo{
9134                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9135                         },
9136                         outputs: []outputInfo{
9137                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9138                         },
9139                 },
9140         },
9141         {
9142                 name:         "SHRWconst",
9143                 auxType:      auxInt8,
9144                 argLen:       1,
9145                 resultInArg0: true,
9146                 clobberFlags: true,
9147                 asm:          x86.ASHRW,
9148                 reg: regInfo{
9149                         inputs: []inputInfo{
9150                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9151                         },
9152                         outputs: []outputInfo{
9153                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9154                         },
9155                 },
9156         },
9157         {
9158                 name:         "SHRBconst",
9159                 auxType:      auxInt8,
9160                 argLen:       1,
9161                 resultInArg0: true,
9162                 clobberFlags: true,
9163                 asm:          x86.ASHRB,
9164                 reg: regInfo{
9165                         inputs: []inputInfo{
9166                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9167                         },
9168                         outputs: []outputInfo{
9169                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9170                         },
9171                 },
9172         },
9173         {
9174                 name:         "SARQ",
9175                 argLen:       2,
9176                 resultInArg0: true,
9177                 clobberFlags: true,
9178                 asm:          x86.ASARQ,
9179                 reg: regInfo{
9180                         inputs: []inputInfo{
9181                                 {1, 2},     // CX
9182                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9183                         },
9184                         outputs: []outputInfo{
9185                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9186                         },
9187                 },
9188         },
9189         {
9190                 name:         "SARL",
9191                 argLen:       2,
9192                 resultInArg0: true,
9193                 clobberFlags: true,
9194                 asm:          x86.ASARL,
9195                 reg: regInfo{
9196                         inputs: []inputInfo{
9197                                 {1, 2},     // CX
9198                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9199                         },
9200                         outputs: []outputInfo{
9201                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9202                         },
9203                 },
9204         },
9205         {
9206                 name:         "SARW",
9207                 argLen:       2,
9208                 resultInArg0: true,
9209                 clobberFlags: true,
9210                 asm:          x86.ASARW,
9211                 reg: regInfo{
9212                         inputs: []inputInfo{
9213                                 {1, 2},     // CX
9214                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9215                         },
9216                         outputs: []outputInfo{
9217                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9218                         },
9219                 },
9220         },
9221         {
9222                 name:         "SARB",
9223                 argLen:       2,
9224                 resultInArg0: true,
9225                 clobberFlags: true,
9226                 asm:          x86.ASARB,
9227                 reg: regInfo{
9228                         inputs: []inputInfo{
9229                                 {1, 2},     // CX
9230                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9231                         },
9232                         outputs: []outputInfo{
9233                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9234                         },
9235                 },
9236         },
9237         {
9238                 name:         "SARQconst",
9239                 auxType:      auxInt8,
9240                 argLen:       1,
9241                 resultInArg0: true,
9242                 clobberFlags: true,
9243                 asm:          x86.ASARQ,
9244                 reg: regInfo{
9245                         inputs: []inputInfo{
9246                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9247                         },
9248                         outputs: []outputInfo{
9249                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9250                         },
9251                 },
9252         },
9253         {
9254                 name:         "SARLconst",
9255                 auxType:      auxInt8,
9256                 argLen:       1,
9257                 resultInArg0: true,
9258                 clobberFlags: true,
9259                 asm:          x86.ASARL,
9260                 reg: regInfo{
9261                         inputs: []inputInfo{
9262                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9263                         },
9264                         outputs: []outputInfo{
9265                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9266                         },
9267                 },
9268         },
9269         {
9270                 name:         "SARWconst",
9271                 auxType:      auxInt8,
9272                 argLen:       1,
9273                 resultInArg0: true,
9274                 clobberFlags: true,
9275                 asm:          x86.ASARW,
9276                 reg: regInfo{
9277                         inputs: []inputInfo{
9278                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9279                         },
9280                         outputs: []outputInfo{
9281                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9282                         },
9283                 },
9284         },
9285         {
9286                 name:         "SARBconst",
9287                 auxType:      auxInt8,
9288                 argLen:       1,
9289                 resultInArg0: true,
9290                 clobberFlags: true,
9291                 asm:          x86.ASARB,
9292                 reg: regInfo{
9293                         inputs: []inputInfo{
9294                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9295                         },
9296                         outputs: []outputInfo{
9297                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9298                         },
9299                 },
9300         },
9301         {
9302                 name:         "SHRDQ",
9303                 argLen:       3,
9304                 resultInArg0: true,
9305                 clobberFlags: true,
9306                 asm:          x86.ASHRQ,
9307                 reg: regInfo{
9308                         inputs: []inputInfo{
9309                                 {2, 2},     // CX
9310                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9311                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9312                         },
9313                         outputs: []outputInfo{
9314                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9315                         },
9316                 },
9317         },
9318         {
9319                 name:         "SHLDQ",
9320                 argLen:       3,
9321                 resultInArg0: true,
9322                 clobberFlags: true,
9323                 asm:          x86.ASHLQ,
9324                 reg: regInfo{
9325                         inputs: []inputInfo{
9326                                 {2, 2},     // CX
9327                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9328                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9329                         },
9330                         outputs: []outputInfo{
9331                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9332                         },
9333                 },
9334         },
9335         {
9336                 name:         "ROLQ",
9337                 argLen:       2,
9338                 resultInArg0: true,
9339                 clobberFlags: true,
9340                 asm:          x86.AROLQ,
9341                 reg: regInfo{
9342                         inputs: []inputInfo{
9343                                 {1, 2},     // CX
9344                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9345                         },
9346                         outputs: []outputInfo{
9347                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9348                         },
9349                 },
9350         },
9351         {
9352                 name:         "ROLL",
9353                 argLen:       2,
9354                 resultInArg0: true,
9355                 clobberFlags: true,
9356                 asm:          x86.AROLL,
9357                 reg: regInfo{
9358                         inputs: []inputInfo{
9359                                 {1, 2},     // CX
9360                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9361                         },
9362                         outputs: []outputInfo{
9363                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9364                         },
9365                 },
9366         },
9367         {
9368                 name:         "ROLW",
9369                 argLen:       2,
9370                 resultInArg0: true,
9371                 clobberFlags: true,
9372                 asm:          x86.AROLW,
9373                 reg: regInfo{
9374                         inputs: []inputInfo{
9375                                 {1, 2},     // CX
9376                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9377                         },
9378                         outputs: []outputInfo{
9379                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9380                         },
9381                 },
9382         },
9383         {
9384                 name:         "ROLB",
9385                 argLen:       2,
9386                 resultInArg0: true,
9387                 clobberFlags: true,
9388                 asm:          x86.AROLB,
9389                 reg: regInfo{
9390                         inputs: []inputInfo{
9391                                 {1, 2},     // CX
9392                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9393                         },
9394                         outputs: []outputInfo{
9395                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9396                         },
9397                 },
9398         },
9399         {
9400                 name:         "RORQ",
9401                 argLen:       2,
9402                 resultInArg0: true,
9403                 clobberFlags: true,
9404                 asm:          x86.ARORQ,
9405                 reg: regInfo{
9406                         inputs: []inputInfo{
9407                                 {1, 2},     // CX
9408                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9409                         },
9410                         outputs: []outputInfo{
9411                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9412                         },
9413                 },
9414         },
9415         {
9416                 name:         "RORL",
9417                 argLen:       2,
9418                 resultInArg0: true,
9419                 clobberFlags: true,
9420                 asm:          x86.ARORL,
9421                 reg: regInfo{
9422                         inputs: []inputInfo{
9423                                 {1, 2},     // CX
9424                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9425                         },
9426                         outputs: []outputInfo{
9427                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9428                         },
9429                 },
9430         },
9431         {
9432                 name:         "RORW",
9433                 argLen:       2,
9434                 resultInArg0: true,
9435                 clobberFlags: true,
9436                 asm:          x86.ARORW,
9437                 reg: regInfo{
9438                         inputs: []inputInfo{
9439                                 {1, 2},     // CX
9440                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9441                         },
9442                         outputs: []outputInfo{
9443                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9444                         },
9445                 },
9446         },
9447         {
9448                 name:         "RORB",
9449                 argLen:       2,
9450                 resultInArg0: true,
9451                 clobberFlags: true,
9452                 asm:          x86.ARORB,
9453                 reg: regInfo{
9454                         inputs: []inputInfo{
9455                                 {1, 2},     // CX
9456                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9457                         },
9458                         outputs: []outputInfo{
9459                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9460                         },
9461                 },
9462         },
9463         {
9464                 name:         "ROLQconst",
9465                 auxType:      auxInt8,
9466                 argLen:       1,
9467                 resultInArg0: true,
9468                 clobberFlags: true,
9469                 asm:          x86.AROLQ,
9470                 reg: regInfo{
9471                         inputs: []inputInfo{
9472                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9473                         },
9474                         outputs: []outputInfo{
9475                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9476                         },
9477                 },
9478         },
9479         {
9480                 name:         "ROLLconst",
9481                 auxType:      auxInt8,
9482                 argLen:       1,
9483                 resultInArg0: true,
9484                 clobberFlags: true,
9485                 asm:          x86.AROLL,
9486                 reg: regInfo{
9487                         inputs: []inputInfo{
9488                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9489                         },
9490                         outputs: []outputInfo{
9491                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9492                         },
9493                 },
9494         },
9495         {
9496                 name:         "ROLWconst",
9497                 auxType:      auxInt8,
9498                 argLen:       1,
9499                 resultInArg0: true,
9500                 clobberFlags: true,
9501                 asm:          x86.AROLW,
9502                 reg: regInfo{
9503                         inputs: []inputInfo{
9504                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9505                         },
9506                         outputs: []outputInfo{
9507                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9508                         },
9509                 },
9510         },
9511         {
9512                 name:         "ROLBconst",
9513                 auxType:      auxInt8,
9514                 argLen:       1,
9515                 resultInArg0: true,
9516                 clobberFlags: true,
9517                 asm:          x86.AROLB,
9518                 reg: regInfo{
9519                         inputs: []inputInfo{
9520                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9521                         },
9522                         outputs: []outputInfo{
9523                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9524                         },
9525                 },
9526         },
9527         {
9528                 name:           "ADDLload",
9529                 auxType:        auxSymOff,
9530                 argLen:         3,
9531                 resultInArg0:   true,
9532                 clobberFlags:   true,
9533                 faultOnNilArg1: true,
9534                 symEffect:      SymRead,
9535                 asm:            x86.AADDL,
9536                 reg: regInfo{
9537                         inputs: []inputInfo{
9538                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9539                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9540                         },
9541                         outputs: []outputInfo{
9542                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9543                         },
9544                 },
9545         },
9546         {
9547                 name:           "ADDQload",
9548                 auxType:        auxSymOff,
9549                 argLen:         3,
9550                 resultInArg0:   true,
9551                 clobberFlags:   true,
9552                 faultOnNilArg1: true,
9553                 symEffect:      SymRead,
9554                 asm:            x86.AADDQ,
9555                 reg: regInfo{
9556                         inputs: []inputInfo{
9557                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9558                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9559                         },
9560                         outputs: []outputInfo{
9561                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9562                         },
9563                 },
9564         },
9565         {
9566                 name:           "SUBQload",
9567                 auxType:        auxSymOff,
9568                 argLen:         3,
9569                 resultInArg0:   true,
9570                 clobberFlags:   true,
9571                 faultOnNilArg1: true,
9572                 symEffect:      SymRead,
9573                 asm:            x86.ASUBQ,
9574                 reg: regInfo{
9575                         inputs: []inputInfo{
9576                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9577                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9578                         },
9579                         outputs: []outputInfo{
9580                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9581                         },
9582                 },
9583         },
9584         {
9585                 name:           "SUBLload",
9586                 auxType:        auxSymOff,
9587                 argLen:         3,
9588                 resultInArg0:   true,
9589                 clobberFlags:   true,
9590                 faultOnNilArg1: true,
9591                 symEffect:      SymRead,
9592                 asm:            x86.ASUBL,
9593                 reg: regInfo{
9594                         inputs: []inputInfo{
9595                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9596                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9597                         },
9598                         outputs: []outputInfo{
9599                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9600                         },
9601                 },
9602         },
9603         {
9604                 name:           "ANDLload",
9605                 auxType:        auxSymOff,
9606                 argLen:         3,
9607                 resultInArg0:   true,
9608                 clobberFlags:   true,
9609                 faultOnNilArg1: true,
9610                 symEffect:      SymRead,
9611                 asm:            x86.AANDL,
9612                 reg: regInfo{
9613                         inputs: []inputInfo{
9614                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9615                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9616                         },
9617                         outputs: []outputInfo{
9618                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9619                         },
9620                 },
9621         },
9622         {
9623                 name:           "ANDQload",
9624                 auxType:        auxSymOff,
9625                 argLen:         3,
9626                 resultInArg0:   true,
9627                 clobberFlags:   true,
9628                 faultOnNilArg1: true,
9629                 symEffect:      SymRead,
9630                 asm:            x86.AANDQ,
9631                 reg: regInfo{
9632                         inputs: []inputInfo{
9633                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9634                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9635                         },
9636                         outputs: []outputInfo{
9637                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9638                         },
9639                 },
9640         },
9641         {
9642                 name:           "ORQload",
9643                 auxType:        auxSymOff,
9644                 argLen:         3,
9645                 resultInArg0:   true,
9646                 clobberFlags:   true,
9647                 faultOnNilArg1: true,
9648                 symEffect:      SymRead,
9649                 asm:            x86.AORQ,
9650                 reg: regInfo{
9651                         inputs: []inputInfo{
9652                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9653                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9654                         },
9655                         outputs: []outputInfo{
9656                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9657                         },
9658                 },
9659         },
9660         {
9661                 name:           "ORLload",
9662                 auxType:        auxSymOff,
9663                 argLen:         3,
9664                 resultInArg0:   true,
9665                 clobberFlags:   true,
9666                 faultOnNilArg1: true,
9667                 symEffect:      SymRead,
9668                 asm:            x86.AORL,
9669                 reg: regInfo{
9670                         inputs: []inputInfo{
9671                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9672                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9673                         },
9674                         outputs: []outputInfo{
9675                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9676                         },
9677                 },
9678         },
9679         {
9680                 name:           "XORQload",
9681                 auxType:        auxSymOff,
9682                 argLen:         3,
9683                 resultInArg0:   true,
9684                 clobberFlags:   true,
9685                 faultOnNilArg1: true,
9686                 symEffect:      SymRead,
9687                 asm:            x86.AXORQ,
9688                 reg: regInfo{
9689                         inputs: []inputInfo{
9690                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9691                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9692                         },
9693                         outputs: []outputInfo{
9694                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9695                         },
9696                 },
9697         },
9698         {
9699                 name:           "XORLload",
9700                 auxType:        auxSymOff,
9701                 argLen:         3,
9702                 resultInArg0:   true,
9703                 clobberFlags:   true,
9704                 faultOnNilArg1: true,
9705                 symEffect:      SymRead,
9706                 asm:            x86.AXORL,
9707                 reg: regInfo{
9708                         inputs: []inputInfo{
9709                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9710                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9711                         },
9712                         outputs: []outputInfo{
9713                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9714                         },
9715                 },
9716         },
9717         {
9718                 name:         "ADDLloadidx1",
9719                 auxType:      auxSymOff,
9720                 argLen:       4,
9721                 resultInArg0: true,
9722                 clobberFlags: true,
9723                 symEffect:    SymRead,
9724                 asm:          x86.AADDL,
9725                 scale:        1,
9726                 reg: regInfo{
9727                         inputs: []inputInfo{
9728                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9729                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9730                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9731                         },
9732                         outputs: []outputInfo{
9733                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9734                         },
9735                 },
9736         },
9737         {
9738                 name:         "ADDLloadidx4",
9739                 auxType:      auxSymOff,
9740                 argLen:       4,
9741                 resultInArg0: true,
9742                 clobberFlags: true,
9743                 symEffect:    SymRead,
9744                 asm:          x86.AADDL,
9745                 scale:        4,
9746                 reg: regInfo{
9747                         inputs: []inputInfo{
9748                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9749                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9750                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9751                         },
9752                         outputs: []outputInfo{
9753                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9754                         },
9755                 },
9756         },
9757         {
9758                 name:         "ADDLloadidx8",
9759                 auxType:      auxSymOff,
9760                 argLen:       4,
9761                 resultInArg0: true,
9762                 clobberFlags: true,
9763                 symEffect:    SymRead,
9764                 asm:          x86.AADDL,
9765                 scale:        8,
9766                 reg: regInfo{
9767                         inputs: []inputInfo{
9768                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9769                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9770                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9771                         },
9772                         outputs: []outputInfo{
9773                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9774                         },
9775                 },
9776         },
9777         {
9778                 name:         "ADDQloadidx1",
9779                 auxType:      auxSymOff,
9780                 argLen:       4,
9781                 resultInArg0: true,
9782                 clobberFlags: true,
9783                 symEffect:    SymRead,
9784                 asm:          x86.AADDQ,
9785                 scale:        1,
9786                 reg: regInfo{
9787                         inputs: []inputInfo{
9788                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9789                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9790                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9791                         },
9792                         outputs: []outputInfo{
9793                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9794                         },
9795                 },
9796         },
9797         {
9798                 name:         "ADDQloadidx8",
9799                 auxType:      auxSymOff,
9800                 argLen:       4,
9801                 resultInArg0: true,
9802                 clobberFlags: true,
9803                 symEffect:    SymRead,
9804                 asm:          x86.AADDQ,
9805                 scale:        8,
9806                 reg: regInfo{
9807                         inputs: []inputInfo{
9808                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9809                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9810                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9811                         },
9812                         outputs: []outputInfo{
9813                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9814                         },
9815                 },
9816         },
9817         {
9818                 name:         "SUBLloadidx1",
9819                 auxType:      auxSymOff,
9820                 argLen:       4,
9821                 resultInArg0: true,
9822                 clobberFlags: true,
9823                 symEffect:    SymRead,
9824                 asm:          x86.ASUBL,
9825                 scale:        1,
9826                 reg: regInfo{
9827                         inputs: []inputInfo{
9828                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9829                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9830                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9831                         },
9832                         outputs: []outputInfo{
9833                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9834                         },
9835                 },
9836         },
9837         {
9838                 name:         "SUBLloadidx4",
9839                 auxType:      auxSymOff,
9840                 argLen:       4,
9841                 resultInArg0: true,
9842                 clobberFlags: true,
9843                 symEffect:    SymRead,
9844                 asm:          x86.ASUBL,
9845                 scale:        4,
9846                 reg: regInfo{
9847                         inputs: []inputInfo{
9848                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9849                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9850                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9851                         },
9852                         outputs: []outputInfo{
9853                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9854                         },
9855                 },
9856         },
9857         {
9858                 name:         "SUBLloadidx8",
9859                 auxType:      auxSymOff,
9860                 argLen:       4,
9861                 resultInArg0: true,
9862                 clobberFlags: true,
9863                 symEffect:    SymRead,
9864                 asm:          x86.ASUBL,
9865                 scale:        8,
9866                 reg: regInfo{
9867                         inputs: []inputInfo{
9868                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9869                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9870                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9871                         },
9872                         outputs: []outputInfo{
9873                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9874                         },
9875                 },
9876         },
9877         {
9878                 name:         "SUBQloadidx1",
9879                 auxType:      auxSymOff,
9880                 argLen:       4,
9881                 resultInArg0: true,
9882                 clobberFlags: true,
9883                 symEffect:    SymRead,
9884                 asm:          x86.ASUBQ,
9885                 scale:        1,
9886                 reg: regInfo{
9887                         inputs: []inputInfo{
9888                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9889                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9890                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9891                         },
9892                         outputs: []outputInfo{
9893                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9894                         },
9895                 },
9896         },
9897         {
9898                 name:         "SUBQloadidx8",
9899                 auxType:      auxSymOff,
9900                 argLen:       4,
9901                 resultInArg0: true,
9902                 clobberFlags: true,
9903                 symEffect:    SymRead,
9904                 asm:          x86.ASUBQ,
9905                 scale:        8,
9906                 reg: regInfo{
9907                         inputs: []inputInfo{
9908                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9909                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9910                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9911                         },
9912                         outputs: []outputInfo{
9913                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9914                         },
9915                 },
9916         },
9917         {
9918                 name:         "ANDLloadidx1",
9919                 auxType:      auxSymOff,
9920                 argLen:       4,
9921                 resultInArg0: true,
9922                 clobberFlags: true,
9923                 symEffect:    SymRead,
9924                 asm:          x86.AANDL,
9925                 scale:        1,
9926                 reg: regInfo{
9927                         inputs: []inputInfo{
9928                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9929                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9930                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9931                         },
9932                         outputs: []outputInfo{
9933                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9934                         },
9935                 },
9936         },
9937         {
9938                 name:         "ANDLloadidx4",
9939                 auxType:      auxSymOff,
9940                 argLen:       4,
9941                 resultInArg0: true,
9942                 clobberFlags: true,
9943                 symEffect:    SymRead,
9944                 asm:          x86.AANDL,
9945                 scale:        4,
9946                 reg: regInfo{
9947                         inputs: []inputInfo{
9948                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9949                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9950                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9951                         },
9952                         outputs: []outputInfo{
9953                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9954                         },
9955                 },
9956         },
9957         {
9958                 name:         "ANDLloadidx8",
9959                 auxType:      auxSymOff,
9960                 argLen:       4,
9961                 resultInArg0: true,
9962                 clobberFlags: true,
9963                 symEffect:    SymRead,
9964                 asm:          x86.AANDL,
9965                 scale:        8,
9966                 reg: regInfo{
9967                         inputs: []inputInfo{
9968                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9969                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9970                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9971                         },
9972                         outputs: []outputInfo{
9973                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9974                         },
9975                 },
9976         },
9977         {
9978                 name:         "ANDQloadidx1",
9979                 auxType:      auxSymOff,
9980                 argLen:       4,
9981                 resultInArg0: true,
9982                 clobberFlags: true,
9983                 symEffect:    SymRead,
9984                 asm:          x86.AANDQ,
9985                 scale:        1,
9986                 reg: regInfo{
9987                         inputs: []inputInfo{
9988                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9989                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9990                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9991                         },
9992                         outputs: []outputInfo{
9993                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9994                         },
9995                 },
9996         },
9997         {
9998                 name:         "ANDQloadidx8",
9999                 auxType:      auxSymOff,
10000                 argLen:       4,
10001                 resultInArg0: true,
10002                 clobberFlags: true,
10003                 symEffect:    SymRead,
10004                 asm:          x86.AANDQ,
10005                 scale:        8,
10006                 reg: regInfo{
10007                         inputs: []inputInfo{
10008                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10009                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10010                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10011                         },
10012                         outputs: []outputInfo{
10013                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10014                         },
10015                 },
10016         },
10017         {
10018                 name:         "ORLloadidx1",
10019                 auxType:      auxSymOff,
10020                 argLen:       4,
10021                 resultInArg0: true,
10022                 clobberFlags: true,
10023                 symEffect:    SymRead,
10024                 asm:          x86.AORL,
10025                 scale:        1,
10026                 reg: regInfo{
10027                         inputs: []inputInfo{
10028                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10029                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10030                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10031                         },
10032                         outputs: []outputInfo{
10033                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10034                         },
10035                 },
10036         },
10037         {
10038                 name:         "ORLloadidx4",
10039                 auxType:      auxSymOff,
10040                 argLen:       4,
10041                 resultInArg0: true,
10042                 clobberFlags: true,
10043                 symEffect:    SymRead,
10044                 asm:          x86.AORL,
10045                 scale:        4,
10046                 reg: regInfo{
10047                         inputs: []inputInfo{
10048                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10049                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10050                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10051                         },
10052                         outputs: []outputInfo{
10053                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10054                         },
10055                 },
10056         },
10057         {
10058                 name:         "ORLloadidx8",
10059                 auxType:      auxSymOff,
10060                 argLen:       4,
10061                 resultInArg0: true,
10062                 clobberFlags: true,
10063                 symEffect:    SymRead,
10064                 asm:          x86.AORL,
10065                 scale:        8,
10066                 reg: regInfo{
10067                         inputs: []inputInfo{
10068                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10069                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10070                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10071                         },
10072                         outputs: []outputInfo{
10073                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10074                         },
10075                 },
10076         },
10077         {
10078                 name:         "ORQloadidx1",
10079                 auxType:      auxSymOff,
10080                 argLen:       4,
10081                 resultInArg0: true,
10082                 clobberFlags: true,
10083                 symEffect:    SymRead,
10084                 asm:          x86.AORQ,
10085                 scale:        1,
10086                 reg: regInfo{
10087                         inputs: []inputInfo{
10088                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10089                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10090                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10091                         },
10092                         outputs: []outputInfo{
10093                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10094                         },
10095                 },
10096         },
10097         {
10098                 name:         "ORQloadidx8",
10099                 auxType:      auxSymOff,
10100                 argLen:       4,
10101                 resultInArg0: true,
10102                 clobberFlags: true,
10103                 symEffect:    SymRead,
10104                 asm:          x86.AORQ,
10105                 scale:        8,
10106                 reg: regInfo{
10107                         inputs: []inputInfo{
10108                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10109                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10110                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10111                         },
10112                         outputs: []outputInfo{
10113                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10114                         },
10115                 },
10116         },
10117         {
10118                 name:         "XORLloadidx1",
10119                 auxType:      auxSymOff,
10120                 argLen:       4,
10121                 resultInArg0: true,
10122                 clobberFlags: true,
10123                 symEffect:    SymRead,
10124                 asm:          x86.AXORL,
10125                 scale:        1,
10126                 reg: regInfo{
10127                         inputs: []inputInfo{
10128                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10129                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10130                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10131                         },
10132                         outputs: []outputInfo{
10133                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10134                         },
10135                 },
10136         },
10137         {
10138                 name:         "XORLloadidx4",
10139                 auxType:      auxSymOff,
10140                 argLen:       4,
10141                 resultInArg0: true,
10142                 clobberFlags: true,
10143                 symEffect:    SymRead,
10144                 asm:          x86.AXORL,
10145                 scale:        4,
10146                 reg: regInfo{
10147                         inputs: []inputInfo{
10148                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10149                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10150                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10151                         },
10152                         outputs: []outputInfo{
10153                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10154                         },
10155                 },
10156         },
10157         {
10158                 name:         "XORLloadidx8",
10159                 auxType:      auxSymOff,
10160                 argLen:       4,
10161                 resultInArg0: true,
10162                 clobberFlags: true,
10163                 symEffect:    SymRead,
10164                 asm:          x86.AXORL,
10165                 scale:        8,
10166                 reg: regInfo{
10167                         inputs: []inputInfo{
10168                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10169                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10170                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10171                         },
10172                         outputs: []outputInfo{
10173                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10174                         },
10175                 },
10176         },
10177         {
10178                 name:         "XORQloadidx1",
10179                 auxType:      auxSymOff,
10180                 argLen:       4,
10181                 resultInArg0: true,
10182                 clobberFlags: true,
10183                 symEffect:    SymRead,
10184                 asm:          x86.AXORQ,
10185                 scale:        1,
10186                 reg: regInfo{
10187                         inputs: []inputInfo{
10188                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10189                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10190                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10191                         },
10192                         outputs: []outputInfo{
10193                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10194                         },
10195                 },
10196         },
10197         {
10198                 name:         "XORQloadidx8",
10199                 auxType:      auxSymOff,
10200                 argLen:       4,
10201                 resultInArg0: true,
10202                 clobberFlags: true,
10203                 symEffect:    SymRead,
10204                 asm:          x86.AXORQ,
10205                 scale:        8,
10206                 reg: regInfo{
10207                         inputs: []inputInfo{
10208                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10209                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10210                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10211                         },
10212                         outputs: []outputInfo{
10213                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10214                         },
10215                 },
10216         },
10217         {
10218                 name:           "ADDQmodify",
10219                 auxType:        auxSymOff,
10220                 argLen:         3,
10221                 clobberFlags:   true,
10222                 faultOnNilArg0: true,
10223                 symEffect:      SymRead | SymWrite,
10224                 asm:            x86.AADDQ,
10225                 reg: regInfo{
10226                         inputs: []inputInfo{
10227                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10228                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10229                         },
10230                 },
10231         },
10232         {
10233                 name:           "SUBQmodify",
10234                 auxType:        auxSymOff,
10235                 argLen:         3,
10236                 clobberFlags:   true,
10237                 faultOnNilArg0: true,
10238                 symEffect:      SymRead | SymWrite,
10239                 asm:            x86.ASUBQ,
10240                 reg: regInfo{
10241                         inputs: []inputInfo{
10242                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10243                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10244                         },
10245                 },
10246         },
10247         {
10248                 name:           "ANDQmodify",
10249                 auxType:        auxSymOff,
10250                 argLen:         3,
10251                 clobberFlags:   true,
10252                 faultOnNilArg0: true,
10253                 symEffect:      SymRead | SymWrite,
10254                 asm:            x86.AANDQ,
10255                 reg: regInfo{
10256                         inputs: []inputInfo{
10257                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10258                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10259                         },
10260                 },
10261         },
10262         {
10263                 name:           "ORQmodify",
10264                 auxType:        auxSymOff,
10265                 argLen:         3,
10266                 clobberFlags:   true,
10267                 faultOnNilArg0: true,
10268                 symEffect:      SymRead | SymWrite,
10269                 asm:            x86.AORQ,
10270                 reg: regInfo{
10271                         inputs: []inputInfo{
10272                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10273                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10274                         },
10275                 },
10276         },
10277         {
10278                 name:           "XORQmodify",
10279                 auxType:        auxSymOff,
10280                 argLen:         3,
10281                 clobberFlags:   true,
10282                 faultOnNilArg0: true,
10283                 symEffect:      SymRead | SymWrite,
10284                 asm:            x86.AXORQ,
10285                 reg: regInfo{
10286                         inputs: []inputInfo{
10287                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10288                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10289                         },
10290                 },
10291         },
10292         {
10293                 name:           "ADDLmodify",
10294                 auxType:        auxSymOff,
10295                 argLen:         3,
10296                 clobberFlags:   true,
10297                 faultOnNilArg0: true,
10298                 symEffect:      SymRead | SymWrite,
10299                 asm:            x86.AADDL,
10300                 reg: regInfo{
10301                         inputs: []inputInfo{
10302                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10303                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10304                         },
10305                 },
10306         },
10307         {
10308                 name:           "SUBLmodify",
10309                 auxType:        auxSymOff,
10310                 argLen:         3,
10311                 clobberFlags:   true,
10312                 faultOnNilArg0: true,
10313                 symEffect:      SymRead | SymWrite,
10314                 asm:            x86.ASUBL,
10315                 reg: regInfo{
10316                         inputs: []inputInfo{
10317                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10318                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10319                         },
10320                 },
10321         },
10322         {
10323                 name:           "ANDLmodify",
10324                 auxType:        auxSymOff,
10325                 argLen:         3,
10326                 clobberFlags:   true,
10327                 faultOnNilArg0: true,
10328                 symEffect:      SymRead | SymWrite,
10329                 asm:            x86.AANDL,
10330                 reg: regInfo{
10331                         inputs: []inputInfo{
10332                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10333                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10334                         },
10335                 },
10336         },
10337         {
10338                 name:           "ORLmodify",
10339                 auxType:        auxSymOff,
10340                 argLen:         3,
10341                 clobberFlags:   true,
10342                 faultOnNilArg0: true,
10343                 symEffect:      SymRead | SymWrite,
10344                 asm:            x86.AORL,
10345                 reg: regInfo{
10346                         inputs: []inputInfo{
10347                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10348                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10349                         },
10350                 },
10351         },
10352         {
10353                 name:           "XORLmodify",
10354                 auxType:        auxSymOff,
10355                 argLen:         3,
10356                 clobberFlags:   true,
10357                 faultOnNilArg0: true,
10358                 symEffect:      SymRead | SymWrite,
10359                 asm:            x86.AXORL,
10360                 reg: regInfo{
10361                         inputs: []inputInfo{
10362                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10363                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10364                         },
10365                 },
10366         },
10367         {
10368                 name:         "ADDQmodifyidx1",
10369                 auxType:      auxSymOff,
10370                 argLen:       4,
10371                 clobberFlags: true,
10372                 symEffect:    SymRead | SymWrite,
10373                 asm:          x86.AADDQ,
10374                 scale:        1,
10375                 reg: regInfo{
10376                         inputs: []inputInfo{
10377                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10378                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10379                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10380                         },
10381                 },
10382         },
10383         {
10384                 name:         "ADDQmodifyidx8",
10385                 auxType:      auxSymOff,
10386                 argLen:       4,
10387                 clobberFlags: true,
10388                 symEffect:    SymRead | SymWrite,
10389                 asm:          x86.AADDQ,
10390                 scale:        8,
10391                 reg: regInfo{
10392                         inputs: []inputInfo{
10393                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10394                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10395                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10396                         },
10397                 },
10398         },
10399         {
10400                 name:         "SUBQmodifyidx1",
10401                 auxType:      auxSymOff,
10402                 argLen:       4,
10403                 clobberFlags: true,
10404                 symEffect:    SymRead | SymWrite,
10405                 asm:          x86.ASUBQ,
10406                 scale:        1,
10407                 reg: regInfo{
10408                         inputs: []inputInfo{
10409                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10410                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10411                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10412                         },
10413                 },
10414         },
10415         {
10416                 name:         "SUBQmodifyidx8",
10417                 auxType:      auxSymOff,
10418                 argLen:       4,
10419                 clobberFlags: true,
10420                 symEffect:    SymRead | SymWrite,
10421                 asm:          x86.ASUBQ,
10422                 scale:        8,
10423                 reg: regInfo{
10424                         inputs: []inputInfo{
10425                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10426                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10427                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10428                         },
10429                 },
10430         },
10431         {
10432                 name:         "ANDQmodifyidx1",
10433                 auxType:      auxSymOff,
10434                 argLen:       4,
10435                 clobberFlags: true,
10436                 symEffect:    SymRead | SymWrite,
10437                 asm:          x86.AANDQ,
10438                 scale:        1,
10439                 reg: regInfo{
10440                         inputs: []inputInfo{
10441                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10442                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10443                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10444                         },
10445                 },
10446         },
10447         {
10448                 name:         "ANDQmodifyidx8",
10449                 auxType:      auxSymOff,
10450                 argLen:       4,
10451                 clobberFlags: true,
10452                 symEffect:    SymRead | SymWrite,
10453                 asm:          x86.AANDQ,
10454                 scale:        8,
10455                 reg: regInfo{
10456                         inputs: []inputInfo{
10457                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10458                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10459                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10460                         },
10461                 },
10462         },
10463         {
10464                 name:         "ORQmodifyidx1",
10465                 auxType:      auxSymOff,
10466                 argLen:       4,
10467                 clobberFlags: true,
10468                 symEffect:    SymRead | SymWrite,
10469                 asm:          x86.AORQ,
10470                 scale:        1,
10471                 reg: regInfo{
10472                         inputs: []inputInfo{
10473                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10474                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10475                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10476                         },
10477                 },
10478         },
10479         {
10480                 name:         "ORQmodifyidx8",
10481                 auxType:      auxSymOff,
10482                 argLen:       4,
10483                 clobberFlags: true,
10484                 symEffect:    SymRead | SymWrite,
10485                 asm:          x86.AORQ,
10486                 scale:        8,
10487                 reg: regInfo{
10488                         inputs: []inputInfo{
10489                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10490                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10491                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10492                         },
10493                 },
10494         },
10495         {
10496                 name:         "XORQmodifyidx1",
10497                 auxType:      auxSymOff,
10498                 argLen:       4,
10499                 clobberFlags: true,
10500                 symEffect:    SymRead | SymWrite,
10501                 asm:          x86.AXORQ,
10502                 scale:        1,
10503                 reg: regInfo{
10504                         inputs: []inputInfo{
10505                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10506                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10507                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10508                         },
10509                 },
10510         },
10511         {
10512                 name:         "XORQmodifyidx8",
10513                 auxType:      auxSymOff,
10514                 argLen:       4,
10515                 clobberFlags: true,
10516                 symEffect:    SymRead | SymWrite,
10517                 asm:          x86.AXORQ,
10518                 scale:        8,
10519                 reg: regInfo{
10520                         inputs: []inputInfo{
10521                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10522                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10523                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10524                         },
10525                 },
10526         },
10527         {
10528                 name:         "ADDLmodifyidx1",
10529                 auxType:      auxSymOff,
10530                 argLen:       4,
10531                 clobberFlags: true,
10532                 symEffect:    SymRead | SymWrite,
10533                 asm:          x86.AADDL,
10534                 scale:        1,
10535                 reg: regInfo{
10536                         inputs: []inputInfo{
10537                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10538                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10539                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10540                         },
10541                 },
10542         },
10543         {
10544                 name:         "ADDLmodifyidx4",
10545                 auxType:      auxSymOff,
10546                 argLen:       4,
10547                 clobberFlags: true,
10548                 symEffect:    SymRead | SymWrite,
10549                 asm:          x86.AADDL,
10550                 scale:        4,
10551                 reg: regInfo{
10552                         inputs: []inputInfo{
10553                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10554                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10555                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10556                         },
10557                 },
10558         },
10559         {
10560                 name:         "ADDLmodifyidx8",
10561                 auxType:      auxSymOff,
10562                 argLen:       4,
10563                 clobberFlags: true,
10564                 symEffect:    SymRead | SymWrite,
10565                 asm:          x86.AADDL,
10566                 scale:        8,
10567                 reg: regInfo{
10568                         inputs: []inputInfo{
10569                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10570                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10571                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10572                         },
10573                 },
10574         },
10575         {
10576                 name:         "SUBLmodifyidx1",
10577                 auxType:      auxSymOff,
10578                 argLen:       4,
10579                 clobberFlags: true,
10580                 symEffect:    SymRead | SymWrite,
10581                 asm:          x86.ASUBL,
10582                 scale:        1,
10583                 reg: regInfo{
10584                         inputs: []inputInfo{
10585                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10586                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10587                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10588                         },
10589                 },
10590         },
10591         {
10592                 name:         "SUBLmodifyidx4",
10593                 auxType:      auxSymOff,
10594                 argLen:       4,
10595                 clobberFlags: true,
10596                 symEffect:    SymRead | SymWrite,
10597                 asm:          x86.ASUBL,
10598                 scale:        4,
10599                 reg: regInfo{
10600                         inputs: []inputInfo{
10601                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10602                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10603                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10604                         },
10605                 },
10606         },
10607         {
10608                 name:         "SUBLmodifyidx8",
10609                 auxType:      auxSymOff,
10610                 argLen:       4,
10611                 clobberFlags: true,
10612                 symEffect:    SymRead | SymWrite,
10613                 asm:          x86.ASUBL,
10614                 scale:        8,
10615                 reg: regInfo{
10616                         inputs: []inputInfo{
10617                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10618                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10619                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10620                         },
10621                 },
10622         },
10623         {
10624                 name:         "ANDLmodifyidx1",
10625                 auxType:      auxSymOff,
10626                 argLen:       4,
10627                 clobberFlags: true,
10628                 symEffect:    SymRead | SymWrite,
10629                 asm:          x86.AANDL,
10630                 scale:        1,
10631                 reg: regInfo{
10632                         inputs: []inputInfo{
10633                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10634                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10635                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10636                         },
10637                 },
10638         },
10639         {
10640                 name:         "ANDLmodifyidx4",
10641                 auxType:      auxSymOff,
10642                 argLen:       4,
10643                 clobberFlags: true,
10644                 symEffect:    SymRead | SymWrite,
10645                 asm:          x86.AANDL,
10646                 scale:        4,
10647                 reg: regInfo{
10648                         inputs: []inputInfo{
10649                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10650                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10651                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10652                         },
10653                 },
10654         },
10655         {
10656                 name:         "ANDLmodifyidx8",
10657                 auxType:      auxSymOff,
10658                 argLen:       4,
10659                 clobberFlags: true,
10660                 symEffect:    SymRead | SymWrite,
10661                 asm:          x86.AANDL,
10662                 scale:        8,
10663                 reg: regInfo{
10664                         inputs: []inputInfo{
10665                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10666                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10667                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10668                         },
10669                 },
10670         },
10671         {
10672                 name:         "ORLmodifyidx1",
10673                 auxType:      auxSymOff,
10674                 argLen:       4,
10675                 clobberFlags: true,
10676                 symEffect:    SymRead | SymWrite,
10677                 asm:          x86.AORL,
10678                 scale:        1,
10679                 reg: regInfo{
10680                         inputs: []inputInfo{
10681                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10682                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10683                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10684                         },
10685                 },
10686         },
10687         {
10688                 name:         "ORLmodifyidx4",
10689                 auxType:      auxSymOff,
10690                 argLen:       4,
10691                 clobberFlags: true,
10692                 symEffect:    SymRead | SymWrite,
10693                 asm:          x86.AORL,
10694                 scale:        4,
10695                 reg: regInfo{
10696                         inputs: []inputInfo{
10697                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10698                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10699                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10700                         },
10701                 },
10702         },
10703         {
10704                 name:         "ORLmodifyidx8",
10705                 auxType:      auxSymOff,
10706                 argLen:       4,
10707                 clobberFlags: true,
10708                 symEffect:    SymRead | SymWrite,
10709                 asm:          x86.AORL,
10710                 scale:        8,
10711                 reg: regInfo{
10712                         inputs: []inputInfo{
10713                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10714                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10715                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10716                         },
10717                 },
10718         },
10719         {
10720                 name:         "XORLmodifyidx1",
10721                 auxType:      auxSymOff,
10722                 argLen:       4,
10723                 clobberFlags: true,
10724                 symEffect:    SymRead | SymWrite,
10725                 asm:          x86.AXORL,
10726                 scale:        1,
10727                 reg: regInfo{
10728                         inputs: []inputInfo{
10729                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10730                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10731                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10732                         },
10733                 },
10734         },
10735         {
10736                 name:         "XORLmodifyidx4",
10737                 auxType:      auxSymOff,
10738                 argLen:       4,
10739                 clobberFlags: true,
10740                 symEffect:    SymRead | SymWrite,
10741                 asm:          x86.AXORL,
10742                 scale:        4,
10743                 reg: regInfo{
10744                         inputs: []inputInfo{
10745                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10746                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10747                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10748                         },
10749                 },
10750         },
10751         {
10752                 name:         "XORLmodifyidx8",
10753                 auxType:      auxSymOff,
10754                 argLen:       4,
10755                 clobberFlags: true,
10756                 symEffect:    SymRead | SymWrite,
10757                 asm:          x86.AXORL,
10758                 scale:        8,
10759                 reg: regInfo{
10760                         inputs: []inputInfo{
10761                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10762                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10763                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10764                         },
10765                 },
10766         },
10767         {
10768                 name:         "ADDQconstmodifyidx1",
10769                 auxType:      auxSymValAndOff,
10770                 argLen:       3,
10771                 clobberFlags: true,
10772                 symEffect:    SymRead | SymWrite,
10773                 asm:          x86.AADDQ,
10774                 scale:        1,
10775                 reg: regInfo{
10776                         inputs: []inputInfo{
10777                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10778                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10779                         },
10780                 },
10781         },
10782         {
10783                 name:         "ADDQconstmodifyidx8",
10784                 auxType:      auxSymValAndOff,
10785                 argLen:       3,
10786                 clobberFlags: true,
10787                 symEffect:    SymRead | SymWrite,
10788                 asm:          x86.AADDQ,
10789                 scale:        8,
10790                 reg: regInfo{
10791                         inputs: []inputInfo{
10792                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10793                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10794                         },
10795                 },
10796         },
10797         {
10798                 name:         "ANDQconstmodifyidx1",
10799                 auxType:      auxSymValAndOff,
10800                 argLen:       3,
10801                 clobberFlags: true,
10802                 symEffect:    SymRead | SymWrite,
10803                 asm:          x86.AANDQ,
10804                 scale:        1,
10805                 reg: regInfo{
10806                         inputs: []inputInfo{
10807                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10808                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10809                         },
10810                 },
10811         },
10812         {
10813                 name:         "ANDQconstmodifyidx8",
10814                 auxType:      auxSymValAndOff,
10815                 argLen:       3,
10816                 clobberFlags: true,
10817                 symEffect:    SymRead | SymWrite,
10818                 asm:          x86.AANDQ,
10819                 scale:        8,
10820                 reg: regInfo{
10821                         inputs: []inputInfo{
10822                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10823                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10824                         },
10825                 },
10826         },
10827         {
10828                 name:         "ORQconstmodifyidx1",
10829                 auxType:      auxSymValAndOff,
10830                 argLen:       3,
10831                 clobberFlags: true,
10832                 symEffect:    SymRead | SymWrite,
10833                 asm:          x86.AORQ,
10834                 scale:        1,
10835                 reg: regInfo{
10836                         inputs: []inputInfo{
10837                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10838                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10839                         },
10840                 },
10841         },
10842         {
10843                 name:         "ORQconstmodifyidx8",
10844                 auxType:      auxSymValAndOff,
10845                 argLen:       3,
10846                 clobberFlags: true,
10847                 symEffect:    SymRead | SymWrite,
10848                 asm:          x86.AORQ,
10849                 scale:        8,
10850                 reg: regInfo{
10851                         inputs: []inputInfo{
10852                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10853                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10854                         },
10855                 },
10856         },
10857         {
10858                 name:         "XORQconstmodifyidx1",
10859                 auxType:      auxSymValAndOff,
10860                 argLen:       3,
10861                 clobberFlags: true,
10862                 symEffect:    SymRead | SymWrite,
10863                 asm:          x86.AXORQ,
10864                 scale:        1,
10865                 reg: regInfo{
10866                         inputs: []inputInfo{
10867                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10868                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10869                         },
10870                 },
10871         },
10872         {
10873                 name:         "XORQconstmodifyidx8",
10874                 auxType:      auxSymValAndOff,
10875                 argLen:       3,
10876                 clobberFlags: true,
10877                 symEffect:    SymRead | SymWrite,
10878                 asm:          x86.AXORQ,
10879                 scale:        8,
10880                 reg: regInfo{
10881                         inputs: []inputInfo{
10882                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10883                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10884                         },
10885                 },
10886         },
10887         {
10888                 name:         "ADDLconstmodifyidx1",
10889                 auxType:      auxSymValAndOff,
10890                 argLen:       3,
10891                 clobberFlags: true,
10892                 symEffect:    SymRead | SymWrite,
10893                 asm:          x86.AADDL,
10894                 scale:        1,
10895                 reg: regInfo{
10896                         inputs: []inputInfo{
10897                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10898                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10899                         },
10900                 },
10901         },
10902         {
10903                 name:         "ADDLconstmodifyidx4",
10904                 auxType:      auxSymValAndOff,
10905                 argLen:       3,
10906                 clobberFlags: true,
10907                 symEffect:    SymRead | SymWrite,
10908                 asm:          x86.AADDL,
10909                 scale:        4,
10910                 reg: regInfo{
10911                         inputs: []inputInfo{
10912                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10913                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10914                         },
10915                 },
10916         },
10917         {
10918                 name:         "ADDLconstmodifyidx8",
10919                 auxType:      auxSymValAndOff,
10920                 argLen:       3,
10921                 clobberFlags: true,
10922                 symEffect:    SymRead | SymWrite,
10923                 asm:          x86.AADDL,
10924                 scale:        8,
10925                 reg: regInfo{
10926                         inputs: []inputInfo{
10927                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10928                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10929                         },
10930                 },
10931         },
10932         {
10933                 name:         "ANDLconstmodifyidx1",
10934                 auxType:      auxSymValAndOff,
10935                 argLen:       3,
10936                 clobberFlags: true,
10937                 symEffect:    SymRead | SymWrite,
10938                 asm:          x86.AANDL,
10939                 scale:        1,
10940                 reg: regInfo{
10941                         inputs: []inputInfo{
10942                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10943                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10944                         },
10945                 },
10946         },
10947         {
10948                 name:         "ANDLconstmodifyidx4",
10949                 auxType:      auxSymValAndOff,
10950                 argLen:       3,
10951                 clobberFlags: true,
10952                 symEffect:    SymRead | SymWrite,
10953                 asm:          x86.AANDL,
10954                 scale:        4,
10955                 reg: regInfo{
10956                         inputs: []inputInfo{
10957                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10958                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10959                         },
10960                 },
10961         },
10962         {
10963                 name:         "ANDLconstmodifyidx8",
10964                 auxType:      auxSymValAndOff,
10965                 argLen:       3,
10966                 clobberFlags: true,
10967                 symEffect:    SymRead | SymWrite,
10968                 asm:          x86.AANDL,
10969                 scale:        8,
10970                 reg: regInfo{
10971                         inputs: []inputInfo{
10972                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10973                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10974                         },
10975                 },
10976         },
10977         {
10978                 name:         "ORLconstmodifyidx1",
10979                 auxType:      auxSymValAndOff,
10980                 argLen:       3,
10981                 clobberFlags: true,
10982                 symEffect:    SymRead | SymWrite,
10983                 asm:          x86.AORL,
10984                 scale:        1,
10985                 reg: regInfo{
10986                         inputs: []inputInfo{
10987                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10988                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10989                         },
10990                 },
10991         },
10992         {
10993                 name:         "ORLconstmodifyidx4",
10994                 auxType:      auxSymValAndOff,
10995                 argLen:       3,
10996                 clobberFlags: true,
10997                 symEffect:    SymRead | SymWrite,
10998                 asm:          x86.AORL,
10999                 scale:        4,
11000                 reg: regInfo{
11001                         inputs: []inputInfo{
11002                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
11003                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11004                         },
11005                 },
11006         },
11007         {
11008                 name:         "ORLconstmodifyidx8",
11009                 auxType:      auxSymValAndOff,
11010                 argLen:       3,
11011                 clobberFlags: true,
11012                 symEffect:    SymRead | SymWrite,
11013                 asm:          x86.AORL,
11014                 scale:        8,
11015                 reg: regInfo{
11016                         inputs: []inputInfo{
11017                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
11018                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11019                         },
11020                 },
11021         },
11022         {
11023                 name:         "XORLconstmodifyidx1",
11024                 auxType:      auxSymValAndOff,
11025                 argLen:       3,
11026                 clobberFlags: true,
11027                 symEffect:    SymRead | SymWrite,
11028                 asm:          x86.AXORL,
11029                 scale:        1,
11030                 reg: regInfo{
11031                         inputs: []inputInfo{
11032                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
11033                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11034                         },
11035                 },
11036         },
11037         {
11038                 name:         "XORLconstmodifyidx4",
11039                 auxType:      auxSymValAndOff,
11040                 argLen:       3,
11041                 clobberFlags: true,
11042                 symEffect:    SymRead | SymWrite,
11043                 asm:          x86.AXORL,
11044                 scale:        4,
11045                 reg: regInfo{
11046                         inputs: []inputInfo{
11047                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
11048                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11049                         },
11050                 },
11051         },
11052         {
11053                 name:         "XORLconstmodifyidx8",
11054                 auxType:      auxSymValAndOff,
11055                 argLen:       3,
11056                 clobberFlags: true,
11057                 symEffect:    SymRead | SymWrite,
11058                 asm:          x86.AXORL,
11059                 scale:        8,
11060                 reg: regInfo{
11061                         inputs: []inputInfo{
11062                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
11063                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11064                         },
11065                 },
11066         },
11067         {
11068                 name:         "NEGQ",
11069                 argLen:       1,
11070                 resultInArg0: true,
11071                 clobberFlags: true,
11072                 asm:          x86.ANEGQ,
11073                 reg: regInfo{
11074                         inputs: []inputInfo{
11075                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11076                         },
11077                         outputs: []outputInfo{
11078                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11079                         },
11080                 },
11081         },
11082         {
11083                 name:         "NEGL",
11084                 argLen:       1,
11085                 resultInArg0: true,
11086                 clobberFlags: true,
11087                 asm:          x86.ANEGL,
11088                 reg: regInfo{
11089                         inputs: []inputInfo{
11090                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11091                         },
11092                         outputs: []outputInfo{
11093                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11094                         },
11095                 },
11096         },
11097         {
11098                 name:         "NOTQ",
11099                 argLen:       1,
11100                 resultInArg0: true,
11101                 asm:          x86.ANOTQ,
11102                 reg: regInfo{
11103                         inputs: []inputInfo{
11104                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11105                         },
11106                         outputs: []outputInfo{
11107                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11108                         },
11109                 },
11110         },
11111         {
11112                 name:         "NOTL",
11113                 argLen:       1,
11114                 resultInArg0: true,
11115                 asm:          x86.ANOTL,
11116                 reg: regInfo{
11117                         inputs: []inputInfo{
11118                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11119                         },
11120                         outputs: []outputInfo{
11121                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11122                         },
11123                 },
11124         },
11125         {
11126                 name:   "BSFQ",
11127                 argLen: 1,
11128                 asm:    x86.ABSFQ,
11129                 reg: regInfo{
11130                         inputs: []inputInfo{
11131                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11132                         },
11133                         outputs: []outputInfo{
11134                                 {1, 0},
11135                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11136                         },
11137                 },
11138         },
11139         {
11140                 name:         "BSFL",
11141                 argLen:       1,
11142                 clobberFlags: true,
11143                 asm:          x86.ABSFL,
11144                 reg: regInfo{
11145                         inputs: []inputInfo{
11146                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11147                         },
11148                         outputs: []outputInfo{
11149                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11150                         },
11151                 },
11152         },
11153         {
11154                 name:   "BSRQ",
11155                 argLen: 1,
11156                 asm:    x86.ABSRQ,
11157                 reg: regInfo{
11158                         inputs: []inputInfo{
11159                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11160                         },
11161                         outputs: []outputInfo{
11162                                 {1, 0},
11163                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11164                         },
11165                 },
11166         },
11167         {
11168                 name:         "BSRL",
11169                 argLen:       1,
11170                 clobberFlags: true,
11171                 asm:          x86.ABSRL,
11172                 reg: regInfo{
11173                         inputs: []inputInfo{
11174                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11175                         },
11176                         outputs: []outputInfo{
11177                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11178                         },
11179                 },
11180         },
11181         {
11182                 name:         "CMOVQEQ",
11183                 argLen:       3,
11184                 resultInArg0: true,
11185                 asm:          x86.ACMOVQEQ,
11186                 reg: regInfo{
11187                         inputs: []inputInfo{
11188                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11189                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11190                         },
11191                         outputs: []outputInfo{
11192                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11193                         },
11194                 },
11195         },
11196         {
11197                 name:         "CMOVQNE",
11198                 argLen:       3,
11199                 resultInArg0: true,
11200                 asm:          x86.ACMOVQNE,
11201                 reg: regInfo{
11202                         inputs: []inputInfo{
11203                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11204                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11205                         },
11206                         outputs: []outputInfo{
11207                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11208                         },
11209                 },
11210         },
11211         {
11212                 name:         "CMOVQLT",
11213                 argLen:       3,
11214                 resultInArg0: true,
11215                 asm:          x86.ACMOVQLT,
11216                 reg: regInfo{
11217                         inputs: []inputInfo{
11218                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11219                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11220                         },
11221                         outputs: []outputInfo{
11222                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11223                         },
11224                 },
11225         },
11226         {
11227                 name:         "CMOVQGT",
11228                 argLen:       3,
11229                 resultInArg0: true,
11230                 asm:          x86.ACMOVQGT,
11231                 reg: regInfo{
11232                         inputs: []inputInfo{
11233                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11234                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11235                         },
11236                         outputs: []outputInfo{
11237                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11238                         },
11239                 },
11240         },
11241         {
11242                 name:         "CMOVQLE",
11243                 argLen:       3,
11244                 resultInArg0: true,
11245                 asm:          x86.ACMOVQLE,
11246                 reg: regInfo{
11247                         inputs: []inputInfo{
11248                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11249                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11250                         },
11251                         outputs: []outputInfo{
11252                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11253                         },
11254                 },
11255         },
11256         {
11257                 name:         "CMOVQGE",
11258                 argLen:       3,
11259                 resultInArg0: true,
11260                 asm:          x86.ACMOVQGE,
11261                 reg: regInfo{
11262                         inputs: []inputInfo{
11263                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11264                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11265                         },
11266                         outputs: []outputInfo{
11267                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11268                         },
11269                 },
11270         },
11271         {
11272                 name:         "CMOVQLS",
11273                 argLen:       3,
11274                 resultInArg0: true,
11275                 asm:          x86.ACMOVQLS,
11276                 reg: regInfo{
11277                         inputs: []inputInfo{
11278                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11279                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11280                         },
11281                         outputs: []outputInfo{
11282                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11283                         },
11284                 },
11285         },
11286         {
11287                 name:         "CMOVQHI",
11288                 argLen:       3,
11289                 resultInArg0: true,
11290                 asm:          x86.ACMOVQHI,
11291                 reg: regInfo{
11292                         inputs: []inputInfo{
11293                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11294                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11295                         },
11296                         outputs: []outputInfo{
11297                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11298                         },
11299                 },
11300         },
11301         {
11302                 name:         "CMOVQCC",
11303                 argLen:       3,
11304                 resultInArg0: true,
11305                 asm:          x86.ACMOVQCC,
11306                 reg: regInfo{
11307                         inputs: []inputInfo{
11308                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11309                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11310                         },
11311                         outputs: []outputInfo{
11312                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11313                         },
11314                 },
11315         },
11316         {
11317                 name:         "CMOVQCS",
11318                 argLen:       3,
11319                 resultInArg0: true,
11320                 asm:          x86.ACMOVQCS,
11321                 reg: regInfo{
11322                         inputs: []inputInfo{
11323                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11324                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11325                         },
11326                         outputs: []outputInfo{
11327                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11328                         },
11329                 },
11330         },
11331         {
11332                 name:         "CMOVLEQ",
11333                 argLen:       3,
11334                 resultInArg0: true,
11335                 asm:          x86.ACMOVLEQ,
11336                 reg: regInfo{
11337                         inputs: []inputInfo{
11338                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11339                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11340                         },
11341                         outputs: []outputInfo{
11342                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11343                         },
11344                 },
11345         },
11346         {
11347                 name:         "CMOVLNE",
11348                 argLen:       3,
11349                 resultInArg0: true,
11350                 asm:          x86.ACMOVLNE,
11351                 reg: regInfo{
11352                         inputs: []inputInfo{
11353                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11354                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11355                         },
11356                         outputs: []outputInfo{
11357                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11358                         },
11359                 },
11360         },
11361         {
11362                 name:         "CMOVLLT",
11363                 argLen:       3,
11364                 resultInArg0: true,
11365                 asm:          x86.ACMOVLLT,
11366                 reg: regInfo{
11367                         inputs: []inputInfo{
11368                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11369                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11370                         },
11371                         outputs: []outputInfo{
11372                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11373                         },
11374                 },
11375         },
11376         {
11377                 name:         "CMOVLGT",
11378                 argLen:       3,
11379                 resultInArg0: true,
11380                 asm:          x86.ACMOVLGT,
11381                 reg: regInfo{
11382                         inputs: []inputInfo{
11383                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11384                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11385                         },
11386                         outputs: []outputInfo{
11387                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11388                         },
11389                 },
11390         },
11391         {
11392                 name:         "CMOVLLE",
11393                 argLen:       3,
11394                 resultInArg0: true,
11395                 asm:          x86.ACMOVLLE,
11396                 reg: regInfo{
11397                         inputs: []inputInfo{
11398                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11399                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11400                         },
11401                         outputs: []outputInfo{
11402                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11403                         },
11404                 },
11405         },
11406         {
11407                 name:         "CMOVLGE",
11408                 argLen:       3,
11409                 resultInArg0: true,
11410                 asm:          x86.ACMOVLGE,
11411                 reg: regInfo{
11412                         inputs: []inputInfo{
11413                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11414                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11415                         },
11416                         outputs: []outputInfo{
11417                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11418                         },
11419                 },
11420         },
11421         {
11422                 name:         "CMOVLLS",
11423                 argLen:       3,
11424                 resultInArg0: true,
11425                 asm:          x86.ACMOVLLS,
11426                 reg: regInfo{
11427                         inputs: []inputInfo{
11428                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11429                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11430                         },
11431                         outputs: []outputInfo{
11432                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11433                         },
11434                 },
11435         },
11436         {
11437                 name:         "CMOVLHI",
11438                 argLen:       3,
11439                 resultInArg0: true,
11440                 asm:          x86.ACMOVLHI,
11441                 reg: regInfo{
11442                         inputs: []inputInfo{
11443                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11444                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11445                         },
11446                         outputs: []outputInfo{
11447                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11448                         },
11449                 },
11450         },
11451         {
11452                 name:         "CMOVLCC",
11453                 argLen:       3,
11454                 resultInArg0: true,
11455                 asm:          x86.ACMOVLCC,
11456                 reg: regInfo{
11457                         inputs: []inputInfo{
11458                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11459                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11460                         },
11461                         outputs: []outputInfo{
11462                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11463                         },
11464                 },
11465         },
11466         {
11467                 name:         "CMOVLCS",
11468                 argLen:       3,
11469                 resultInArg0: true,
11470                 asm:          x86.ACMOVLCS,
11471                 reg: regInfo{
11472                         inputs: []inputInfo{
11473                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11474                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11475                         },
11476                         outputs: []outputInfo{
11477                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11478                         },
11479                 },
11480         },
11481         {
11482                 name:         "CMOVWEQ",
11483                 argLen:       3,
11484                 resultInArg0: true,
11485                 asm:          x86.ACMOVWEQ,
11486                 reg: regInfo{
11487                         inputs: []inputInfo{
11488                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11489                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11490                         },
11491                         outputs: []outputInfo{
11492                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11493                         },
11494                 },
11495         },
11496         {
11497                 name:         "CMOVWNE",
11498                 argLen:       3,
11499                 resultInArg0: true,
11500                 asm:          x86.ACMOVWNE,
11501                 reg: regInfo{
11502                         inputs: []inputInfo{
11503                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11504                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11505                         },
11506                         outputs: []outputInfo{
11507                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11508                         },
11509                 },
11510         },
11511         {
11512                 name:         "CMOVWLT",
11513                 argLen:       3,
11514                 resultInArg0: true,
11515                 asm:          x86.ACMOVWLT,
11516                 reg: regInfo{
11517                         inputs: []inputInfo{
11518                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11519                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11520                         },
11521                         outputs: []outputInfo{
11522                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11523                         },
11524                 },
11525         },
11526         {
11527                 name:         "CMOVWGT",
11528                 argLen:       3,
11529                 resultInArg0: true,
11530                 asm:          x86.ACMOVWGT,
11531                 reg: regInfo{
11532                         inputs: []inputInfo{
11533                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11534                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11535                         },
11536                         outputs: []outputInfo{
11537                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11538                         },
11539                 },
11540         },
11541         {
11542                 name:         "CMOVWLE",
11543                 argLen:       3,
11544                 resultInArg0: true,
11545                 asm:          x86.ACMOVWLE,
11546                 reg: regInfo{
11547                         inputs: []inputInfo{
11548                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11549                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11550                         },
11551                         outputs: []outputInfo{
11552                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11553                         },
11554                 },
11555         },
11556         {
11557                 name:         "CMOVWGE",
11558                 argLen:       3,
11559                 resultInArg0: true,
11560                 asm:          x86.ACMOVWGE,
11561                 reg: regInfo{
11562                         inputs: []inputInfo{
11563                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11564                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11565                         },
11566                         outputs: []outputInfo{
11567                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11568                         },
11569                 },
11570         },
11571         {
11572                 name:         "CMOVWLS",
11573                 argLen:       3,
11574                 resultInArg0: true,
11575                 asm:          x86.ACMOVWLS,
11576                 reg: regInfo{
11577                         inputs: []inputInfo{
11578                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11579                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11580                         },
11581                         outputs: []outputInfo{
11582                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11583                         },
11584                 },
11585         },
11586         {
11587                 name:         "CMOVWHI",
11588                 argLen:       3,
11589                 resultInArg0: true,
11590                 asm:          x86.ACMOVWHI,
11591                 reg: regInfo{
11592                         inputs: []inputInfo{
11593                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11594                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11595                         },
11596                         outputs: []outputInfo{
11597                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11598                         },
11599                 },
11600         },
11601         {
11602                 name:         "CMOVWCC",
11603                 argLen:       3,
11604                 resultInArg0: true,
11605                 asm:          x86.ACMOVWCC,
11606                 reg: regInfo{
11607                         inputs: []inputInfo{
11608                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11609                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11610                         },
11611                         outputs: []outputInfo{
11612                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11613                         },
11614                 },
11615         },
11616         {
11617                 name:         "CMOVWCS",
11618                 argLen:       3,
11619                 resultInArg0: true,
11620                 asm:          x86.ACMOVWCS,
11621                 reg: regInfo{
11622                         inputs: []inputInfo{
11623                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11624                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11625                         },
11626                         outputs: []outputInfo{
11627                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11628                         },
11629                 },
11630         },
11631         {
11632                 name:         "CMOVQEQF",
11633                 argLen:       3,
11634                 resultInArg0: true,
11635                 needIntTemp:  true,
11636                 asm:          x86.ACMOVQNE,
11637                 reg: regInfo{
11638                         inputs: []inputInfo{
11639                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11640                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11641                         },
11642                         outputs: []outputInfo{
11643                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11644                         },
11645                 },
11646         },
11647         {
11648                 name:         "CMOVQNEF",
11649                 argLen:       3,
11650                 resultInArg0: true,
11651                 asm:          x86.ACMOVQNE,
11652                 reg: regInfo{
11653                         inputs: []inputInfo{
11654                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11655                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11656                         },
11657                         outputs: []outputInfo{
11658                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11659                         },
11660                 },
11661         },
11662         {
11663                 name:         "CMOVQGTF",
11664                 argLen:       3,
11665                 resultInArg0: true,
11666                 asm:          x86.ACMOVQHI,
11667                 reg: regInfo{
11668                         inputs: []inputInfo{
11669                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11670                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11671                         },
11672                         outputs: []outputInfo{
11673                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11674                         },
11675                 },
11676         },
11677         {
11678                 name:         "CMOVQGEF",
11679                 argLen:       3,
11680                 resultInArg0: true,
11681                 asm:          x86.ACMOVQCC,
11682                 reg: regInfo{
11683                         inputs: []inputInfo{
11684                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11685                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11686                         },
11687                         outputs: []outputInfo{
11688                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11689                         },
11690                 },
11691         },
11692         {
11693                 name:         "CMOVLEQF",
11694                 argLen:       3,
11695                 resultInArg0: true,
11696                 needIntTemp:  true,
11697                 asm:          x86.ACMOVLNE,
11698                 reg: regInfo{
11699                         inputs: []inputInfo{
11700                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11701                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11702                         },
11703                         outputs: []outputInfo{
11704                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11705                         },
11706                 },
11707         },
11708         {
11709                 name:         "CMOVLNEF",
11710                 argLen:       3,
11711                 resultInArg0: true,
11712                 asm:          x86.ACMOVLNE,
11713                 reg: regInfo{
11714                         inputs: []inputInfo{
11715                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11716                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11717                         },
11718                         outputs: []outputInfo{
11719                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11720                         },
11721                 },
11722         },
11723         {
11724                 name:         "CMOVLGTF",
11725                 argLen:       3,
11726                 resultInArg0: true,
11727                 asm:          x86.ACMOVLHI,
11728                 reg: regInfo{
11729                         inputs: []inputInfo{
11730                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11731                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11732                         },
11733                         outputs: []outputInfo{
11734                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11735                         },
11736                 },
11737         },
11738         {
11739                 name:         "CMOVLGEF",
11740                 argLen:       3,
11741                 resultInArg0: true,
11742                 asm:          x86.ACMOVLCC,
11743                 reg: regInfo{
11744                         inputs: []inputInfo{
11745                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11746                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11747                         },
11748                         outputs: []outputInfo{
11749                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11750                         },
11751                 },
11752         },
11753         {
11754                 name:         "CMOVWEQF",
11755                 argLen:       3,
11756                 resultInArg0: true,
11757                 needIntTemp:  true,
11758                 asm:          x86.ACMOVWNE,
11759                 reg: regInfo{
11760                         inputs: []inputInfo{
11761                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11762                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11763                         },
11764                         outputs: []outputInfo{
11765                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11766                         },
11767                 },
11768         },
11769         {
11770                 name:         "CMOVWNEF",
11771                 argLen:       3,
11772                 resultInArg0: true,
11773                 asm:          x86.ACMOVWNE,
11774                 reg: regInfo{
11775                         inputs: []inputInfo{
11776                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11777                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11778                         },
11779                         outputs: []outputInfo{
11780                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11781                         },
11782                 },
11783         },
11784         {
11785                 name:         "CMOVWGTF",
11786                 argLen:       3,
11787                 resultInArg0: true,
11788                 asm:          x86.ACMOVWHI,
11789                 reg: regInfo{
11790                         inputs: []inputInfo{
11791                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11792                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11793                         },
11794                         outputs: []outputInfo{
11795                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11796                         },
11797                 },
11798         },
11799         {
11800                 name:         "CMOVWGEF",
11801                 argLen:       3,
11802                 resultInArg0: true,
11803                 asm:          x86.ACMOVWCC,
11804                 reg: regInfo{
11805                         inputs: []inputInfo{
11806                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11807                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11808                         },
11809                         outputs: []outputInfo{
11810                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11811                         },
11812                 },
11813         },
11814         {
11815                 name:         "BSWAPQ",
11816                 argLen:       1,
11817                 resultInArg0: true,
11818                 asm:          x86.ABSWAPQ,
11819                 reg: regInfo{
11820                         inputs: []inputInfo{
11821                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11822                         },
11823                         outputs: []outputInfo{
11824                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11825                         },
11826                 },
11827         },
11828         {
11829                 name:         "BSWAPL",
11830                 argLen:       1,
11831                 resultInArg0: true,
11832                 asm:          x86.ABSWAPL,
11833                 reg: regInfo{
11834                         inputs: []inputInfo{
11835                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11836                         },
11837                         outputs: []outputInfo{
11838                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11839                         },
11840                 },
11841         },
11842         {
11843                 name:         "POPCNTQ",
11844                 argLen:       1,
11845                 clobberFlags: true,
11846                 asm:          x86.APOPCNTQ,
11847                 reg: regInfo{
11848                         inputs: []inputInfo{
11849                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11850                         },
11851                         outputs: []outputInfo{
11852                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11853                         },
11854                 },
11855         },
11856         {
11857                 name:         "POPCNTL",
11858                 argLen:       1,
11859                 clobberFlags: true,
11860                 asm:          x86.APOPCNTL,
11861                 reg: regInfo{
11862                         inputs: []inputInfo{
11863                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11864                         },
11865                         outputs: []outputInfo{
11866                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11867                         },
11868                 },
11869         },
11870         {
11871                 name:   "SQRTSD",
11872                 argLen: 1,
11873                 asm:    x86.ASQRTSD,
11874                 reg: regInfo{
11875                         inputs: []inputInfo{
11876                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11877                         },
11878                         outputs: []outputInfo{
11879                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11880                         },
11881                 },
11882         },
11883         {
11884                 name:   "SQRTSS",
11885                 argLen: 1,
11886                 asm:    x86.ASQRTSS,
11887                 reg: regInfo{
11888                         inputs: []inputInfo{
11889                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11890                         },
11891                         outputs: []outputInfo{
11892                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11893                         },
11894                 },
11895         },
11896         {
11897                 name:    "ROUNDSD",
11898                 auxType: auxInt8,
11899                 argLen:  1,
11900                 asm:     x86.AROUNDSD,
11901                 reg: regInfo{
11902                         inputs: []inputInfo{
11903                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11904                         },
11905                         outputs: []outputInfo{
11906                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11907                         },
11908                 },
11909         },
11910         {
11911                 name:         "VFMADD231SD",
11912                 argLen:       3,
11913                 resultInArg0: true,
11914                 asm:          x86.AVFMADD231SD,
11915                 reg: regInfo{
11916                         inputs: []inputInfo{
11917                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11918                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11919                                 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11920                         },
11921                         outputs: []outputInfo{
11922                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11923                         },
11924                 },
11925         },
11926         {
11927                 name:         "MINSD",
11928                 argLen:       2,
11929                 resultInArg0: true,
11930                 asm:          x86.AMINSD,
11931                 reg: regInfo{
11932                         inputs: []inputInfo{
11933                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11934                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11935                         },
11936                         outputs: []outputInfo{
11937                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11938                         },
11939                 },
11940         },
11941         {
11942                 name:         "MINSS",
11943                 argLen:       2,
11944                 resultInArg0: true,
11945                 asm:          x86.AMINSS,
11946                 reg: regInfo{
11947                         inputs: []inputInfo{
11948                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11949                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11950                         },
11951                         outputs: []outputInfo{
11952                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11953                         },
11954                 },
11955         },
11956         {
11957                 name:   "SBBQcarrymask",
11958                 argLen: 1,
11959                 asm:    x86.ASBBQ,
11960                 reg: regInfo{
11961                         outputs: []outputInfo{
11962                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11963                         },
11964                 },
11965         },
11966         {
11967                 name:   "SBBLcarrymask",
11968                 argLen: 1,
11969                 asm:    x86.ASBBL,
11970                 reg: regInfo{
11971                         outputs: []outputInfo{
11972                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11973                         },
11974                 },
11975         },
11976         {
11977                 name:   "SETEQ",
11978                 argLen: 1,
11979                 asm:    x86.ASETEQ,
11980                 reg: regInfo{
11981                         outputs: []outputInfo{
11982                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11983                         },
11984                 },
11985         },
11986         {
11987                 name:   "SETNE",
11988                 argLen: 1,
11989                 asm:    x86.ASETNE,
11990                 reg: regInfo{
11991                         outputs: []outputInfo{
11992                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11993                         },
11994                 },
11995         },
11996         {
11997                 name:   "SETL",
11998                 argLen: 1,
11999                 asm:    x86.ASETLT,
12000                 reg: regInfo{
12001                         outputs: []outputInfo{
12002                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12003                         },
12004                 },
12005         },
12006         {
12007                 name:   "SETLE",
12008                 argLen: 1,
12009                 asm:    x86.ASETLE,
12010                 reg: regInfo{
12011                         outputs: []outputInfo{
12012                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12013                         },
12014                 },
12015         },
12016         {
12017                 name:   "SETG",
12018                 argLen: 1,
12019                 asm:    x86.ASETGT,
12020                 reg: regInfo{
12021                         outputs: []outputInfo{
12022                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12023                         },
12024                 },
12025         },
12026         {
12027                 name:   "SETGE",
12028                 argLen: 1,
12029                 asm:    x86.ASETGE,
12030                 reg: regInfo{
12031                         outputs: []outputInfo{
12032                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12033                         },
12034                 },
12035         },
12036         {
12037                 name:   "SETB",
12038                 argLen: 1,
12039                 asm:    x86.ASETCS,
12040                 reg: regInfo{
12041                         outputs: []outputInfo{
12042                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12043                         },
12044                 },
12045         },
12046         {
12047                 name:   "SETBE",
12048                 argLen: 1,
12049                 asm:    x86.ASETLS,
12050                 reg: regInfo{
12051                         outputs: []outputInfo{
12052                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12053                         },
12054                 },
12055         },
12056         {
12057                 name:   "SETA",
12058                 argLen: 1,
12059                 asm:    x86.ASETHI,
12060                 reg: regInfo{
12061                         outputs: []outputInfo{
12062                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12063                         },
12064                 },
12065         },
12066         {
12067                 name:   "SETAE",
12068                 argLen: 1,
12069                 asm:    x86.ASETCC,
12070                 reg: regInfo{
12071                         outputs: []outputInfo{
12072                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12073                         },
12074                 },
12075         },
12076         {
12077                 name:   "SETO",
12078                 argLen: 1,
12079                 asm:    x86.ASETOS,
12080                 reg: regInfo{
12081                         outputs: []outputInfo{
12082                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12083                         },
12084                 },
12085         },
12086         {
12087                 name:           "SETEQstore",
12088                 auxType:        auxSymOff,
12089                 argLen:         3,
12090                 faultOnNilArg0: true,
12091                 symEffect:      SymWrite,
12092                 asm:            x86.ASETEQ,
12093                 reg: regInfo{
12094                         inputs: []inputInfo{
12095                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12096                         },
12097                 },
12098         },
12099         {
12100                 name:           "SETNEstore",
12101                 auxType:        auxSymOff,
12102                 argLen:         3,
12103                 faultOnNilArg0: true,
12104                 symEffect:      SymWrite,
12105                 asm:            x86.ASETNE,
12106                 reg: regInfo{
12107                         inputs: []inputInfo{
12108                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12109                         },
12110                 },
12111         },
12112         {
12113                 name:           "SETLstore",
12114                 auxType:        auxSymOff,
12115                 argLen:         3,
12116                 faultOnNilArg0: true,
12117                 symEffect:      SymWrite,
12118                 asm:            x86.ASETLT,
12119                 reg: regInfo{
12120                         inputs: []inputInfo{
12121                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12122                         },
12123                 },
12124         },
12125         {
12126                 name:           "SETLEstore",
12127                 auxType:        auxSymOff,
12128                 argLen:         3,
12129                 faultOnNilArg0: true,
12130                 symEffect:      SymWrite,
12131                 asm:            x86.ASETLE,
12132                 reg: regInfo{
12133                         inputs: []inputInfo{
12134                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12135                         },
12136                 },
12137         },
12138         {
12139                 name:           "SETGstore",
12140                 auxType:        auxSymOff,
12141                 argLen:         3,
12142                 faultOnNilArg0: true,
12143                 symEffect:      SymWrite,
12144                 asm:            x86.ASETGT,
12145                 reg: regInfo{
12146                         inputs: []inputInfo{
12147                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12148                         },
12149                 },
12150         },
12151         {
12152                 name:           "SETGEstore",
12153                 auxType:        auxSymOff,
12154                 argLen:         3,
12155                 faultOnNilArg0: true,
12156                 symEffect:      SymWrite,
12157                 asm:            x86.ASETGE,
12158                 reg: regInfo{
12159                         inputs: []inputInfo{
12160                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12161                         },
12162                 },
12163         },
12164         {
12165                 name:           "SETBstore",
12166                 auxType:        auxSymOff,
12167                 argLen:         3,
12168                 faultOnNilArg0: true,
12169                 symEffect:      SymWrite,
12170                 asm:            x86.ASETCS,
12171                 reg: regInfo{
12172                         inputs: []inputInfo{
12173                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12174                         },
12175                 },
12176         },
12177         {
12178                 name:           "SETBEstore",
12179                 auxType:        auxSymOff,
12180                 argLen:         3,
12181                 faultOnNilArg0: true,
12182                 symEffect:      SymWrite,
12183                 asm:            x86.ASETLS,
12184                 reg: regInfo{
12185                         inputs: []inputInfo{
12186                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12187                         },
12188                 },
12189         },
12190         {
12191                 name:           "SETAstore",
12192                 auxType:        auxSymOff,
12193                 argLen:         3,
12194                 faultOnNilArg0: true,
12195                 symEffect:      SymWrite,
12196                 asm:            x86.ASETHI,
12197                 reg: regInfo{
12198                         inputs: []inputInfo{
12199                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12200                         },
12201                 },
12202         },
12203         {
12204                 name:           "SETAEstore",
12205                 auxType:        auxSymOff,
12206                 argLen:         3,
12207                 faultOnNilArg0: true,
12208                 symEffect:      SymWrite,
12209                 asm:            x86.ASETCC,
12210                 reg: regInfo{
12211                         inputs: []inputInfo{
12212                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12213                         },
12214                 },
12215         },
12216         {
12217                 name:        "SETEQstoreidx1",
12218                 auxType:     auxSymOff,
12219                 argLen:      4,
12220                 commutative: true,
12221                 symEffect:   SymWrite,
12222                 asm:         x86.ASETEQ,
12223                 scale:       1,
12224                 reg: regInfo{
12225                         inputs: []inputInfo{
12226                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12227                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12228                         },
12229                 },
12230         },
12231         {
12232                 name:        "SETNEstoreidx1",
12233                 auxType:     auxSymOff,
12234                 argLen:      4,
12235                 commutative: true,
12236                 symEffect:   SymWrite,
12237                 asm:         x86.ASETNE,
12238                 scale:       1,
12239                 reg: regInfo{
12240                         inputs: []inputInfo{
12241                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12242                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12243                         },
12244                 },
12245         },
12246         {
12247                 name:        "SETLstoreidx1",
12248                 auxType:     auxSymOff,
12249                 argLen:      4,
12250                 commutative: true,
12251                 symEffect:   SymWrite,
12252                 asm:         x86.ASETLT,
12253                 scale:       1,
12254                 reg: regInfo{
12255                         inputs: []inputInfo{
12256                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12257                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12258                         },
12259                 },
12260         },
12261         {
12262                 name:        "SETLEstoreidx1",
12263                 auxType:     auxSymOff,
12264                 argLen:      4,
12265                 commutative: true,
12266                 symEffect:   SymWrite,
12267                 asm:         x86.ASETLE,
12268                 scale:       1,
12269                 reg: regInfo{
12270                         inputs: []inputInfo{
12271                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12272                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12273                         },
12274                 },
12275         },
12276         {
12277                 name:        "SETGstoreidx1",
12278                 auxType:     auxSymOff,
12279                 argLen:      4,
12280                 commutative: true,
12281                 symEffect:   SymWrite,
12282                 asm:         x86.ASETGT,
12283                 scale:       1,
12284                 reg: regInfo{
12285                         inputs: []inputInfo{
12286                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12287                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12288                         },
12289                 },
12290         },
12291         {
12292                 name:        "SETGEstoreidx1",
12293                 auxType:     auxSymOff,
12294                 argLen:      4,
12295                 commutative: true,
12296                 symEffect:   SymWrite,
12297                 asm:         x86.ASETGE,
12298                 scale:       1,
12299                 reg: regInfo{
12300                         inputs: []inputInfo{
12301                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12302                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12303                         },
12304                 },
12305         },
12306         {
12307                 name:        "SETBstoreidx1",
12308                 auxType:     auxSymOff,
12309                 argLen:      4,
12310                 commutative: true,
12311                 symEffect:   SymWrite,
12312                 asm:         x86.ASETCS,
12313                 scale:       1,
12314                 reg: regInfo{
12315                         inputs: []inputInfo{
12316                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12317                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12318                         },
12319                 },
12320         },
12321         {
12322                 name:        "SETBEstoreidx1",
12323                 auxType:     auxSymOff,
12324                 argLen:      4,
12325                 commutative: true,
12326                 symEffect:   SymWrite,
12327                 asm:         x86.ASETLS,
12328                 scale:       1,
12329                 reg: regInfo{
12330                         inputs: []inputInfo{
12331                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12332                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12333                         },
12334                 },
12335         },
12336         {
12337                 name:        "SETAstoreidx1",
12338                 auxType:     auxSymOff,
12339                 argLen:      4,
12340                 commutative: true,
12341                 symEffect:   SymWrite,
12342                 asm:         x86.ASETHI,
12343                 scale:       1,
12344                 reg: regInfo{
12345                         inputs: []inputInfo{
12346                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12347                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12348                         },
12349                 },
12350         },
12351         {
12352                 name:        "SETAEstoreidx1",
12353                 auxType:     auxSymOff,
12354                 argLen:      4,
12355                 commutative: true,
12356                 symEffect:   SymWrite,
12357                 asm:         x86.ASETCC,
12358                 scale:       1,
12359                 reg: regInfo{
12360                         inputs: []inputInfo{
12361                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12362                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12363                         },
12364                 },
12365         },
12366         {
12367                 name:         "SETEQF",
12368                 argLen:       1,
12369                 clobberFlags: true,
12370                 needIntTemp:  true,
12371                 asm:          x86.ASETEQ,
12372                 reg: regInfo{
12373                         outputs: []outputInfo{
12374                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12375                         },
12376                 },
12377         },
12378         {
12379                 name:         "SETNEF",
12380                 argLen:       1,
12381                 clobberFlags: true,
12382                 needIntTemp:  true,
12383                 asm:          x86.ASETNE,
12384                 reg: regInfo{
12385                         outputs: []outputInfo{
12386                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12387                         },
12388                 },
12389         },
12390         {
12391                 name:   "SETORD",
12392                 argLen: 1,
12393                 asm:    x86.ASETPC,
12394                 reg: regInfo{
12395                         outputs: []outputInfo{
12396                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12397                         },
12398                 },
12399         },
12400         {
12401                 name:   "SETNAN",
12402                 argLen: 1,
12403                 asm:    x86.ASETPS,
12404                 reg: regInfo{
12405                         outputs: []outputInfo{
12406                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12407                         },
12408                 },
12409         },
12410         {
12411                 name:   "SETGF",
12412                 argLen: 1,
12413                 asm:    x86.ASETHI,
12414                 reg: regInfo{
12415                         outputs: []outputInfo{
12416                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12417                         },
12418                 },
12419         },
12420         {
12421                 name:   "SETGEF",
12422                 argLen: 1,
12423                 asm:    x86.ASETCC,
12424                 reg: regInfo{
12425                         outputs: []outputInfo{
12426                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12427                         },
12428                 },
12429         },
12430         {
12431                 name:   "MOVBQSX",
12432                 argLen: 1,
12433                 asm:    x86.AMOVBQSX,
12434                 reg: regInfo{
12435                         inputs: []inputInfo{
12436                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12437                         },
12438                         outputs: []outputInfo{
12439                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12440                         },
12441                 },
12442         },
12443         {
12444                 name:   "MOVBQZX",
12445                 argLen: 1,
12446                 asm:    x86.AMOVBLZX,
12447                 reg: regInfo{
12448                         inputs: []inputInfo{
12449                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12450                         },
12451                         outputs: []outputInfo{
12452                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12453                         },
12454                 },
12455         },
12456         {
12457                 name:   "MOVWQSX",
12458                 argLen: 1,
12459                 asm:    x86.AMOVWQSX,
12460                 reg: regInfo{
12461                         inputs: []inputInfo{
12462                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12463                         },
12464                         outputs: []outputInfo{
12465                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12466                         },
12467                 },
12468         },
12469         {
12470                 name:   "MOVWQZX",
12471                 argLen: 1,
12472                 asm:    x86.AMOVWLZX,
12473                 reg: regInfo{
12474                         inputs: []inputInfo{
12475                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12476                         },
12477                         outputs: []outputInfo{
12478                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12479                         },
12480                 },
12481         },
12482         {
12483                 name:   "MOVLQSX",
12484                 argLen: 1,
12485                 asm:    x86.AMOVLQSX,
12486                 reg: regInfo{
12487                         inputs: []inputInfo{
12488                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12489                         },
12490                         outputs: []outputInfo{
12491                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12492                         },
12493                 },
12494         },
12495         {
12496                 name:   "MOVLQZX",
12497                 argLen: 1,
12498                 asm:    x86.AMOVL,
12499                 reg: regInfo{
12500                         inputs: []inputInfo{
12501                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12502                         },
12503                         outputs: []outputInfo{
12504                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12505                         },
12506                 },
12507         },
12508         {
12509                 name:              "MOVLconst",
12510                 auxType:           auxInt32,
12511                 argLen:            0,
12512                 rematerializeable: true,
12513                 asm:               x86.AMOVL,
12514                 reg: regInfo{
12515                         outputs: []outputInfo{
12516                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12517                         },
12518                 },
12519         },
12520         {
12521                 name:              "MOVQconst",
12522                 auxType:           auxInt64,
12523                 argLen:            0,
12524                 rematerializeable: true,
12525                 asm:               x86.AMOVQ,
12526                 reg: regInfo{
12527                         outputs: []outputInfo{
12528                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12529                         },
12530                 },
12531         },
12532         {
12533                 name:   "CVTTSD2SL",
12534                 argLen: 1,
12535                 asm:    x86.ACVTTSD2SL,
12536                 reg: regInfo{
12537                         inputs: []inputInfo{
12538                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12539                         },
12540                         outputs: []outputInfo{
12541                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12542                         },
12543                 },
12544         },
12545         {
12546                 name:   "CVTTSD2SQ",
12547                 argLen: 1,
12548                 asm:    x86.ACVTTSD2SQ,
12549                 reg: regInfo{
12550                         inputs: []inputInfo{
12551                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12552                         },
12553                         outputs: []outputInfo{
12554                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12555                         },
12556                 },
12557         },
12558         {
12559                 name:   "CVTTSS2SL",
12560                 argLen: 1,
12561                 asm:    x86.ACVTTSS2SL,
12562                 reg: regInfo{
12563                         inputs: []inputInfo{
12564                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12565                         },
12566                         outputs: []outputInfo{
12567                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12568                         },
12569                 },
12570         },
12571         {
12572                 name:   "CVTTSS2SQ",
12573                 argLen: 1,
12574                 asm:    x86.ACVTTSS2SQ,
12575                 reg: regInfo{
12576                         inputs: []inputInfo{
12577                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12578                         },
12579                         outputs: []outputInfo{
12580                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12581                         },
12582                 },
12583         },
12584         {
12585                 name:   "CVTSL2SS",
12586                 argLen: 1,
12587                 asm:    x86.ACVTSL2SS,
12588                 reg: regInfo{
12589                         inputs: []inputInfo{
12590                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12591                         },
12592                         outputs: []outputInfo{
12593                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12594                         },
12595                 },
12596         },
12597         {
12598                 name:   "CVTSL2SD",
12599                 argLen: 1,
12600                 asm:    x86.ACVTSL2SD,
12601                 reg: regInfo{
12602                         inputs: []inputInfo{
12603                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12604                         },
12605                         outputs: []outputInfo{
12606                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12607                         },
12608                 },
12609         },
12610         {
12611                 name:   "CVTSQ2SS",
12612                 argLen: 1,
12613                 asm:    x86.ACVTSQ2SS,
12614                 reg: regInfo{
12615                         inputs: []inputInfo{
12616                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12617                         },
12618                         outputs: []outputInfo{
12619                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12620                         },
12621                 },
12622         },
12623         {
12624                 name:   "CVTSQ2SD",
12625                 argLen: 1,
12626                 asm:    x86.ACVTSQ2SD,
12627                 reg: regInfo{
12628                         inputs: []inputInfo{
12629                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12630                         },
12631                         outputs: []outputInfo{
12632                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12633                         },
12634                 },
12635         },
12636         {
12637                 name:   "CVTSD2SS",
12638                 argLen: 1,
12639                 asm:    x86.ACVTSD2SS,
12640                 reg: regInfo{
12641                         inputs: []inputInfo{
12642                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12643                         },
12644                         outputs: []outputInfo{
12645                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12646                         },
12647                 },
12648         },
12649         {
12650                 name:   "CVTSS2SD",
12651                 argLen: 1,
12652                 asm:    x86.ACVTSS2SD,
12653                 reg: regInfo{
12654                         inputs: []inputInfo{
12655                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12656                         },
12657                         outputs: []outputInfo{
12658                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12659                         },
12660                 },
12661         },
12662         {
12663                 name:   "MOVQi2f",
12664                 argLen: 1,
12665                 reg: regInfo{
12666                         inputs: []inputInfo{
12667                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12668                         },
12669                         outputs: []outputInfo{
12670                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12671                         },
12672                 },
12673         },
12674         {
12675                 name:   "MOVQf2i",
12676                 argLen: 1,
12677                 reg: regInfo{
12678                         inputs: []inputInfo{
12679                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12680                         },
12681                         outputs: []outputInfo{
12682                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12683                         },
12684                 },
12685         },
12686         {
12687                 name:   "MOVLi2f",
12688                 argLen: 1,
12689                 reg: regInfo{
12690                         inputs: []inputInfo{
12691                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12692                         },
12693                         outputs: []outputInfo{
12694                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12695                         },
12696                 },
12697         },
12698         {
12699                 name:   "MOVLf2i",
12700                 argLen: 1,
12701                 reg: regInfo{
12702                         inputs: []inputInfo{
12703                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12704                         },
12705                         outputs: []outputInfo{
12706                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12707                         },
12708                 },
12709         },
12710         {
12711                 name:         "PXOR",
12712                 argLen:       2,
12713                 commutative:  true,
12714                 resultInArg0: true,
12715                 asm:          x86.APXOR,
12716                 reg: regInfo{
12717                         inputs: []inputInfo{
12718                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12719                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12720                         },
12721                         outputs: []outputInfo{
12722                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12723                         },
12724                 },
12725         },
12726         {
12727                 name:         "POR",
12728                 argLen:       2,
12729                 commutative:  true,
12730                 resultInArg0: true,
12731                 asm:          x86.APOR,
12732                 reg: regInfo{
12733                         inputs: []inputInfo{
12734                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12735                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12736                         },
12737                         outputs: []outputInfo{
12738                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12739                         },
12740                 },
12741         },
12742         {
12743                 name:              "LEAQ",
12744                 auxType:           auxSymOff,
12745                 argLen:            1,
12746                 rematerializeable: true,
12747                 symEffect:         SymAddr,
12748                 asm:               x86.ALEAQ,
12749                 reg: regInfo{
12750                         inputs: []inputInfo{
12751                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12752                         },
12753                         outputs: []outputInfo{
12754                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12755                         },
12756                 },
12757         },
12758         {
12759                 name:              "LEAL",
12760                 auxType:           auxSymOff,
12761                 argLen:            1,
12762                 rematerializeable: true,
12763                 symEffect:         SymAddr,
12764                 asm:               x86.ALEAL,
12765                 reg: regInfo{
12766                         inputs: []inputInfo{
12767                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12768                         },
12769                         outputs: []outputInfo{
12770                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12771                         },
12772                 },
12773         },
12774         {
12775                 name:              "LEAW",
12776                 auxType:           auxSymOff,
12777                 argLen:            1,
12778                 rematerializeable: true,
12779                 symEffect:         SymAddr,
12780                 asm:               x86.ALEAW,
12781                 reg: regInfo{
12782                         inputs: []inputInfo{
12783                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12784                         },
12785                         outputs: []outputInfo{
12786                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12787                         },
12788                 },
12789         },
12790         {
12791                 name:        "LEAQ1",
12792                 auxType:     auxSymOff,
12793                 argLen:      2,
12794                 commutative: true,
12795                 symEffect:   SymAddr,
12796                 asm:         x86.ALEAQ,
12797                 scale:       1,
12798                 reg: regInfo{
12799                         inputs: []inputInfo{
12800                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12801                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12802                         },
12803                         outputs: []outputInfo{
12804                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12805                         },
12806                 },
12807         },
12808         {
12809                 name:        "LEAL1",
12810                 auxType:     auxSymOff,
12811                 argLen:      2,
12812                 commutative: true,
12813                 symEffect:   SymAddr,
12814                 asm:         x86.ALEAL,
12815                 scale:       1,
12816                 reg: regInfo{
12817                         inputs: []inputInfo{
12818                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12819                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12820                         },
12821                         outputs: []outputInfo{
12822                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12823                         },
12824                 },
12825         },
12826         {
12827                 name:        "LEAW1",
12828                 auxType:     auxSymOff,
12829                 argLen:      2,
12830                 commutative: true,
12831                 symEffect:   SymAddr,
12832                 asm:         x86.ALEAW,
12833                 scale:       1,
12834                 reg: regInfo{
12835                         inputs: []inputInfo{
12836                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12837                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12838                         },
12839                         outputs: []outputInfo{
12840                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12841                         },
12842                 },
12843         },
12844         {
12845                 name:      "LEAQ2",
12846                 auxType:   auxSymOff,
12847                 argLen:    2,
12848                 symEffect: SymAddr,
12849                 asm:       x86.ALEAQ,
12850                 scale:     2,
12851                 reg: regInfo{
12852                         inputs: []inputInfo{
12853                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12854                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12855                         },
12856                         outputs: []outputInfo{
12857                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12858                         },
12859                 },
12860         },
12861         {
12862                 name:      "LEAL2",
12863                 auxType:   auxSymOff,
12864                 argLen:    2,
12865                 symEffect: SymAddr,
12866                 asm:       x86.ALEAL,
12867                 scale:     2,
12868                 reg: regInfo{
12869                         inputs: []inputInfo{
12870                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12871                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12872                         },
12873                         outputs: []outputInfo{
12874                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12875                         },
12876                 },
12877         },
12878         {
12879                 name:      "LEAW2",
12880                 auxType:   auxSymOff,
12881                 argLen:    2,
12882                 symEffect: SymAddr,
12883                 asm:       x86.ALEAW,
12884                 scale:     2,
12885                 reg: regInfo{
12886                         inputs: []inputInfo{
12887                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12888                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12889                         },
12890                         outputs: []outputInfo{
12891                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12892                         },
12893                 },
12894         },
12895         {
12896                 name:      "LEAQ4",
12897                 auxType:   auxSymOff,
12898                 argLen:    2,
12899                 symEffect: SymAddr,
12900                 asm:       x86.ALEAQ,
12901                 scale:     4,
12902                 reg: regInfo{
12903                         inputs: []inputInfo{
12904                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12905                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12906                         },
12907                         outputs: []outputInfo{
12908                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12909                         },
12910                 },
12911         },
12912         {
12913                 name:      "LEAL4",
12914                 auxType:   auxSymOff,
12915                 argLen:    2,
12916                 symEffect: SymAddr,
12917                 asm:       x86.ALEAL,
12918                 scale:     4,
12919                 reg: regInfo{
12920                         inputs: []inputInfo{
12921                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12922                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12923                         },
12924                         outputs: []outputInfo{
12925                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12926                         },
12927                 },
12928         },
12929         {
12930                 name:      "LEAW4",
12931                 auxType:   auxSymOff,
12932                 argLen:    2,
12933                 symEffect: SymAddr,
12934                 asm:       x86.ALEAW,
12935                 scale:     4,
12936                 reg: regInfo{
12937                         inputs: []inputInfo{
12938                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12939                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12940                         },
12941                         outputs: []outputInfo{
12942                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12943                         },
12944                 },
12945         },
12946         {
12947                 name:      "LEAQ8",
12948                 auxType:   auxSymOff,
12949                 argLen:    2,
12950                 symEffect: SymAddr,
12951                 asm:       x86.ALEAQ,
12952                 scale:     8,
12953                 reg: regInfo{
12954                         inputs: []inputInfo{
12955                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12956                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12957                         },
12958                         outputs: []outputInfo{
12959                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12960                         },
12961                 },
12962         },
12963         {
12964                 name:      "LEAL8",
12965                 auxType:   auxSymOff,
12966                 argLen:    2,
12967                 symEffect: SymAddr,
12968                 asm:       x86.ALEAL,
12969                 scale:     8,
12970                 reg: regInfo{
12971                         inputs: []inputInfo{
12972                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12973                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12974                         },
12975                         outputs: []outputInfo{
12976                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12977                         },
12978                 },
12979         },
12980         {
12981                 name:      "LEAW8",
12982                 auxType:   auxSymOff,
12983                 argLen:    2,
12984                 symEffect: SymAddr,
12985                 asm:       x86.ALEAW,
12986                 scale:     8,
12987                 reg: regInfo{
12988                         inputs: []inputInfo{
12989                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12990                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12991                         },
12992                         outputs: []outputInfo{
12993                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12994                         },
12995                 },
12996         },
12997         {
12998                 name:           "MOVBload",
12999                 auxType:        auxSymOff,
13000                 argLen:         2,
13001                 faultOnNilArg0: true,
13002                 symEffect:      SymRead,
13003                 asm:            x86.AMOVBLZX,
13004                 reg: regInfo{
13005                         inputs: []inputInfo{
13006                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13007                         },
13008                         outputs: []outputInfo{
13009                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13010                         },
13011                 },
13012         },
13013         {
13014                 name:           "MOVBQSXload",
13015                 auxType:        auxSymOff,
13016                 argLen:         2,
13017                 faultOnNilArg0: true,
13018                 symEffect:      SymRead,
13019                 asm:            x86.AMOVBQSX,
13020                 reg: regInfo{
13021                         inputs: []inputInfo{
13022                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13023                         },
13024                         outputs: []outputInfo{
13025                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13026                         },
13027                 },
13028         },
13029         {
13030                 name:           "MOVWload",
13031                 auxType:        auxSymOff,
13032                 argLen:         2,
13033                 faultOnNilArg0: true,
13034                 symEffect:      SymRead,
13035                 asm:            x86.AMOVWLZX,
13036                 reg: regInfo{
13037                         inputs: []inputInfo{
13038                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13039                         },
13040                         outputs: []outputInfo{
13041                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13042                         },
13043                 },
13044         },
13045         {
13046                 name:           "MOVWQSXload",
13047                 auxType:        auxSymOff,
13048                 argLen:         2,
13049                 faultOnNilArg0: true,
13050                 symEffect:      SymRead,
13051                 asm:            x86.AMOVWQSX,
13052                 reg: regInfo{
13053                         inputs: []inputInfo{
13054                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13055                         },
13056                         outputs: []outputInfo{
13057                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13058                         },
13059                 },
13060         },
13061         {
13062                 name:           "MOVLload",
13063                 auxType:        auxSymOff,
13064                 argLen:         2,
13065                 faultOnNilArg0: true,
13066                 symEffect:      SymRead,
13067                 asm:            x86.AMOVL,
13068                 reg: regInfo{
13069                         inputs: []inputInfo{
13070                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13071                         },
13072                         outputs: []outputInfo{
13073                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13074                         },
13075                 },
13076         },
13077         {
13078                 name:           "MOVLQSXload",
13079                 auxType:        auxSymOff,
13080                 argLen:         2,
13081                 faultOnNilArg0: true,
13082                 symEffect:      SymRead,
13083                 asm:            x86.AMOVLQSX,
13084                 reg: regInfo{
13085                         inputs: []inputInfo{
13086                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13087                         },
13088                         outputs: []outputInfo{
13089                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13090                         },
13091                 },
13092         },
13093         {
13094                 name:           "MOVQload",
13095                 auxType:        auxSymOff,
13096                 argLen:         2,
13097                 faultOnNilArg0: true,
13098                 symEffect:      SymRead,
13099                 asm:            x86.AMOVQ,
13100                 reg: regInfo{
13101                         inputs: []inputInfo{
13102                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13103                         },
13104                         outputs: []outputInfo{
13105                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13106                         },
13107                 },
13108         },
13109         {
13110                 name:           "MOVBstore",
13111                 auxType:        auxSymOff,
13112                 argLen:         3,
13113                 faultOnNilArg0: true,
13114                 symEffect:      SymWrite,
13115                 asm:            x86.AMOVB,
13116                 reg: regInfo{
13117                         inputs: []inputInfo{
13118                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13119                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13120                         },
13121                 },
13122         },
13123         {
13124                 name:           "MOVWstore",
13125                 auxType:        auxSymOff,
13126                 argLen:         3,
13127                 faultOnNilArg0: true,
13128                 symEffect:      SymWrite,
13129                 asm:            x86.AMOVW,
13130                 reg: regInfo{
13131                         inputs: []inputInfo{
13132                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13133                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13134                         },
13135                 },
13136         },
13137         {
13138                 name:           "MOVLstore",
13139                 auxType:        auxSymOff,
13140                 argLen:         3,
13141                 faultOnNilArg0: true,
13142                 symEffect:      SymWrite,
13143                 asm:            x86.AMOVL,
13144                 reg: regInfo{
13145                         inputs: []inputInfo{
13146                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13147                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13148                         },
13149                 },
13150         },
13151         {
13152                 name:           "MOVQstore",
13153                 auxType:        auxSymOff,
13154                 argLen:         3,
13155                 faultOnNilArg0: true,
13156                 symEffect:      SymWrite,
13157                 asm:            x86.AMOVQ,
13158                 reg: regInfo{
13159                         inputs: []inputInfo{
13160                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13161                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13162                         },
13163                 },
13164         },
13165         {
13166                 name:           "MOVOload",
13167                 auxType:        auxSymOff,
13168                 argLen:         2,
13169                 faultOnNilArg0: true,
13170                 symEffect:      SymRead,
13171                 asm:            x86.AMOVUPS,
13172                 reg: regInfo{
13173                         inputs: []inputInfo{
13174                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
13175                         },
13176                         outputs: []outputInfo{
13177                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13178                         },
13179                 },
13180         },
13181         {
13182                 name:           "MOVOstore",
13183                 auxType:        auxSymOff,
13184                 argLen:         3,
13185                 faultOnNilArg0: true,
13186                 symEffect:      SymWrite,
13187                 asm:            x86.AMOVUPS,
13188                 reg: regInfo{
13189                         inputs: []inputInfo{
13190                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13191                                 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
13192                         },
13193                 },
13194         },
13195         {
13196                 name:        "MOVBloadidx1",
13197                 auxType:     auxSymOff,
13198                 argLen:      3,
13199                 commutative: true,
13200                 symEffect:   SymRead,
13201                 asm:         x86.AMOVBLZX,
13202                 scale:       1,
13203                 reg: regInfo{
13204                         inputs: []inputInfo{
13205                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13206                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13207                         },
13208                         outputs: []outputInfo{
13209                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13210                         },
13211                 },
13212         },
13213         {
13214                 name:        "MOVWloadidx1",
13215                 auxType:     auxSymOff,
13216                 argLen:      3,
13217                 commutative: true,
13218                 symEffect:   SymRead,
13219                 asm:         x86.AMOVWLZX,
13220                 scale:       1,
13221                 reg: regInfo{
13222                         inputs: []inputInfo{
13223                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13224                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13225                         },
13226                         outputs: []outputInfo{
13227                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13228                         },
13229                 },
13230         },
13231         {
13232                 name:      "MOVWloadidx2",
13233                 auxType:   auxSymOff,
13234                 argLen:    3,
13235                 symEffect: SymRead,
13236                 asm:       x86.AMOVWLZX,
13237                 scale:     2,
13238                 reg: regInfo{
13239                         inputs: []inputInfo{
13240                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13241                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13242                         },
13243                         outputs: []outputInfo{
13244                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13245                         },
13246                 },
13247         },
13248         {
13249                 name:        "MOVLloadidx1",
13250                 auxType:     auxSymOff,
13251                 argLen:      3,
13252                 commutative: true,
13253                 symEffect:   SymRead,
13254                 asm:         x86.AMOVL,
13255                 scale:       1,
13256                 reg: regInfo{
13257                         inputs: []inputInfo{
13258                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13259                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13260                         },
13261                         outputs: []outputInfo{
13262                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13263                         },
13264                 },
13265         },
13266         {
13267                 name:      "MOVLloadidx4",
13268                 auxType:   auxSymOff,
13269                 argLen:    3,
13270                 symEffect: SymRead,
13271                 asm:       x86.AMOVL,
13272                 scale:     4,
13273                 reg: regInfo{
13274                         inputs: []inputInfo{
13275                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13276                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13277                         },
13278                         outputs: []outputInfo{
13279                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13280                         },
13281                 },
13282         },
13283         {
13284                 name:      "MOVLloadidx8",
13285                 auxType:   auxSymOff,
13286                 argLen:    3,
13287                 symEffect: SymRead,
13288                 asm:       x86.AMOVL,
13289                 scale:     8,
13290                 reg: regInfo{
13291                         inputs: []inputInfo{
13292                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13293                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13294                         },
13295                         outputs: []outputInfo{
13296                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13297                         },
13298                 },
13299         },
13300         {
13301                 name:        "MOVQloadidx1",
13302                 auxType:     auxSymOff,
13303                 argLen:      3,
13304                 commutative: true,
13305                 symEffect:   SymRead,
13306                 asm:         x86.AMOVQ,
13307                 scale:       1,
13308                 reg: regInfo{
13309                         inputs: []inputInfo{
13310                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13311                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13312                         },
13313                         outputs: []outputInfo{
13314                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13315                         },
13316                 },
13317         },
13318         {
13319                 name:      "MOVQloadidx8",
13320                 auxType:   auxSymOff,
13321                 argLen:    3,
13322                 symEffect: SymRead,
13323                 asm:       x86.AMOVQ,
13324                 scale:     8,
13325                 reg: regInfo{
13326                         inputs: []inputInfo{
13327                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13328                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13329                         },
13330                         outputs: []outputInfo{
13331                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13332                         },
13333                 },
13334         },
13335         {
13336                 name:        "MOVBstoreidx1",
13337                 auxType:     auxSymOff,
13338                 argLen:      4,
13339                 commutative: true,
13340                 symEffect:   SymWrite,
13341                 asm:         x86.AMOVB,
13342                 scale:       1,
13343                 reg: regInfo{
13344                         inputs: []inputInfo{
13345                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13346                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13347                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13348                         },
13349                 },
13350         },
13351         {
13352                 name:        "MOVWstoreidx1",
13353                 auxType:     auxSymOff,
13354                 argLen:      4,
13355                 commutative: true,
13356                 symEffect:   SymWrite,
13357                 asm:         x86.AMOVW,
13358                 scale:       1,
13359                 reg: regInfo{
13360                         inputs: []inputInfo{
13361                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13362                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13363                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13364                         },
13365                 },
13366         },
13367         {
13368                 name:      "MOVWstoreidx2",
13369                 auxType:   auxSymOff,
13370                 argLen:    4,
13371                 symEffect: SymWrite,
13372                 asm:       x86.AMOVW,
13373                 scale:     2,
13374                 reg: regInfo{
13375                         inputs: []inputInfo{
13376                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13377                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13378                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13379                         },
13380                 },
13381         },
13382         {
13383                 name:        "MOVLstoreidx1",
13384                 auxType:     auxSymOff,
13385                 argLen:      4,
13386                 commutative: true,
13387                 symEffect:   SymWrite,
13388                 asm:         x86.AMOVL,
13389                 scale:       1,
13390                 reg: regInfo{
13391                         inputs: []inputInfo{
13392                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13393                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13394                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13395                         },
13396                 },
13397         },
13398         {
13399                 name:      "MOVLstoreidx4",
13400                 auxType:   auxSymOff,
13401                 argLen:    4,
13402                 symEffect: SymWrite,
13403                 asm:       x86.AMOVL,
13404                 scale:     4,
13405                 reg: regInfo{
13406                         inputs: []inputInfo{
13407                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13408                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13409                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13410                         },
13411                 },
13412         },
13413         {
13414                 name:      "MOVLstoreidx8",
13415                 auxType:   auxSymOff,
13416                 argLen:    4,
13417                 symEffect: SymWrite,
13418                 asm:       x86.AMOVL,
13419                 scale:     8,
13420                 reg: regInfo{
13421                         inputs: []inputInfo{
13422                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13423                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13424                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13425                         },
13426                 },
13427         },
13428         {
13429                 name:        "MOVQstoreidx1",
13430                 auxType:     auxSymOff,
13431                 argLen:      4,
13432                 commutative: true,
13433                 symEffect:   SymWrite,
13434                 asm:         x86.AMOVQ,
13435                 scale:       1,
13436                 reg: regInfo{
13437                         inputs: []inputInfo{
13438                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13439                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13440                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13441                         },
13442                 },
13443         },
13444         {
13445                 name:      "MOVQstoreidx8",
13446                 auxType:   auxSymOff,
13447                 argLen:    4,
13448                 symEffect: SymWrite,
13449                 asm:       x86.AMOVQ,
13450                 scale:     8,
13451                 reg: regInfo{
13452                         inputs: []inputInfo{
13453                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13454                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13455                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13456                         },
13457                 },
13458         },
13459         {
13460                 name:           "MOVBstoreconst",
13461                 auxType:        auxSymValAndOff,
13462                 argLen:         2,
13463                 faultOnNilArg0: true,
13464                 symEffect:      SymWrite,
13465                 asm:            x86.AMOVB,
13466                 reg: regInfo{
13467                         inputs: []inputInfo{
13468                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13469                         },
13470                 },
13471         },
13472         {
13473                 name:           "MOVWstoreconst",
13474                 auxType:        auxSymValAndOff,
13475                 argLen:         2,
13476                 faultOnNilArg0: true,
13477                 symEffect:      SymWrite,
13478                 asm:            x86.AMOVW,
13479                 reg: regInfo{
13480                         inputs: []inputInfo{
13481                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13482                         },
13483                 },
13484         },
13485         {
13486                 name:           "MOVLstoreconst",
13487                 auxType:        auxSymValAndOff,
13488                 argLen:         2,
13489                 faultOnNilArg0: true,
13490                 symEffect:      SymWrite,
13491                 asm:            x86.AMOVL,
13492                 reg: regInfo{
13493                         inputs: []inputInfo{
13494                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13495                         },
13496                 },
13497         },
13498         {
13499                 name:           "MOVQstoreconst",
13500                 auxType:        auxSymValAndOff,
13501                 argLen:         2,
13502                 faultOnNilArg0: true,
13503                 symEffect:      SymWrite,
13504                 asm:            x86.AMOVQ,
13505                 reg: regInfo{
13506                         inputs: []inputInfo{
13507                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13508                         },
13509                 },
13510         },
13511         {
13512                 name:           "MOVOstoreconst",
13513                 auxType:        auxSymValAndOff,
13514                 argLen:         2,
13515                 faultOnNilArg0: true,
13516                 symEffect:      SymWrite,
13517                 asm:            x86.AMOVUPS,
13518                 reg: regInfo{
13519                         inputs: []inputInfo{
13520                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13521                         },
13522                 },
13523         },
13524         {
13525                 name:        "MOVBstoreconstidx1",
13526                 auxType:     auxSymValAndOff,
13527                 argLen:      3,
13528                 commutative: true,
13529                 symEffect:   SymWrite,
13530                 asm:         x86.AMOVB,
13531                 scale:       1,
13532                 reg: regInfo{
13533                         inputs: []inputInfo{
13534                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13535                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13536                         },
13537                 },
13538         },
13539         {
13540                 name:        "MOVWstoreconstidx1",
13541                 auxType:     auxSymValAndOff,
13542                 argLen:      3,
13543                 commutative: true,
13544                 symEffect:   SymWrite,
13545                 asm:         x86.AMOVW,
13546                 scale:       1,
13547                 reg: regInfo{
13548                         inputs: []inputInfo{
13549                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13550                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13551                         },
13552                 },
13553         },
13554         {
13555                 name:      "MOVWstoreconstidx2",
13556                 auxType:   auxSymValAndOff,
13557                 argLen:    3,
13558                 symEffect: SymWrite,
13559                 asm:       x86.AMOVW,
13560                 scale:     2,
13561                 reg: regInfo{
13562                         inputs: []inputInfo{
13563                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13564                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13565                         },
13566                 },
13567         },
13568         {
13569                 name:        "MOVLstoreconstidx1",
13570                 auxType:     auxSymValAndOff,
13571                 argLen:      3,
13572                 commutative: true,
13573                 symEffect:   SymWrite,
13574                 asm:         x86.AMOVL,
13575                 scale:       1,
13576                 reg: regInfo{
13577                         inputs: []inputInfo{
13578                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13579                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13580                         },
13581                 },
13582         },
13583         {
13584                 name:      "MOVLstoreconstidx4",
13585                 auxType:   auxSymValAndOff,
13586                 argLen:    3,
13587                 symEffect: SymWrite,
13588                 asm:       x86.AMOVL,
13589                 scale:     4,
13590                 reg: regInfo{
13591                         inputs: []inputInfo{
13592                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13593                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13594                         },
13595                 },
13596         },
13597         {
13598                 name:        "MOVQstoreconstidx1",
13599                 auxType:     auxSymValAndOff,
13600                 argLen:      3,
13601                 commutative: true,
13602                 symEffect:   SymWrite,
13603                 asm:         x86.AMOVQ,
13604                 scale:       1,
13605                 reg: regInfo{
13606                         inputs: []inputInfo{
13607                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13608                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13609                         },
13610                 },
13611         },
13612         {
13613                 name:      "MOVQstoreconstidx8",
13614                 auxType:   auxSymValAndOff,
13615                 argLen:    3,
13616                 symEffect: SymWrite,
13617                 asm:       x86.AMOVQ,
13618                 scale:     8,
13619                 reg: regInfo{
13620                         inputs: []inputInfo{
13621                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13622                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13623                         },
13624                 },
13625         },
13626         {
13627                 name:           "DUFFZERO",
13628                 auxType:        auxInt64,
13629                 argLen:         2,
13630                 faultOnNilArg0: true,
13631                 unsafePoint:    true,
13632                 reg: regInfo{
13633                         inputs: []inputInfo{
13634                                 {0, 128}, // DI
13635                         },
13636                         clobbers: 128, // DI
13637                 },
13638         },
13639         {
13640                 name:           "REPSTOSQ",
13641                 argLen:         4,
13642                 faultOnNilArg0: true,
13643                 reg: regInfo{
13644                         inputs: []inputInfo{
13645                                 {0, 128}, // DI
13646                                 {1, 2},   // CX
13647                                 {2, 1},   // AX
13648                         },
13649                         clobbers: 130, // CX DI
13650                 },
13651         },
13652         {
13653                 name:         "CALLstatic",
13654                 auxType:      auxCallOff,
13655                 argLen:       -1,
13656                 clobberFlags: true,
13657                 call:         true,
13658                 reg: regInfo{
13659                         clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13660                 },
13661         },
13662         {
13663                 name:         "CALLtail",
13664                 auxType:      auxCallOff,
13665                 argLen:       -1,
13666                 clobberFlags: true,
13667                 call:         true,
13668                 tailCall:     true,
13669                 reg: regInfo{
13670                         clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13671                 },
13672         },
13673         {
13674                 name:         "CALLclosure",
13675                 auxType:      auxCallOff,
13676                 argLen:       -1,
13677                 clobberFlags: true,
13678                 call:         true,
13679                 reg: regInfo{
13680                         inputs: []inputInfo{
13681                                 {1, 4},     // DX
13682                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13683                         },
13684                         clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13685                 },
13686         },
13687         {
13688                 name:         "CALLinter",
13689                 auxType:      auxCallOff,
13690                 argLen:       -1,
13691                 clobberFlags: true,
13692                 call:         true,
13693                 reg: regInfo{
13694                         inputs: []inputInfo{
13695                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13696                         },
13697                         clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13698                 },
13699         },
13700         {
13701                 name:           "DUFFCOPY",
13702                 auxType:        auxInt64,
13703                 argLen:         3,
13704                 clobberFlags:   true,
13705                 faultOnNilArg0: true,
13706                 faultOnNilArg1: true,
13707                 unsafePoint:    true,
13708                 reg: regInfo{
13709                         inputs: []inputInfo{
13710                                 {0, 128}, // DI
13711                                 {1, 64},  // SI
13712                         },
13713                         clobbers: 65728, // SI DI X0
13714                 },
13715         },
13716         {
13717                 name:           "REPMOVSQ",
13718                 argLen:         4,
13719                 faultOnNilArg0: true,
13720                 faultOnNilArg1: true,
13721                 reg: regInfo{
13722                         inputs: []inputInfo{
13723                                 {0, 128}, // DI
13724                                 {1, 64},  // SI
13725                                 {2, 2},   // CX
13726                         },
13727                         clobbers: 194, // CX SI DI
13728                 },
13729         },
13730         {
13731                 name:   "InvertFlags",
13732                 argLen: 1,
13733                 reg:    regInfo{},
13734         },
13735         {
13736                 name:   "LoweredGetG",
13737                 argLen: 1,
13738                 reg: regInfo{
13739                         outputs: []outputInfo{
13740                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13741                         },
13742                 },
13743         },
13744         {
13745                 name:      "LoweredGetClosurePtr",
13746                 argLen:    0,
13747                 zeroWidth: true,
13748                 reg: regInfo{
13749                         outputs: []outputInfo{
13750                                 {0, 4}, // DX
13751                         },
13752                 },
13753         },
13754         {
13755                 name:              "LoweredGetCallerPC",
13756                 argLen:            0,
13757                 rematerializeable: true,
13758                 reg: regInfo{
13759                         outputs: []outputInfo{
13760                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13761                         },
13762                 },
13763         },
13764         {
13765                 name:              "LoweredGetCallerSP",
13766                 argLen:            1,
13767                 rematerializeable: true,
13768                 reg: regInfo{
13769                         outputs: []outputInfo{
13770                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13771                         },
13772                 },
13773         },
13774         {
13775                 name:           "LoweredNilCheck",
13776                 argLen:         2,
13777                 clobberFlags:   true,
13778                 nilCheck:       true,
13779                 faultOnNilArg0: true,
13780                 reg: regInfo{
13781                         inputs: []inputInfo{
13782                                 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13783                         },
13784                 },
13785         },
13786         {
13787                 name:         "LoweredWB",
13788                 auxType:      auxInt64,
13789                 argLen:       1,
13790                 clobberFlags: true,
13791                 reg: regInfo{
13792                         clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13793                         outputs: []outputInfo{
13794                                 {0, 2048}, // R11
13795                         },
13796                 },
13797         },
13798         {
13799                 name:              "LoweredHasCPUFeature",
13800                 auxType:           auxSym,
13801                 argLen:            0,
13802                 rematerializeable: true,
13803                 symEffect:         SymNone,
13804                 reg: regInfo{
13805                         outputs: []outputInfo{
13806                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13807                         },
13808                 },
13809         },
13810         {
13811                 name:    "LoweredPanicBoundsA",
13812                 auxType: auxInt64,
13813                 argLen:  3,
13814                 call:    true,
13815                 reg: regInfo{
13816                         inputs: []inputInfo{
13817                                 {0, 4}, // DX
13818                                 {1, 8}, // BX
13819                         },
13820                 },
13821         },
13822         {
13823                 name:    "LoweredPanicBoundsB",
13824                 auxType: auxInt64,
13825                 argLen:  3,
13826                 call:    true,
13827                 reg: regInfo{
13828                         inputs: []inputInfo{
13829                                 {0, 2}, // CX
13830                                 {1, 4}, // DX
13831                         },
13832                 },
13833         },
13834         {
13835                 name:    "LoweredPanicBoundsC",
13836                 auxType: auxInt64,
13837                 argLen:  3,
13838                 call:    true,
13839                 reg: regInfo{
13840                         inputs: []inputInfo{
13841                                 {0, 1}, // AX
13842                                 {1, 2}, // CX
13843                         },
13844                 },
13845         },
13846         {
13847                 name:   "FlagEQ",
13848                 argLen: 0,
13849                 reg:    regInfo{},
13850         },
13851         {
13852                 name:   "FlagLT_ULT",
13853                 argLen: 0,
13854                 reg:    regInfo{},
13855         },
13856         {
13857                 name:   "FlagLT_UGT",
13858                 argLen: 0,
13859                 reg:    regInfo{},
13860         },
13861         {
13862                 name:   "FlagGT_UGT",
13863                 argLen: 0,
13864                 reg:    regInfo{},
13865         },
13866         {
13867                 name:   "FlagGT_ULT",
13868                 argLen: 0,
13869                 reg:    regInfo{},
13870         },
13871         {
13872                 name:           "MOVBatomicload",
13873                 auxType:        auxSymOff,
13874                 argLen:         2,
13875                 faultOnNilArg0: true,
13876                 symEffect:      SymRead,
13877                 asm:            x86.AMOVB,
13878                 reg: regInfo{
13879                         inputs: []inputInfo{
13880                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13881                         },
13882                         outputs: []outputInfo{
13883                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13884                         },
13885                 },
13886         },
13887         {
13888                 name:           "MOVLatomicload",
13889                 auxType:        auxSymOff,
13890                 argLen:         2,
13891                 faultOnNilArg0: true,
13892                 symEffect:      SymRead,
13893                 asm:            x86.AMOVL,
13894                 reg: regInfo{
13895                         inputs: []inputInfo{
13896                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13897                         },
13898                         outputs: []outputInfo{
13899                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13900                         },
13901                 },
13902         },
13903         {
13904                 name:           "MOVQatomicload",
13905                 auxType:        auxSymOff,
13906                 argLen:         2,
13907                 faultOnNilArg0: true,
13908                 symEffect:      SymRead,
13909                 asm:            x86.AMOVQ,
13910                 reg: regInfo{
13911                         inputs: []inputInfo{
13912                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13913                         },
13914                         outputs: []outputInfo{
13915                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13916                         },
13917                 },
13918         },
13919         {
13920                 name:           "XCHGB",
13921                 auxType:        auxSymOff,
13922                 argLen:         3,
13923                 resultInArg0:   true,
13924                 faultOnNilArg1: true,
13925                 hasSideEffects: true,
13926                 symEffect:      SymRdWr,
13927                 asm:            x86.AXCHGB,
13928                 reg: regInfo{
13929                         inputs: []inputInfo{
13930                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13931                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13932                         },
13933                         outputs: []outputInfo{
13934                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13935                         },
13936                 },
13937         },
13938         {
13939                 name:           "XCHGL",
13940                 auxType:        auxSymOff,
13941                 argLen:         3,
13942                 resultInArg0:   true,
13943                 faultOnNilArg1: true,
13944                 hasSideEffects: true,
13945                 symEffect:      SymRdWr,
13946                 asm:            x86.AXCHGL,
13947                 reg: regInfo{
13948                         inputs: []inputInfo{
13949                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13950                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13951                         },
13952                         outputs: []outputInfo{
13953                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13954                         },
13955                 },
13956         },
13957         {
13958                 name:           "XCHGQ",
13959                 auxType:        auxSymOff,
13960                 argLen:         3,
13961                 resultInArg0:   true,
13962                 faultOnNilArg1: true,
13963                 hasSideEffects: true,
13964                 symEffect:      SymRdWr,
13965                 asm:            x86.AXCHGQ,
13966                 reg: regInfo{
13967                         inputs: []inputInfo{
13968                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13969                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13970                         },
13971                         outputs: []outputInfo{
13972                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13973                         },
13974                 },
13975         },
13976         {
13977                 name:           "XADDLlock",
13978                 auxType:        auxSymOff,
13979                 argLen:         3,
13980                 resultInArg0:   true,
13981                 clobberFlags:   true,
13982                 faultOnNilArg1: true,
13983                 hasSideEffects: true,
13984                 symEffect:      SymRdWr,
13985                 asm:            x86.AXADDL,
13986                 reg: regInfo{
13987                         inputs: []inputInfo{
13988                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13989                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13990                         },
13991                         outputs: []outputInfo{
13992                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13993                         },
13994                 },
13995         },
13996         {
13997                 name:           "XADDQlock",
13998                 auxType:        auxSymOff,
13999                 argLen:         3,
14000                 resultInArg0:   true,
14001                 clobberFlags:   true,
14002                 faultOnNilArg1: true,
14003                 hasSideEffects: true,
14004                 symEffect:      SymRdWr,
14005                 asm:            x86.AXADDQ,
14006                 reg: regInfo{
14007                         inputs: []inputInfo{
14008                                 {0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14009                                 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14010                         },
14011                         outputs: []outputInfo{
14012                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14013                         },
14014                 },
14015         },
14016         {
14017                 name:   "AddTupleFirst32",
14018                 argLen: 2,
14019                 reg:    regInfo{},
14020         },
14021         {
14022                 name:   "AddTupleFirst64",
14023                 argLen: 2,
14024                 reg:    regInfo{},
14025         },
14026         {
14027                 name:           "CMPXCHGLlock",
14028                 auxType:        auxSymOff,
14029                 argLen:         4,
14030                 clobberFlags:   true,
14031                 faultOnNilArg0: true,
14032                 hasSideEffects: true,
14033                 symEffect:      SymRdWr,
14034                 asm:            x86.ACMPXCHGL,
14035                 reg: regInfo{
14036                         inputs: []inputInfo{
14037                                 {1, 1},     // AX
14038                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14039                                 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14040                         },
14041                         clobbers: 1, // AX
14042                         outputs: []outputInfo{
14043                                 {1, 0},
14044                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14045                         },
14046                 },
14047         },
14048         {
14049                 name:           "CMPXCHGQlock",
14050                 auxType:        auxSymOff,
14051                 argLen:         4,
14052                 clobberFlags:   true,
14053                 faultOnNilArg0: true,
14054                 hasSideEffects: true,
14055                 symEffect:      SymRdWr,
14056                 asm:            x86.ACMPXCHGQ,
14057                 reg: regInfo{
14058                         inputs: []inputInfo{
14059                                 {1, 1},     // AX
14060                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14061                                 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14062                         },
14063                         clobbers: 1, // AX
14064                         outputs: []outputInfo{
14065                                 {1, 0},
14066                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14067                         },
14068                 },
14069         },
14070         {
14071                 name:           "ANDBlock",
14072                 auxType:        auxSymOff,
14073                 argLen:         3,
14074                 clobberFlags:   true,
14075                 faultOnNilArg0: true,
14076                 hasSideEffects: true,
14077                 symEffect:      SymRdWr,
14078                 asm:            x86.AANDB,
14079                 reg: regInfo{
14080                         inputs: []inputInfo{
14081                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14082                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14083                         },
14084                 },
14085         },
14086         {
14087                 name:           "ANDLlock",
14088                 auxType:        auxSymOff,
14089                 argLen:         3,
14090                 clobberFlags:   true,
14091                 faultOnNilArg0: true,
14092                 hasSideEffects: true,
14093                 symEffect:      SymRdWr,
14094                 asm:            x86.AANDL,
14095                 reg: regInfo{
14096                         inputs: []inputInfo{
14097                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14098                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14099                         },
14100                 },
14101         },
14102         {
14103                 name:           "ORBlock",
14104                 auxType:        auxSymOff,
14105                 argLen:         3,
14106                 clobberFlags:   true,
14107                 faultOnNilArg0: true,
14108                 hasSideEffects: true,
14109                 symEffect:      SymRdWr,
14110                 asm:            x86.AORB,
14111                 reg: regInfo{
14112                         inputs: []inputInfo{
14113                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14114                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14115                         },
14116                 },
14117         },
14118         {
14119                 name:           "ORLlock",
14120                 auxType:        auxSymOff,
14121                 argLen:         3,
14122                 clobberFlags:   true,
14123                 faultOnNilArg0: true,
14124                 hasSideEffects: true,
14125                 symEffect:      SymRdWr,
14126                 asm:            x86.AORL,
14127                 reg: regInfo{
14128                         inputs: []inputInfo{
14129                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14130                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14131                         },
14132                 },
14133         },
14134         {
14135                 name:           "PrefetchT0",
14136                 argLen:         2,
14137                 hasSideEffects: true,
14138                 asm:            x86.APREFETCHT0,
14139                 reg: regInfo{
14140                         inputs: []inputInfo{
14141                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14142                         },
14143                 },
14144         },
14145         {
14146                 name:           "PrefetchNTA",
14147                 argLen:         2,
14148                 hasSideEffects: true,
14149                 asm:            x86.APREFETCHNTA,
14150                 reg: regInfo{
14151                         inputs: []inputInfo{
14152                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14153                         },
14154                 },
14155         },
14156         {
14157                 name:         "ANDNQ",
14158                 argLen:       2,
14159                 clobberFlags: true,
14160                 asm:          x86.AANDNQ,
14161                 reg: regInfo{
14162                         inputs: []inputInfo{
14163                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14164                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14165                         },
14166                         outputs: []outputInfo{
14167                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14168                         },
14169                 },
14170         },
14171         {
14172                 name:         "ANDNL",
14173                 argLen:       2,
14174                 clobberFlags: true,
14175                 asm:          x86.AANDNL,
14176                 reg: regInfo{
14177                         inputs: []inputInfo{
14178                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14179                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14180                         },
14181                         outputs: []outputInfo{
14182                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14183                         },
14184                 },
14185         },
14186         {
14187                 name:         "BLSIQ",
14188                 argLen:       1,
14189                 clobberFlags: true,
14190                 asm:          x86.ABLSIQ,
14191                 reg: regInfo{
14192                         inputs: []inputInfo{
14193                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14194                         },
14195                         outputs: []outputInfo{
14196                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14197                         },
14198                 },
14199         },
14200         {
14201                 name:         "BLSIL",
14202                 argLen:       1,
14203                 clobberFlags: true,
14204                 asm:          x86.ABLSIL,
14205                 reg: regInfo{
14206                         inputs: []inputInfo{
14207                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14208                         },
14209                         outputs: []outputInfo{
14210                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14211                         },
14212                 },
14213         },
14214         {
14215                 name:         "BLSMSKQ",
14216                 argLen:       1,
14217                 clobberFlags: true,
14218                 asm:          x86.ABLSMSKQ,
14219                 reg: regInfo{
14220                         inputs: []inputInfo{
14221                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14222                         },
14223                         outputs: []outputInfo{
14224                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14225                         },
14226                 },
14227         },
14228         {
14229                 name:         "BLSMSKL",
14230                 argLen:       1,
14231                 clobberFlags: true,
14232                 asm:          x86.ABLSMSKL,
14233                 reg: regInfo{
14234                         inputs: []inputInfo{
14235                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14236                         },
14237                         outputs: []outputInfo{
14238                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14239                         },
14240                 },
14241         },
14242         {
14243                 name:   "BLSRQ",
14244                 argLen: 1,
14245                 asm:    x86.ABLSRQ,
14246                 reg: regInfo{
14247                         inputs: []inputInfo{
14248                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14249                         },
14250                         outputs: []outputInfo{
14251                                 {1, 0},
14252                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14253                         },
14254                 },
14255         },
14256         {
14257                 name:   "BLSRL",
14258                 argLen: 1,
14259                 asm:    x86.ABLSRL,
14260                 reg: regInfo{
14261                         inputs: []inputInfo{
14262                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14263                         },
14264                         outputs: []outputInfo{
14265                                 {1, 0},
14266                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14267                         },
14268                 },
14269         },
14270         {
14271                 name:         "TZCNTQ",
14272                 argLen:       1,
14273                 clobberFlags: true,
14274                 asm:          x86.ATZCNTQ,
14275                 reg: regInfo{
14276                         inputs: []inputInfo{
14277                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14278                         },
14279                         outputs: []outputInfo{
14280                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14281                         },
14282                 },
14283         },
14284         {
14285                 name:         "TZCNTL",
14286                 argLen:       1,
14287                 clobberFlags: true,
14288                 asm:          x86.ATZCNTL,
14289                 reg: regInfo{
14290                         inputs: []inputInfo{
14291                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14292                         },
14293                         outputs: []outputInfo{
14294                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14295                         },
14296                 },
14297         },
14298         {
14299                 name:         "LZCNTQ",
14300                 argLen:       1,
14301                 clobberFlags: true,
14302                 asm:          x86.ALZCNTQ,
14303                 reg: regInfo{
14304                         inputs: []inputInfo{
14305                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14306                         },
14307                         outputs: []outputInfo{
14308                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14309                         },
14310                 },
14311         },
14312         {
14313                 name:         "LZCNTL",
14314                 argLen:       1,
14315                 clobberFlags: true,
14316                 asm:          x86.ALZCNTL,
14317                 reg: regInfo{
14318                         inputs: []inputInfo{
14319                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14320                         },
14321                         outputs: []outputInfo{
14322                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14323                         },
14324                 },
14325         },
14326         {
14327                 name:           "MOVBEWstore",
14328                 auxType:        auxSymOff,
14329                 argLen:         3,
14330                 faultOnNilArg0: true,
14331                 symEffect:      SymWrite,
14332                 asm:            x86.AMOVBEW,
14333                 reg: regInfo{
14334                         inputs: []inputInfo{
14335                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14336                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14337                         },
14338                 },
14339         },
14340         {
14341                 name:           "MOVBELload",
14342                 auxType:        auxSymOff,
14343                 argLen:         2,
14344                 faultOnNilArg0: true,
14345                 symEffect:      SymRead,
14346                 asm:            x86.AMOVBEL,
14347                 reg: regInfo{
14348                         inputs: []inputInfo{
14349                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14350                         },
14351                         outputs: []outputInfo{
14352                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14353                         },
14354                 },
14355         },
14356         {
14357                 name:           "MOVBELstore",
14358                 auxType:        auxSymOff,
14359                 argLen:         3,
14360                 faultOnNilArg0: true,
14361                 symEffect:      SymWrite,
14362                 asm:            x86.AMOVBEL,
14363                 reg: regInfo{
14364                         inputs: []inputInfo{
14365                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14366                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14367                         },
14368                 },
14369         },
14370         {
14371                 name:           "MOVBEQload",
14372                 auxType:        auxSymOff,
14373                 argLen:         2,
14374                 faultOnNilArg0: true,
14375                 symEffect:      SymRead,
14376                 asm:            x86.AMOVBEQ,
14377                 reg: regInfo{
14378                         inputs: []inputInfo{
14379                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14380                         },
14381                         outputs: []outputInfo{
14382                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14383                         },
14384                 },
14385         },
14386         {
14387                 name:           "MOVBEQstore",
14388                 auxType:        auxSymOff,
14389                 argLen:         3,
14390                 faultOnNilArg0: true,
14391                 symEffect:      SymWrite,
14392                 asm:            x86.AMOVBEQ,
14393                 reg: regInfo{
14394                         inputs: []inputInfo{
14395                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14396                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14397                         },
14398                 },
14399         },
14400         {
14401                 name:        "MOVBELloadidx1",
14402                 auxType:     auxSymOff,
14403                 argLen:      3,
14404                 commutative: true,
14405                 symEffect:   SymRead,
14406                 asm:         x86.AMOVBEL,
14407                 scale:       1,
14408                 reg: regInfo{
14409                         inputs: []inputInfo{
14410                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14411                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14412                         },
14413                         outputs: []outputInfo{
14414                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14415                         },
14416                 },
14417         },
14418         {
14419                 name:      "MOVBELloadidx4",
14420                 auxType:   auxSymOff,
14421                 argLen:    3,
14422                 symEffect: SymRead,
14423                 asm:       x86.AMOVBEL,
14424                 scale:     4,
14425                 reg: regInfo{
14426                         inputs: []inputInfo{
14427                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14428                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14429                         },
14430                         outputs: []outputInfo{
14431                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14432                         },
14433                 },
14434         },
14435         {
14436                 name:      "MOVBELloadidx8",
14437                 auxType:   auxSymOff,
14438                 argLen:    3,
14439                 symEffect: SymRead,
14440                 asm:       x86.AMOVBEL,
14441                 scale:     8,
14442                 reg: regInfo{
14443                         inputs: []inputInfo{
14444                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14445                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14446                         },
14447                         outputs: []outputInfo{
14448                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14449                         },
14450                 },
14451         },
14452         {
14453                 name:        "MOVBEQloadidx1",
14454                 auxType:     auxSymOff,
14455                 argLen:      3,
14456                 commutative: true,
14457                 symEffect:   SymRead,
14458                 asm:         x86.AMOVBEQ,
14459                 scale:       1,
14460                 reg: regInfo{
14461                         inputs: []inputInfo{
14462                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14463                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14464                         },
14465                         outputs: []outputInfo{
14466                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14467                         },
14468                 },
14469         },
14470         {
14471                 name:      "MOVBEQloadidx8",
14472                 auxType:   auxSymOff,
14473                 argLen:    3,
14474                 symEffect: SymRead,
14475                 asm:       x86.AMOVBEQ,
14476                 scale:     8,
14477                 reg: regInfo{
14478                         inputs: []inputInfo{
14479                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14480                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14481                         },
14482                         outputs: []outputInfo{
14483                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14484                         },
14485                 },
14486         },
14487         {
14488                 name:        "MOVBEWstoreidx1",
14489                 auxType:     auxSymOff,
14490                 argLen:      4,
14491                 commutative: true,
14492                 symEffect:   SymWrite,
14493                 asm:         x86.AMOVBEW,
14494                 scale:       1,
14495                 reg: regInfo{
14496                         inputs: []inputInfo{
14497                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14498                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14499                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14500                         },
14501                 },
14502         },
14503         {
14504                 name:      "MOVBEWstoreidx2",
14505                 auxType:   auxSymOff,
14506                 argLen:    4,
14507                 symEffect: SymWrite,
14508                 asm:       x86.AMOVBEW,
14509                 scale:     2,
14510                 reg: regInfo{
14511                         inputs: []inputInfo{
14512                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14513                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14514                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14515                         },
14516                 },
14517         },
14518         {
14519                 name:        "MOVBELstoreidx1",
14520                 auxType:     auxSymOff,
14521                 argLen:      4,
14522                 commutative: true,
14523                 symEffect:   SymWrite,
14524                 asm:         x86.AMOVBEL,
14525                 scale:       1,
14526                 reg: regInfo{
14527                         inputs: []inputInfo{
14528                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14529                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14530                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14531                         },
14532                 },
14533         },
14534         {
14535                 name:      "MOVBELstoreidx4",
14536                 auxType:   auxSymOff,
14537                 argLen:    4,
14538                 symEffect: SymWrite,
14539                 asm:       x86.AMOVBEL,
14540                 scale:     4,
14541                 reg: regInfo{
14542                         inputs: []inputInfo{
14543                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14544                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14545                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14546                         },
14547                 },
14548         },
14549         {
14550                 name:      "MOVBELstoreidx8",
14551                 auxType:   auxSymOff,
14552                 argLen:    4,
14553                 symEffect: SymWrite,
14554                 asm:       x86.AMOVBEL,
14555                 scale:     8,
14556                 reg: regInfo{
14557                         inputs: []inputInfo{
14558                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14559                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14560                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14561                         },
14562                 },
14563         },
14564         {
14565                 name:        "MOVBEQstoreidx1",
14566                 auxType:     auxSymOff,
14567                 argLen:      4,
14568                 commutative: true,
14569                 symEffect:   SymWrite,
14570                 asm:         x86.AMOVBEQ,
14571                 scale:       1,
14572                 reg: regInfo{
14573                         inputs: []inputInfo{
14574                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14575                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14576                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14577                         },
14578                 },
14579         },
14580         {
14581                 name:      "MOVBEQstoreidx8",
14582                 auxType:   auxSymOff,
14583                 argLen:    4,
14584                 symEffect: SymWrite,
14585                 asm:       x86.AMOVBEQ,
14586                 scale:     8,
14587                 reg: regInfo{
14588                         inputs: []inputInfo{
14589                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14590                                 {2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14591                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14592                         },
14593                 },
14594         },
14595         {
14596                 name:   "SARXQ",
14597                 argLen: 2,
14598                 asm:    x86.ASARXQ,
14599                 reg: regInfo{
14600                         inputs: []inputInfo{
14601                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14602                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14603                         },
14604                         outputs: []outputInfo{
14605                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14606                         },
14607                 },
14608         },
14609         {
14610                 name:   "SARXL",
14611                 argLen: 2,
14612                 asm:    x86.ASARXL,
14613                 reg: regInfo{
14614                         inputs: []inputInfo{
14615                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14616                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14617                         },
14618                         outputs: []outputInfo{
14619                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14620                         },
14621                 },
14622         },
14623         {
14624                 name:   "SHLXQ",
14625                 argLen: 2,
14626                 asm:    x86.ASHLXQ,
14627                 reg: regInfo{
14628                         inputs: []inputInfo{
14629                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14630                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14631                         },
14632                         outputs: []outputInfo{
14633                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14634                         },
14635                 },
14636         },
14637         {
14638                 name:   "SHLXL",
14639                 argLen: 2,
14640                 asm:    x86.ASHLXL,
14641                 reg: regInfo{
14642                         inputs: []inputInfo{
14643                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14644                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14645                         },
14646                         outputs: []outputInfo{
14647                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14648                         },
14649                 },
14650         },
14651         {
14652                 name:   "SHRXQ",
14653                 argLen: 2,
14654                 asm:    x86.ASHRXQ,
14655                 reg: regInfo{
14656                         inputs: []inputInfo{
14657                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14658                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14659                         },
14660                         outputs: []outputInfo{
14661                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14662                         },
14663                 },
14664         },
14665         {
14666                 name:   "SHRXL",
14667                 argLen: 2,
14668                 asm:    x86.ASHRXL,
14669                 reg: regInfo{
14670                         inputs: []inputInfo{
14671                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14672                                 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14673                         },
14674                         outputs: []outputInfo{
14675                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14676                         },
14677                 },
14678         },
14679         {
14680                 name:           "SARXLload",
14681                 auxType:        auxSymOff,
14682                 argLen:         3,
14683                 faultOnNilArg0: true,
14684                 symEffect:      SymRead,
14685                 asm:            x86.ASARXL,
14686                 reg: regInfo{
14687                         inputs: []inputInfo{
14688                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14689                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14690                         },
14691                         outputs: []outputInfo{
14692                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14693                         },
14694                 },
14695         },
14696         {
14697                 name:           "SARXQload",
14698                 auxType:        auxSymOff,
14699                 argLen:         3,
14700                 faultOnNilArg0: true,
14701                 symEffect:      SymRead,
14702                 asm:            x86.ASARXQ,
14703                 reg: regInfo{
14704                         inputs: []inputInfo{
14705                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14706                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14707                         },
14708                         outputs: []outputInfo{
14709                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14710                         },
14711                 },
14712         },
14713         {
14714                 name:           "SHLXLload",
14715                 auxType:        auxSymOff,
14716                 argLen:         3,
14717                 faultOnNilArg0: true,
14718                 symEffect:      SymRead,
14719                 asm:            x86.ASHLXL,
14720                 reg: regInfo{
14721                         inputs: []inputInfo{
14722                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14723                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14724                         },
14725                         outputs: []outputInfo{
14726                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14727                         },
14728                 },
14729         },
14730         {
14731                 name:           "SHLXQload",
14732                 auxType:        auxSymOff,
14733                 argLen:         3,
14734                 faultOnNilArg0: true,
14735                 symEffect:      SymRead,
14736                 asm:            x86.ASHLXQ,
14737                 reg: regInfo{
14738                         inputs: []inputInfo{
14739                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14740                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14741                         },
14742                         outputs: []outputInfo{
14743                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14744                         },
14745                 },
14746         },
14747         {
14748                 name:           "SHRXLload",
14749                 auxType:        auxSymOff,
14750                 argLen:         3,
14751                 faultOnNilArg0: true,
14752                 symEffect:      SymRead,
14753                 asm:            x86.ASHRXL,
14754                 reg: regInfo{
14755                         inputs: []inputInfo{
14756                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14757                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14758                         },
14759                         outputs: []outputInfo{
14760                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14761                         },
14762                 },
14763         },
14764         {
14765                 name:           "SHRXQload",
14766                 auxType:        auxSymOff,
14767                 argLen:         3,
14768                 faultOnNilArg0: true,
14769                 symEffect:      SymRead,
14770                 asm:            x86.ASHRXQ,
14771                 reg: regInfo{
14772                         inputs: []inputInfo{
14773                                 {1, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14774                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14775                         },
14776                         outputs: []outputInfo{
14777                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14778                         },
14779                 },
14780         },
14781         {
14782                 name:           "SARXLloadidx1",
14783                 auxType:        auxSymOff,
14784                 argLen:         4,
14785                 faultOnNilArg0: true,
14786                 symEffect:      SymRead,
14787                 asm:            x86.ASARXL,
14788                 scale:          1,
14789                 reg: regInfo{
14790                         inputs: []inputInfo{
14791                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14792                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14793                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14794                         },
14795                         outputs: []outputInfo{
14796                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14797                         },
14798                 },
14799         },
14800         {
14801                 name:           "SARXLloadidx4",
14802                 auxType:        auxSymOff,
14803                 argLen:         4,
14804                 faultOnNilArg0: true,
14805                 symEffect:      SymRead,
14806                 asm:            x86.ASARXL,
14807                 scale:          4,
14808                 reg: regInfo{
14809                         inputs: []inputInfo{
14810                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14811                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14812                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14813                         },
14814                         outputs: []outputInfo{
14815                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14816                         },
14817                 },
14818         },
14819         {
14820                 name:           "SARXLloadidx8",
14821                 auxType:        auxSymOff,
14822                 argLen:         4,
14823                 faultOnNilArg0: true,
14824                 symEffect:      SymRead,
14825                 asm:            x86.ASARXL,
14826                 scale:          8,
14827                 reg: regInfo{
14828                         inputs: []inputInfo{
14829                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14830                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14831                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14832                         },
14833                         outputs: []outputInfo{
14834                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14835                         },
14836                 },
14837         },
14838         {
14839                 name:           "SARXQloadidx1",
14840                 auxType:        auxSymOff,
14841                 argLen:         4,
14842                 faultOnNilArg0: true,
14843                 symEffect:      SymRead,
14844                 asm:            x86.ASARXQ,
14845                 scale:          1,
14846                 reg: regInfo{
14847                         inputs: []inputInfo{
14848                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14849                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14850                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14851                         },
14852                         outputs: []outputInfo{
14853                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14854                         },
14855                 },
14856         },
14857         {
14858                 name:           "SARXQloadidx8",
14859                 auxType:        auxSymOff,
14860                 argLen:         4,
14861                 faultOnNilArg0: true,
14862                 symEffect:      SymRead,
14863                 asm:            x86.ASARXQ,
14864                 scale:          8,
14865                 reg: regInfo{
14866                         inputs: []inputInfo{
14867                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14868                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14869                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14870                         },
14871                         outputs: []outputInfo{
14872                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14873                         },
14874                 },
14875         },
14876         {
14877                 name:           "SHLXLloadidx1",
14878                 auxType:        auxSymOff,
14879                 argLen:         4,
14880                 faultOnNilArg0: true,
14881                 symEffect:      SymRead,
14882                 asm:            x86.ASHLXL,
14883                 scale:          1,
14884                 reg: regInfo{
14885                         inputs: []inputInfo{
14886                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14887                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14888                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14889                         },
14890                         outputs: []outputInfo{
14891                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14892                         },
14893                 },
14894         },
14895         {
14896                 name:           "SHLXLloadidx4",
14897                 auxType:        auxSymOff,
14898                 argLen:         4,
14899                 faultOnNilArg0: true,
14900                 symEffect:      SymRead,
14901                 asm:            x86.ASHLXL,
14902                 scale:          4,
14903                 reg: regInfo{
14904                         inputs: []inputInfo{
14905                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14906                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14907                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14908                         },
14909                         outputs: []outputInfo{
14910                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14911                         },
14912                 },
14913         },
14914         {
14915                 name:           "SHLXLloadidx8",
14916                 auxType:        auxSymOff,
14917                 argLen:         4,
14918                 faultOnNilArg0: true,
14919                 symEffect:      SymRead,
14920                 asm:            x86.ASHLXL,
14921                 scale:          8,
14922                 reg: regInfo{
14923                         inputs: []inputInfo{
14924                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14925                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14926                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14927                         },
14928                         outputs: []outputInfo{
14929                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14930                         },
14931                 },
14932         },
14933         {
14934                 name:           "SHLXQloadidx1",
14935                 auxType:        auxSymOff,
14936                 argLen:         4,
14937                 faultOnNilArg0: true,
14938                 symEffect:      SymRead,
14939                 asm:            x86.ASHLXQ,
14940                 scale:          1,
14941                 reg: regInfo{
14942                         inputs: []inputInfo{
14943                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14944                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14945                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14946                         },
14947                         outputs: []outputInfo{
14948                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14949                         },
14950                 },
14951         },
14952         {
14953                 name:           "SHLXQloadidx8",
14954                 auxType:        auxSymOff,
14955                 argLen:         4,
14956                 faultOnNilArg0: true,
14957                 symEffect:      SymRead,
14958                 asm:            x86.ASHLXQ,
14959                 scale:          8,
14960                 reg: regInfo{
14961                         inputs: []inputInfo{
14962                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14963                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14964                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14965                         },
14966                         outputs: []outputInfo{
14967                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14968                         },
14969                 },
14970         },
14971         {
14972                 name:           "SHRXLloadidx1",
14973                 auxType:        auxSymOff,
14974                 argLen:         4,
14975                 faultOnNilArg0: true,
14976                 symEffect:      SymRead,
14977                 asm:            x86.ASHRXL,
14978                 scale:          1,
14979                 reg: regInfo{
14980                         inputs: []inputInfo{
14981                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14982                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
14983                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
14984                         },
14985                         outputs: []outputInfo{
14986                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
14987                         },
14988                 },
14989         },
14990         {
14991                 name:           "SHRXLloadidx4",
14992                 auxType:        auxSymOff,
14993                 argLen:         4,
14994                 faultOnNilArg0: true,
14995                 symEffect:      SymRead,
14996                 asm:            x86.ASHRXL,
14997                 scale:          4,
14998                 reg: regInfo{
14999                         inputs: []inputInfo{
15000                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15001                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
15002                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
15003                         },
15004                         outputs: []outputInfo{
15005                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15006                         },
15007                 },
15008         },
15009         {
15010                 name:           "SHRXLloadidx8",
15011                 auxType:        auxSymOff,
15012                 argLen:         4,
15013                 faultOnNilArg0: true,
15014                 symEffect:      SymRead,
15015                 asm:            x86.ASHRXL,
15016                 scale:          8,
15017                 reg: regInfo{
15018                         inputs: []inputInfo{
15019                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15020                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
15021                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
15022                         },
15023                         outputs: []outputInfo{
15024                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15025                         },
15026                 },
15027         },
15028         {
15029                 name:           "SHRXQloadidx1",
15030                 auxType:        auxSymOff,
15031                 argLen:         4,
15032                 faultOnNilArg0: true,
15033                 symEffect:      SymRead,
15034                 asm:            x86.ASHRXQ,
15035                 scale:          1,
15036                 reg: regInfo{
15037                         inputs: []inputInfo{
15038                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15039                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
15040                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
15041                         },
15042                         outputs: []outputInfo{
15043                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15044                         },
15045                 },
15046         },
15047         {
15048                 name:           "SHRXQloadidx8",
15049                 auxType:        auxSymOff,
15050                 argLen:         4,
15051                 faultOnNilArg0: true,
15052                 symEffect:      SymRead,
15053                 asm:            x86.ASHRXQ,
15054                 scale:          8,
15055                 reg: regInfo{
15056                         inputs: []inputInfo{
15057                                 {2, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15058                                 {1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
15059                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
15060                         },
15061                         outputs: []outputInfo{
15062                                 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
15063                         },
15064                 },
15065         },
15066
15067         {
15068                 name:        "ADD",
15069                 argLen:      2,
15070                 commutative: true,
15071                 asm:         arm.AADD,
15072                 reg: regInfo{
15073                         inputs: []inputInfo{
15074                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15075                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15076                         },
15077                         outputs: []outputInfo{
15078                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15079                         },
15080                 },
15081         },
15082         {
15083                 name:    "ADDconst",
15084                 auxType: auxInt32,
15085                 argLen:  1,
15086                 asm:     arm.AADD,
15087                 reg: regInfo{
15088                         inputs: []inputInfo{
15089                                 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
15090                         },
15091                         outputs: []outputInfo{
15092                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15093                         },
15094                 },
15095         },
15096         {
15097                 name:   "SUB",
15098                 argLen: 2,
15099                 asm:    arm.ASUB,
15100                 reg: regInfo{
15101                         inputs: []inputInfo{
15102                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15103                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15104                         },
15105                         outputs: []outputInfo{
15106                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15107                         },
15108                 },
15109         },
15110         {
15111                 name:    "SUBconst",
15112                 auxType: auxInt32,
15113                 argLen:  1,
15114                 asm:     arm.ASUB,
15115                 reg: regInfo{
15116                         inputs: []inputInfo{
15117                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15118                         },
15119                         outputs: []outputInfo{
15120                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15121                         },
15122                 },
15123         },
15124         {
15125                 name:   "RSB",
15126                 argLen: 2,
15127                 asm:    arm.ARSB,
15128                 reg: regInfo{
15129                         inputs: []inputInfo{
15130                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15131                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15132                         },
15133                         outputs: []outputInfo{
15134                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15135                         },
15136                 },
15137         },
15138         {
15139                 name:    "RSBconst",
15140                 auxType: auxInt32,
15141                 argLen:  1,
15142                 asm:     arm.ARSB,
15143                 reg: regInfo{
15144                         inputs: []inputInfo{
15145                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15146                         },
15147                         outputs: []outputInfo{
15148                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15149                         },
15150                 },
15151         },
15152         {
15153                 name:        "MUL",
15154                 argLen:      2,
15155                 commutative: true,
15156                 asm:         arm.AMUL,
15157                 reg: regInfo{
15158                         inputs: []inputInfo{
15159                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15160                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15161                         },
15162                         outputs: []outputInfo{
15163                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15164                         },
15165                 },
15166         },
15167         {
15168                 name:        "HMUL",
15169                 argLen:      2,
15170                 commutative: true,
15171                 asm:         arm.AMULL,
15172                 reg: regInfo{
15173                         inputs: []inputInfo{
15174                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15175                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15176                         },
15177                         outputs: []outputInfo{
15178                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15179                         },
15180                 },
15181         },
15182         {
15183                 name:        "HMULU",
15184                 argLen:      2,
15185                 commutative: true,
15186                 asm:         arm.AMULLU,
15187                 reg: regInfo{
15188                         inputs: []inputInfo{
15189                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15190                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15191                         },
15192                         outputs: []outputInfo{
15193                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15194                         },
15195                 },
15196         },
15197         {
15198                 name:         "CALLudiv",
15199                 argLen:       2,
15200                 clobberFlags: true,
15201                 reg: regInfo{
15202                         inputs: []inputInfo{
15203                                 {0, 2}, // R1
15204                                 {1, 1}, // R0
15205                         },
15206                         clobbers: 20492, // R2 R3 R12 R14
15207                         outputs: []outputInfo{
15208                                 {0, 1}, // R0
15209                                 {1, 2}, // R1
15210                         },
15211                 },
15212         },
15213         {
15214                 name:        "ADDS",
15215                 argLen:      2,
15216                 commutative: true,
15217                 asm:         arm.AADD,
15218                 reg: regInfo{
15219                         inputs: []inputInfo{
15220                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15221                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15222                         },
15223                         outputs: []outputInfo{
15224                                 {1, 0},
15225                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15226                         },
15227                 },
15228         },
15229         {
15230                 name:    "ADDSconst",
15231                 auxType: auxInt32,
15232                 argLen:  1,
15233                 asm:     arm.AADD,
15234                 reg: regInfo{
15235                         inputs: []inputInfo{
15236                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15237                         },
15238                         outputs: []outputInfo{
15239                                 {1, 0},
15240                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15241                         },
15242                 },
15243         },
15244         {
15245                 name:        "ADC",
15246                 argLen:      3,
15247                 commutative: true,
15248                 asm:         arm.AADC,
15249                 reg: regInfo{
15250                         inputs: []inputInfo{
15251                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15252                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15253                         },
15254                         outputs: []outputInfo{
15255                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15256                         },
15257                 },
15258         },
15259         {
15260                 name:    "ADCconst",
15261                 auxType: auxInt32,
15262                 argLen:  2,
15263                 asm:     arm.AADC,
15264                 reg: regInfo{
15265                         inputs: []inputInfo{
15266                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15267                         },
15268                         outputs: []outputInfo{
15269                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15270                         },
15271                 },
15272         },
15273         {
15274                 name:   "SUBS",
15275                 argLen: 2,
15276                 asm:    arm.ASUB,
15277                 reg: regInfo{
15278                         inputs: []inputInfo{
15279                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15280                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15281                         },
15282                         outputs: []outputInfo{
15283                                 {1, 0},
15284                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15285                         },
15286                 },
15287         },
15288         {
15289                 name:    "SUBSconst",
15290                 auxType: auxInt32,
15291                 argLen:  1,
15292                 asm:     arm.ASUB,
15293                 reg: regInfo{
15294                         inputs: []inputInfo{
15295                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15296                         },
15297                         outputs: []outputInfo{
15298                                 {1, 0},
15299                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15300                         },
15301                 },
15302         },
15303         {
15304                 name:    "RSBSconst",
15305                 auxType: auxInt32,
15306                 argLen:  1,
15307                 asm:     arm.ARSB,
15308                 reg: regInfo{
15309                         inputs: []inputInfo{
15310                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15311                         },
15312                         outputs: []outputInfo{
15313                                 {1, 0},
15314                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15315                         },
15316                 },
15317         },
15318         {
15319                 name:   "SBC",
15320                 argLen: 3,
15321                 asm:    arm.ASBC,
15322                 reg: regInfo{
15323                         inputs: []inputInfo{
15324                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15325                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15326                         },
15327                         outputs: []outputInfo{
15328                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15329                         },
15330                 },
15331         },
15332         {
15333                 name:    "SBCconst",
15334                 auxType: auxInt32,
15335                 argLen:  2,
15336                 asm:     arm.ASBC,
15337                 reg: regInfo{
15338                         inputs: []inputInfo{
15339                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15340                         },
15341                         outputs: []outputInfo{
15342                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15343                         },
15344                 },
15345         },
15346         {
15347                 name:    "RSCconst",
15348                 auxType: auxInt32,
15349                 argLen:  2,
15350                 asm:     arm.ARSC,
15351                 reg: regInfo{
15352                         inputs: []inputInfo{
15353                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15354                         },
15355                         outputs: []outputInfo{
15356                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15357                         },
15358                 },
15359         },
15360         {
15361                 name:        "MULLU",
15362                 argLen:      2,
15363                 commutative: true,
15364                 asm:         arm.AMULLU,
15365                 reg: regInfo{
15366                         inputs: []inputInfo{
15367                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15368                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15369                         },
15370                         outputs: []outputInfo{
15371                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15372                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15373                         },
15374                 },
15375         },
15376         {
15377                 name:   "MULA",
15378                 argLen: 3,
15379                 asm:    arm.AMULA,
15380                 reg: regInfo{
15381                         inputs: []inputInfo{
15382                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15383                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15384                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15385                         },
15386                         outputs: []outputInfo{
15387                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15388                         },
15389                 },
15390         },
15391         {
15392                 name:   "MULS",
15393                 argLen: 3,
15394                 asm:    arm.AMULS,
15395                 reg: regInfo{
15396                         inputs: []inputInfo{
15397                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15398                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15399                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15400                         },
15401                         outputs: []outputInfo{
15402                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15403                         },
15404                 },
15405         },
15406         {
15407                 name:        "ADDF",
15408                 argLen:      2,
15409                 commutative: true,
15410                 asm:         arm.AADDF,
15411                 reg: regInfo{
15412                         inputs: []inputInfo{
15413                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15414                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15415                         },
15416                         outputs: []outputInfo{
15417                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15418                         },
15419                 },
15420         },
15421         {
15422                 name:        "ADDD",
15423                 argLen:      2,
15424                 commutative: true,
15425                 asm:         arm.AADDD,
15426                 reg: regInfo{
15427                         inputs: []inputInfo{
15428                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15429                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15430                         },
15431                         outputs: []outputInfo{
15432                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15433                         },
15434                 },
15435         },
15436         {
15437                 name:   "SUBF",
15438                 argLen: 2,
15439                 asm:    arm.ASUBF,
15440                 reg: regInfo{
15441                         inputs: []inputInfo{
15442                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15443                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15444                         },
15445                         outputs: []outputInfo{
15446                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15447                         },
15448                 },
15449         },
15450         {
15451                 name:   "SUBD",
15452                 argLen: 2,
15453                 asm:    arm.ASUBD,
15454                 reg: regInfo{
15455                         inputs: []inputInfo{
15456                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15457                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15458                         },
15459                         outputs: []outputInfo{
15460                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15461                         },
15462                 },
15463         },
15464         {
15465                 name:        "MULF",
15466                 argLen:      2,
15467                 commutative: true,
15468                 asm:         arm.AMULF,
15469                 reg: regInfo{
15470                         inputs: []inputInfo{
15471                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15472                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15473                         },
15474                         outputs: []outputInfo{
15475                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15476                         },
15477                 },
15478         },
15479         {
15480                 name:        "MULD",
15481                 argLen:      2,
15482                 commutative: true,
15483                 asm:         arm.AMULD,
15484                 reg: regInfo{
15485                         inputs: []inputInfo{
15486                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15487                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15488                         },
15489                         outputs: []outputInfo{
15490                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15491                         },
15492                 },
15493         },
15494         {
15495                 name:        "NMULF",
15496                 argLen:      2,
15497                 commutative: true,
15498                 asm:         arm.ANMULF,
15499                 reg: regInfo{
15500                         inputs: []inputInfo{
15501                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15502                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15503                         },
15504                         outputs: []outputInfo{
15505                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15506                         },
15507                 },
15508         },
15509         {
15510                 name:        "NMULD",
15511                 argLen:      2,
15512                 commutative: true,
15513                 asm:         arm.ANMULD,
15514                 reg: regInfo{
15515                         inputs: []inputInfo{
15516                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15517                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15518                         },
15519                         outputs: []outputInfo{
15520                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15521                         },
15522                 },
15523         },
15524         {
15525                 name:   "DIVF",
15526                 argLen: 2,
15527                 asm:    arm.ADIVF,
15528                 reg: regInfo{
15529                         inputs: []inputInfo{
15530                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15531                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15532                         },
15533                         outputs: []outputInfo{
15534                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15535                         },
15536                 },
15537         },
15538         {
15539                 name:   "DIVD",
15540                 argLen: 2,
15541                 asm:    arm.ADIVD,
15542                 reg: regInfo{
15543                         inputs: []inputInfo{
15544                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15545                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15546                         },
15547                         outputs: []outputInfo{
15548                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15549                         },
15550                 },
15551         },
15552         {
15553                 name:         "MULAF",
15554                 argLen:       3,
15555                 resultInArg0: true,
15556                 asm:          arm.AMULAF,
15557                 reg: regInfo{
15558                         inputs: []inputInfo{
15559                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15560                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15561                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15562                         },
15563                         outputs: []outputInfo{
15564                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15565                         },
15566                 },
15567         },
15568         {
15569                 name:         "MULAD",
15570                 argLen:       3,
15571                 resultInArg0: true,
15572                 asm:          arm.AMULAD,
15573                 reg: regInfo{
15574                         inputs: []inputInfo{
15575                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15576                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15577                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15578                         },
15579                         outputs: []outputInfo{
15580                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15581                         },
15582                 },
15583         },
15584         {
15585                 name:         "MULSF",
15586                 argLen:       3,
15587                 resultInArg0: true,
15588                 asm:          arm.AMULSF,
15589                 reg: regInfo{
15590                         inputs: []inputInfo{
15591                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15592                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15593                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15594                         },
15595                         outputs: []outputInfo{
15596                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15597                         },
15598                 },
15599         },
15600         {
15601                 name:         "MULSD",
15602                 argLen:       3,
15603                 resultInArg0: true,
15604                 asm:          arm.AMULSD,
15605                 reg: regInfo{
15606                         inputs: []inputInfo{
15607                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15608                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15609                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15610                         },
15611                         outputs: []outputInfo{
15612                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15613                         },
15614                 },
15615         },
15616         {
15617                 name:         "FMULAD",
15618                 argLen:       3,
15619                 resultInArg0: true,
15620                 asm:          arm.AFMULAD,
15621                 reg: regInfo{
15622                         inputs: []inputInfo{
15623                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15624                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15625                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15626                         },
15627                         outputs: []outputInfo{
15628                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15629                         },
15630                 },
15631         },
15632         {
15633                 name:        "AND",
15634                 argLen:      2,
15635                 commutative: true,
15636                 asm:         arm.AAND,
15637                 reg: regInfo{
15638                         inputs: []inputInfo{
15639                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15640                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15641                         },
15642                         outputs: []outputInfo{
15643                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15644                         },
15645                 },
15646         },
15647         {
15648                 name:    "ANDconst",
15649                 auxType: auxInt32,
15650                 argLen:  1,
15651                 asm:     arm.AAND,
15652                 reg: regInfo{
15653                         inputs: []inputInfo{
15654                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15655                         },
15656                         outputs: []outputInfo{
15657                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15658                         },
15659                 },
15660         },
15661         {
15662                 name:        "OR",
15663                 argLen:      2,
15664                 commutative: true,
15665                 asm:         arm.AORR,
15666                 reg: regInfo{
15667                         inputs: []inputInfo{
15668                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15669                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15670                         },
15671                         outputs: []outputInfo{
15672                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15673                         },
15674                 },
15675         },
15676         {
15677                 name:    "ORconst",
15678                 auxType: auxInt32,
15679                 argLen:  1,
15680                 asm:     arm.AORR,
15681                 reg: regInfo{
15682                         inputs: []inputInfo{
15683                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15684                         },
15685                         outputs: []outputInfo{
15686                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15687                         },
15688                 },
15689         },
15690         {
15691                 name:        "XOR",
15692                 argLen:      2,
15693                 commutative: true,
15694                 asm:         arm.AEOR,
15695                 reg: regInfo{
15696                         inputs: []inputInfo{
15697                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15698                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15699                         },
15700                         outputs: []outputInfo{
15701                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15702                         },
15703                 },
15704         },
15705         {
15706                 name:    "XORconst",
15707                 auxType: auxInt32,
15708                 argLen:  1,
15709                 asm:     arm.AEOR,
15710                 reg: regInfo{
15711                         inputs: []inputInfo{
15712                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15713                         },
15714                         outputs: []outputInfo{
15715                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15716                         },
15717                 },
15718         },
15719         {
15720                 name:   "BIC",
15721                 argLen: 2,
15722                 asm:    arm.ABIC,
15723                 reg: regInfo{
15724                         inputs: []inputInfo{
15725                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15726                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15727                         },
15728                         outputs: []outputInfo{
15729                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15730                         },
15731                 },
15732         },
15733         {
15734                 name:    "BICconst",
15735                 auxType: auxInt32,
15736                 argLen:  1,
15737                 asm:     arm.ABIC,
15738                 reg: regInfo{
15739                         inputs: []inputInfo{
15740                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15741                         },
15742                         outputs: []outputInfo{
15743                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15744                         },
15745                 },
15746         },
15747         {
15748                 name:    "BFX",
15749                 auxType: auxInt32,
15750                 argLen:  1,
15751                 asm:     arm.ABFX,
15752                 reg: regInfo{
15753                         inputs: []inputInfo{
15754                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15755                         },
15756                         outputs: []outputInfo{
15757                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15758                         },
15759                 },
15760         },
15761         {
15762                 name:    "BFXU",
15763                 auxType: auxInt32,
15764                 argLen:  1,
15765                 asm:     arm.ABFXU,
15766                 reg: regInfo{
15767                         inputs: []inputInfo{
15768                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15769                         },
15770                         outputs: []outputInfo{
15771                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15772                         },
15773                 },
15774         },
15775         {
15776                 name:   "MVN",
15777                 argLen: 1,
15778                 asm:    arm.AMVN,
15779                 reg: regInfo{
15780                         inputs: []inputInfo{
15781                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15782                         },
15783                         outputs: []outputInfo{
15784                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15785                         },
15786                 },
15787         },
15788         {
15789                 name:   "NEGF",
15790                 argLen: 1,
15791                 asm:    arm.ANEGF,
15792                 reg: regInfo{
15793                         inputs: []inputInfo{
15794                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15795                         },
15796                         outputs: []outputInfo{
15797                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15798                         },
15799                 },
15800         },
15801         {
15802                 name:   "NEGD",
15803                 argLen: 1,
15804                 asm:    arm.ANEGD,
15805                 reg: regInfo{
15806                         inputs: []inputInfo{
15807                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15808                         },
15809                         outputs: []outputInfo{
15810                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15811                         },
15812                 },
15813         },
15814         {
15815                 name:   "SQRTD",
15816                 argLen: 1,
15817                 asm:    arm.ASQRTD,
15818                 reg: regInfo{
15819                         inputs: []inputInfo{
15820                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15821                         },
15822                         outputs: []outputInfo{
15823                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15824                         },
15825                 },
15826         },
15827         {
15828                 name:   "SQRTF",
15829                 argLen: 1,
15830                 asm:    arm.ASQRTF,
15831                 reg: regInfo{
15832                         inputs: []inputInfo{
15833                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15834                         },
15835                         outputs: []outputInfo{
15836                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15837                         },
15838                 },
15839         },
15840         {
15841                 name:   "ABSD",
15842                 argLen: 1,
15843                 asm:    arm.AABSD,
15844                 reg: regInfo{
15845                         inputs: []inputInfo{
15846                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15847                         },
15848                         outputs: []outputInfo{
15849                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15850                         },
15851                 },
15852         },
15853         {
15854                 name:   "CLZ",
15855                 argLen: 1,
15856                 asm:    arm.ACLZ,
15857                 reg: regInfo{
15858                         inputs: []inputInfo{
15859                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15860                         },
15861                         outputs: []outputInfo{
15862                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15863                         },
15864                 },
15865         },
15866         {
15867                 name:   "REV",
15868                 argLen: 1,
15869                 asm:    arm.AREV,
15870                 reg: regInfo{
15871                         inputs: []inputInfo{
15872                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15873                         },
15874                         outputs: []outputInfo{
15875                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15876                         },
15877                 },
15878         },
15879         {
15880                 name:   "REV16",
15881                 argLen: 1,
15882                 asm:    arm.AREV16,
15883                 reg: regInfo{
15884                         inputs: []inputInfo{
15885                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15886                         },
15887                         outputs: []outputInfo{
15888                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15889                         },
15890                 },
15891         },
15892         {
15893                 name:   "RBIT",
15894                 argLen: 1,
15895                 asm:    arm.ARBIT,
15896                 reg: regInfo{
15897                         inputs: []inputInfo{
15898                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15899                         },
15900                         outputs: []outputInfo{
15901                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15902                         },
15903                 },
15904         },
15905         {
15906                 name:   "SLL",
15907                 argLen: 2,
15908                 asm:    arm.ASLL,
15909                 reg: regInfo{
15910                         inputs: []inputInfo{
15911                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15912                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15913                         },
15914                         outputs: []outputInfo{
15915                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15916                         },
15917                 },
15918         },
15919         {
15920                 name:    "SLLconst",
15921                 auxType: auxInt32,
15922                 argLen:  1,
15923                 asm:     arm.ASLL,
15924                 reg: regInfo{
15925                         inputs: []inputInfo{
15926                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15927                         },
15928                         outputs: []outputInfo{
15929                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15930                         },
15931                 },
15932         },
15933         {
15934                 name:   "SRL",
15935                 argLen: 2,
15936                 asm:    arm.ASRL,
15937                 reg: regInfo{
15938                         inputs: []inputInfo{
15939                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15940                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15941                         },
15942                         outputs: []outputInfo{
15943                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15944                         },
15945                 },
15946         },
15947         {
15948                 name:    "SRLconst",
15949                 auxType: auxInt32,
15950                 argLen:  1,
15951                 asm:     arm.ASRL,
15952                 reg: regInfo{
15953                         inputs: []inputInfo{
15954                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15955                         },
15956                         outputs: []outputInfo{
15957                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15958                         },
15959                 },
15960         },
15961         {
15962                 name:   "SRA",
15963                 argLen: 2,
15964                 asm:    arm.ASRA,
15965                 reg: regInfo{
15966                         inputs: []inputInfo{
15967                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15968                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15969                         },
15970                         outputs: []outputInfo{
15971                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15972                         },
15973                 },
15974         },
15975         {
15976                 name:    "SRAconst",
15977                 auxType: auxInt32,
15978                 argLen:  1,
15979                 asm:     arm.ASRA,
15980                 reg: regInfo{
15981                         inputs: []inputInfo{
15982                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15983                         },
15984                         outputs: []outputInfo{
15985                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15986                         },
15987                 },
15988         },
15989         {
15990                 name:   "SRR",
15991                 argLen: 2,
15992                 reg: regInfo{
15993                         inputs: []inputInfo{
15994                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15995                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15996                         },
15997                         outputs: []outputInfo{
15998                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15999                         },
16000                 },
16001         },
16002         {
16003                 name:    "SRRconst",
16004                 auxType: auxInt32,
16005                 argLen:  1,
16006                 reg: regInfo{
16007                         inputs: []inputInfo{
16008                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16009                         },
16010                         outputs: []outputInfo{
16011                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16012                         },
16013                 },
16014         },
16015         {
16016                 name:    "ADDshiftLL",
16017                 auxType: auxInt32,
16018                 argLen:  2,
16019                 asm:     arm.AADD,
16020                 reg: regInfo{
16021                         inputs: []inputInfo{
16022                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16023                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16024                         },
16025                         outputs: []outputInfo{
16026                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16027                         },
16028                 },
16029         },
16030         {
16031                 name:    "ADDshiftRL",
16032                 auxType: auxInt32,
16033                 argLen:  2,
16034                 asm:     arm.AADD,
16035                 reg: regInfo{
16036                         inputs: []inputInfo{
16037                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16038                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16039                         },
16040                         outputs: []outputInfo{
16041                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16042                         },
16043                 },
16044         },
16045         {
16046                 name:    "ADDshiftRA",
16047                 auxType: auxInt32,
16048                 argLen:  2,
16049                 asm:     arm.AADD,
16050                 reg: regInfo{
16051                         inputs: []inputInfo{
16052                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16053                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16054                         },
16055                         outputs: []outputInfo{
16056                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16057                         },
16058                 },
16059         },
16060         {
16061                 name:    "SUBshiftLL",
16062                 auxType: auxInt32,
16063                 argLen:  2,
16064                 asm:     arm.ASUB,
16065                 reg: regInfo{
16066                         inputs: []inputInfo{
16067                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16068                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16069                         },
16070                         outputs: []outputInfo{
16071                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16072                         },
16073                 },
16074         },
16075         {
16076                 name:    "SUBshiftRL",
16077                 auxType: auxInt32,
16078                 argLen:  2,
16079                 asm:     arm.ASUB,
16080                 reg: regInfo{
16081                         inputs: []inputInfo{
16082                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16083                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16084                         },
16085                         outputs: []outputInfo{
16086                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16087                         },
16088                 },
16089         },
16090         {
16091                 name:    "SUBshiftRA",
16092                 auxType: auxInt32,
16093                 argLen:  2,
16094                 asm:     arm.ASUB,
16095                 reg: regInfo{
16096                         inputs: []inputInfo{
16097                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16098                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16099                         },
16100                         outputs: []outputInfo{
16101                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16102                         },
16103                 },
16104         },
16105         {
16106                 name:    "RSBshiftLL",
16107                 auxType: auxInt32,
16108                 argLen:  2,
16109                 asm:     arm.ARSB,
16110                 reg: regInfo{
16111                         inputs: []inputInfo{
16112                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16113                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16114                         },
16115                         outputs: []outputInfo{
16116                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16117                         },
16118                 },
16119         },
16120         {
16121                 name:    "RSBshiftRL",
16122                 auxType: auxInt32,
16123                 argLen:  2,
16124                 asm:     arm.ARSB,
16125                 reg: regInfo{
16126                         inputs: []inputInfo{
16127                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16128                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16129                         },
16130                         outputs: []outputInfo{
16131                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16132                         },
16133                 },
16134         },
16135         {
16136                 name:    "RSBshiftRA",
16137                 auxType: auxInt32,
16138                 argLen:  2,
16139                 asm:     arm.ARSB,
16140                 reg: regInfo{
16141                         inputs: []inputInfo{
16142                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16143                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16144                         },
16145                         outputs: []outputInfo{
16146                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16147                         },
16148                 },
16149         },
16150         {
16151                 name:    "ANDshiftLL",
16152                 auxType: auxInt32,
16153                 argLen:  2,
16154                 asm:     arm.AAND,
16155                 reg: regInfo{
16156                         inputs: []inputInfo{
16157                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16158                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16159                         },
16160                         outputs: []outputInfo{
16161                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16162                         },
16163                 },
16164         },
16165         {
16166                 name:    "ANDshiftRL",
16167                 auxType: auxInt32,
16168                 argLen:  2,
16169                 asm:     arm.AAND,
16170                 reg: regInfo{
16171                         inputs: []inputInfo{
16172                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16173                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16174                         },
16175                         outputs: []outputInfo{
16176                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16177                         },
16178                 },
16179         },
16180         {
16181                 name:    "ANDshiftRA",
16182                 auxType: auxInt32,
16183                 argLen:  2,
16184                 asm:     arm.AAND,
16185                 reg: regInfo{
16186                         inputs: []inputInfo{
16187                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16188                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16189                         },
16190                         outputs: []outputInfo{
16191                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16192                         },
16193                 },
16194         },
16195         {
16196                 name:    "ORshiftLL",
16197                 auxType: auxInt32,
16198                 argLen:  2,
16199                 asm:     arm.AORR,
16200                 reg: regInfo{
16201                         inputs: []inputInfo{
16202                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16203                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16204                         },
16205                         outputs: []outputInfo{
16206                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16207                         },
16208                 },
16209         },
16210         {
16211                 name:    "ORshiftRL",
16212                 auxType: auxInt32,
16213                 argLen:  2,
16214                 asm:     arm.AORR,
16215                 reg: regInfo{
16216                         inputs: []inputInfo{
16217                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16218                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16219                         },
16220                         outputs: []outputInfo{
16221                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16222                         },
16223                 },
16224         },
16225         {
16226                 name:    "ORshiftRA",
16227                 auxType: auxInt32,
16228                 argLen:  2,
16229                 asm:     arm.AORR,
16230                 reg: regInfo{
16231                         inputs: []inputInfo{
16232                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16233                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16234                         },
16235                         outputs: []outputInfo{
16236                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16237                         },
16238                 },
16239         },
16240         {
16241                 name:    "XORshiftLL",
16242                 auxType: auxInt32,
16243                 argLen:  2,
16244                 asm:     arm.AEOR,
16245                 reg: regInfo{
16246                         inputs: []inputInfo{
16247                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16248                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16249                         },
16250                         outputs: []outputInfo{
16251                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16252                         },
16253                 },
16254         },
16255         {
16256                 name:    "XORshiftRL",
16257                 auxType: auxInt32,
16258                 argLen:  2,
16259                 asm:     arm.AEOR,
16260                 reg: regInfo{
16261                         inputs: []inputInfo{
16262                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16263                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16264                         },
16265                         outputs: []outputInfo{
16266                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16267                         },
16268                 },
16269         },
16270         {
16271                 name:    "XORshiftRA",
16272                 auxType: auxInt32,
16273                 argLen:  2,
16274                 asm:     arm.AEOR,
16275                 reg: regInfo{
16276                         inputs: []inputInfo{
16277                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16278                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16279                         },
16280                         outputs: []outputInfo{
16281                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16282                         },
16283                 },
16284         },
16285         {
16286                 name:    "XORshiftRR",
16287                 auxType: auxInt32,
16288                 argLen:  2,
16289                 asm:     arm.AEOR,
16290                 reg: regInfo{
16291                         inputs: []inputInfo{
16292                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16293                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16294                         },
16295                         outputs: []outputInfo{
16296                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16297                         },
16298                 },
16299         },
16300         {
16301                 name:    "BICshiftLL",
16302                 auxType: auxInt32,
16303                 argLen:  2,
16304                 asm:     arm.ABIC,
16305                 reg: regInfo{
16306                         inputs: []inputInfo{
16307                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16308                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16309                         },
16310                         outputs: []outputInfo{
16311                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16312                         },
16313                 },
16314         },
16315         {
16316                 name:    "BICshiftRL",
16317                 auxType: auxInt32,
16318                 argLen:  2,
16319                 asm:     arm.ABIC,
16320                 reg: regInfo{
16321                         inputs: []inputInfo{
16322                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16323                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16324                         },
16325                         outputs: []outputInfo{
16326                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16327                         },
16328                 },
16329         },
16330         {
16331                 name:    "BICshiftRA",
16332                 auxType: auxInt32,
16333                 argLen:  2,
16334                 asm:     arm.ABIC,
16335                 reg: regInfo{
16336                         inputs: []inputInfo{
16337                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16338                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16339                         },
16340                         outputs: []outputInfo{
16341                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16342                         },
16343                 },
16344         },
16345         {
16346                 name:    "MVNshiftLL",
16347                 auxType: auxInt32,
16348                 argLen:  1,
16349                 asm:     arm.AMVN,
16350                 reg: regInfo{
16351                         inputs: []inputInfo{
16352                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16353                         },
16354                         outputs: []outputInfo{
16355                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16356                         },
16357                 },
16358         },
16359         {
16360                 name:    "MVNshiftRL",
16361                 auxType: auxInt32,
16362                 argLen:  1,
16363                 asm:     arm.AMVN,
16364                 reg: regInfo{
16365                         inputs: []inputInfo{
16366                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16367                         },
16368                         outputs: []outputInfo{
16369                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16370                         },
16371                 },
16372         },
16373         {
16374                 name:    "MVNshiftRA",
16375                 auxType: auxInt32,
16376                 argLen:  1,
16377                 asm:     arm.AMVN,
16378                 reg: regInfo{
16379                         inputs: []inputInfo{
16380                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16381                         },
16382                         outputs: []outputInfo{
16383                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16384                         },
16385                 },
16386         },
16387         {
16388                 name:    "ADCshiftLL",
16389                 auxType: auxInt32,
16390                 argLen:  3,
16391                 asm:     arm.AADC,
16392                 reg: regInfo{
16393                         inputs: []inputInfo{
16394                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16395                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16396                         },
16397                         outputs: []outputInfo{
16398                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16399                         },
16400                 },
16401         },
16402         {
16403                 name:    "ADCshiftRL",
16404                 auxType: auxInt32,
16405                 argLen:  3,
16406                 asm:     arm.AADC,
16407                 reg: regInfo{
16408                         inputs: []inputInfo{
16409                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16410                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16411                         },
16412                         outputs: []outputInfo{
16413                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16414                         },
16415                 },
16416         },
16417         {
16418                 name:    "ADCshiftRA",
16419                 auxType: auxInt32,
16420                 argLen:  3,
16421                 asm:     arm.AADC,
16422                 reg: regInfo{
16423                         inputs: []inputInfo{
16424                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16425                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16426                         },
16427                         outputs: []outputInfo{
16428                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16429                         },
16430                 },
16431         },
16432         {
16433                 name:    "SBCshiftLL",
16434                 auxType: auxInt32,
16435                 argLen:  3,
16436                 asm:     arm.ASBC,
16437                 reg: regInfo{
16438                         inputs: []inputInfo{
16439                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16440                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16441                         },
16442                         outputs: []outputInfo{
16443                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16444                         },
16445                 },
16446         },
16447         {
16448                 name:    "SBCshiftRL",
16449                 auxType: auxInt32,
16450                 argLen:  3,
16451                 asm:     arm.ASBC,
16452                 reg: regInfo{
16453                         inputs: []inputInfo{
16454                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16455                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16456                         },
16457                         outputs: []outputInfo{
16458                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16459                         },
16460                 },
16461         },
16462         {
16463                 name:    "SBCshiftRA",
16464                 auxType: auxInt32,
16465                 argLen:  3,
16466                 asm:     arm.ASBC,
16467                 reg: regInfo{
16468                         inputs: []inputInfo{
16469                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16470                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16471                         },
16472                         outputs: []outputInfo{
16473                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16474                         },
16475                 },
16476         },
16477         {
16478                 name:    "RSCshiftLL",
16479                 auxType: auxInt32,
16480                 argLen:  3,
16481                 asm:     arm.ARSC,
16482                 reg: regInfo{
16483                         inputs: []inputInfo{
16484                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16485                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16486                         },
16487                         outputs: []outputInfo{
16488                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16489                         },
16490                 },
16491         },
16492         {
16493                 name:    "RSCshiftRL",
16494                 auxType: auxInt32,
16495                 argLen:  3,
16496                 asm:     arm.ARSC,
16497                 reg: regInfo{
16498                         inputs: []inputInfo{
16499                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16500                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16501                         },
16502                         outputs: []outputInfo{
16503                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16504                         },
16505                 },
16506         },
16507         {
16508                 name:    "RSCshiftRA",
16509                 auxType: auxInt32,
16510                 argLen:  3,
16511                 asm:     arm.ARSC,
16512                 reg: regInfo{
16513                         inputs: []inputInfo{
16514                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16515                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16516                         },
16517                         outputs: []outputInfo{
16518                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16519                         },
16520                 },
16521         },
16522         {
16523                 name:    "ADDSshiftLL",
16524                 auxType: auxInt32,
16525                 argLen:  2,
16526                 asm:     arm.AADD,
16527                 reg: regInfo{
16528                         inputs: []inputInfo{
16529                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16530                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16531                         },
16532                         outputs: []outputInfo{
16533                                 {1, 0},
16534                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16535                         },
16536                 },
16537         },
16538         {
16539                 name:    "ADDSshiftRL",
16540                 auxType: auxInt32,
16541                 argLen:  2,
16542                 asm:     arm.AADD,
16543                 reg: regInfo{
16544                         inputs: []inputInfo{
16545                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16546                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16547                         },
16548                         outputs: []outputInfo{
16549                                 {1, 0},
16550                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16551                         },
16552                 },
16553         },
16554         {
16555                 name:    "ADDSshiftRA",
16556                 auxType: auxInt32,
16557                 argLen:  2,
16558                 asm:     arm.AADD,
16559                 reg: regInfo{
16560                         inputs: []inputInfo{
16561                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16562                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16563                         },
16564                         outputs: []outputInfo{
16565                                 {1, 0},
16566                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16567                         },
16568                 },
16569         },
16570         {
16571                 name:    "SUBSshiftLL",
16572                 auxType: auxInt32,
16573                 argLen:  2,
16574                 asm:     arm.ASUB,
16575                 reg: regInfo{
16576                         inputs: []inputInfo{
16577                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16578                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16579                         },
16580                         outputs: []outputInfo{
16581                                 {1, 0},
16582                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16583                         },
16584                 },
16585         },
16586         {
16587                 name:    "SUBSshiftRL",
16588                 auxType: auxInt32,
16589                 argLen:  2,
16590                 asm:     arm.ASUB,
16591                 reg: regInfo{
16592                         inputs: []inputInfo{
16593                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16594                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16595                         },
16596                         outputs: []outputInfo{
16597                                 {1, 0},
16598                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16599                         },
16600                 },
16601         },
16602         {
16603                 name:    "SUBSshiftRA",
16604                 auxType: auxInt32,
16605                 argLen:  2,
16606                 asm:     arm.ASUB,
16607                 reg: regInfo{
16608                         inputs: []inputInfo{
16609                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16610                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16611                         },
16612                         outputs: []outputInfo{
16613                                 {1, 0},
16614                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16615                         },
16616                 },
16617         },
16618         {
16619                 name:    "RSBSshiftLL",
16620                 auxType: auxInt32,
16621                 argLen:  2,
16622                 asm:     arm.ARSB,
16623                 reg: regInfo{
16624                         inputs: []inputInfo{
16625                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16626                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16627                         },
16628                         outputs: []outputInfo{
16629                                 {1, 0},
16630                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16631                         },
16632                 },
16633         },
16634         {
16635                 name:    "RSBSshiftRL",
16636                 auxType: auxInt32,
16637                 argLen:  2,
16638                 asm:     arm.ARSB,
16639                 reg: regInfo{
16640                         inputs: []inputInfo{
16641                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16642                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16643                         },
16644                         outputs: []outputInfo{
16645                                 {1, 0},
16646                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16647                         },
16648                 },
16649         },
16650         {
16651                 name:    "RSBSshiftRA",
16652                 auxType: auxInt32,
16653                 argLen:  2,
16654                 asm:     arm.ARSB,
16655                 reg: regInfo{
16656                         inputs: []inputInfo{
16657                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16658                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16659                         },
16660                         outputs: []outputInfo{
16661                                 {1, 0},
16662                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16663                         },
16664                 },
16665         },
16666         {
16667                 name:   "ADDshiftLLreg",
16668                 argLen: 3,
16669                 asm:    arm.AADD,
16670                 reg: regInfo{
16671                         inputs: []inputInfo{
16672                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16673                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16674                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16675                         },
16676                         outputs: []outputInfo{
16677                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16678                         },
16679                 },
16680         },
16681         {
16682                 name:   "ADDshiftRLreg",
16683                 argLen: 3,
16684                 asm:    arm.AADD,
16685                 reg: regInfo{
16686                         inputs: []inputInfo{
16687                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16688                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16689                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16690                         },
16691                         outputs: []outputInfo{
16692                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16693                         },
16694                 },
16695         },
16696         {
16697                 name:   "ADDshiftRAreg",
16698                 argLen: 3,
16699                 asm:    arm.AADD,
16700                 reg: regInfo{
16701                         inputs: []inputInfo{
16702                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16703                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16704                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16705                         },
16706                         outputs: []outputInfo{
16707                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16708                         },
16709                 },
16710         },
16711         {
16712                 name:   "SUBshiftLLreg",
16713                 argLen: 3,
16714                 asm:    arm.ASUB,
16715                 reg: regInfo{
16716                         inputs: []inputInfo{
16717                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16718                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16719                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16720                         },
16721                         outputs: []outputInfo{
16722                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16723                         },
16724                 },
16725         },
16726         {
16727                 name:   "SUBshiftRLreg",
16728                 argLen: 3,
16729                 asm:    arm.ASUB,
16730                 reg: regInfo{
16731                         inputs: []inputInfo{
16732                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16733                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16734                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16735                         },
16736                         outputs: []outputInfo{
16737                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16738                         },
16739                 },
16740         },
16741         {
16742                 name:   "SUBshiftRAreg",
16743                 argLen: 3,
16744                 asm:    arm.ASUB,
16745                 reg: regInfo{
16746                         inputs: []inputInfo{
16747                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16748                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16749                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16750                         },
16751                         outputs: []outputInfo{
16752                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16753                         },
16754                 },
16755         },
16756         {
16757                 name:   "RSBshiftLLreg",
16758                 argLen: 3,
16759                 asm:    arm.ARSB,
16760                 reg: regInfo{
16761                         inputs: []inputInfo{
16762                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16763                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16764                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16765                         },
16766                         outputs: []outputInfo{
16767                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16768                         },
16769                 },
16770         },
16771         {
16772                 name:   "RSBshiftRLreg",
16773                 argLen: 3,
16774                 asm:    arm.ARSB,
16775                 reg: regInfo{
16776                         inputs: []inputInfo{
16777                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16778                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16779                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16780                         },
16781                         outputs: []outputInfo{
16782                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16783                         },
16784                 },
16785         },
16786         {
16787                 name:   "RSBshiftRAreg",
16788                 argLen: 3,
16789                 asm:    arm.ARSB,
16790                 reg: regInfo{
16791                         inputs: []inputInfo{
16792                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16793                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16794                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16795                         },
16796                         outputs: []outputInfo{
16797                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16798                         },
16799                 },
16800         },
16801         {
16802                 name:   "ANDshiftLLreg",
16803                 argLen: 3,
16804                 asm:    arm.AAND,
16805                 reg: regInfo{
16806                         inputs: []inputInfo{
16807                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16808                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16809                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16810                         },
16811                         outputs: []outputInfo{
16812                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16813                         },
16814                 },
16815         },
16816         {
16817                 name:   "ANDshiftRLreg",
16818                 argLen: 3,
16819                 asm:    arm.AAND,
16820                 reg: regInfo{
16821                         inputs: []inputInfo{
16822                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16823                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16824                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16825                         },
16826                         outputs: []outputInfo{
16827                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16828                         },
16829                 },
16830         },
16831         {
16832                 name:   "ANDshiftRAreg",
16833                 argLen: 3,
16834                 asm:    arm.AAND,
16835                 reg: regInfo{
16836                         inputs: []inputInfo{
16837                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16838                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16839                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16840                         },
16841                         outputs: []outputInfo{
16842                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16843                         },
16844                 },
16845         },
16846         {
16847                 name:   "ORshiftLLreg",
16848                 argLen: 3,
16849                 asm:    arm.AORR,
16850                 reg: regInfo{
16851                         inputs: []inputInfo{
16852                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16853                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16854                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16855                         },
16856                         outputs: []outputInfo{
16857                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16858                         },
16859                 },
16860         },
16861         {
16862                 name:   "ORshiftRLreg",
16863                 argLen: 3,
16864                 asm:    arm.AORR,
16865                 reg: regInfo{
16866                         inputs: []inputInfo{
16867                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16868                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16869                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16870                         },
16871                         outputs: []outputInfo{
16872                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16873                         },
16874                 },
16875         },
16876         {
16877                 name:   "ORshiftRAreg",
16878                 argLen: 3,
16879                 asm:    arm.AORR,
16880                 reg: regInfo{
16881                         inputs: []inputInfo{
16882                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16883                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16884                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16885                         },
16886                         outputs: []outputInfo{
16887                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16888                         },
16889                 },
16890         },
16891         {
16892                 name:   "XORshiftLLreg",
16893                 argLen: 3,
16894                 asm:    arm.AEOR,
16895                 reg: regInfo{
16896                         inputs: []inputInfo{
16897                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16898                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16899                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16900                         },
16901                         outputs: []outputInfo{
16902                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16903                         },
16904                 },
16905         },
16906         {
16907                 name:   "XORshiftRLreg",
16908                 argLen: 3,
16909                 asm:    arm.AEOR,
16910                 reg: regInfo{
16911                         inputs: []inputInfo{
16912                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16913                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16914                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16915                         },
16916                         outputs: []outputInfo{
16917                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16918                         },
16919                 },
16920         },
16921         {
16922                 name:   "XORshiftRAreg",
16923                 argLen: 3,
16924                 asm:    arm.AEOR,
16925                 reg: regInfo{
16926                         inputs: []inputInfo{
16927                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16928                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16929                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16930                         },
16931                         outputs: []outputInfo{
16932                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16933                         },
16934                 },
16935         },
16936         {
16937                 name:   "BICshiftLLreg",
16938                 argLen: 3,
16939                 asm:    arm.ABIC,
16940                 reg: regInfo{
16941                         inputs: []inputInfo{
16942                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16943                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16944                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16945                         },
16946                         outputs: []outputInfo{
16947                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16948                         },
16949                 },
16950         },
16951         {
16952                 name:   "BICshiftRLreg",
16953                 argLen: 3,
16954                 asm:    arm.ABIC,
16955                 reg: regInfo{
16956                         inputs: []inputInfo{
16957                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16958                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16959                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16960                         },
16961                         outputs: []outputInfo{
16962                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16963                         },
16964                 },
16965         },
16966         {
16967                 name:   "BICshiftRAreg",
16968                 argLen: 3,
16969                 asm:    arm.ABIC,
16970                 reg: regInfo{
16971                         inputs: []inputInfo{
16972                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16973                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16974                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16975                         },
16976                         outputs: []outputInfo{
16977                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16978                         },
16979                 },
16980         },
16981         {
16982                 name:   "MVNshiftLLreg",
16983                 argLen: 2,
16984                 asm:    arm.AMVN,
16985                 reg: regInfo{
16986                         inputs: []inputInfo{
16987                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16988                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16989                         },
16990                         outputs: []outputInfo{
16991                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16992                         },
16993                 },
16994         },
16995         {
16996                 name:   "MVNshiftRLreg",
16997                 argLen: 2,
16998                 asm:    arm.AMVN,
16999                 reg: regInfo{
17000                         inputs: []inputInfo{
17001                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17002                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17003                         },
17004                         outputs: []outputInfo{
17005                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17006                         },
17007                 },
17008         },
17009         {
17010                 name:   "MVNshiftRAreg",
17011                 argLen: 2,
17012                 asm:    arm.AMVN,
17013                 reg: regInfo{
17014                         inputs: []inputInfo{
17015                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17016                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17017                         },
17018                         outputs: []outputInfo{
17019                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17020                         },
17021                 },
17022         },
17023         {
17024                 name:   "ADCshiftLLreg",
17025                 argLen: 4,
17026                 asm:    arm.AADC,
17027                 reg: regInfo{
17028                         inputs: []inputInfo{
17029                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17030                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17031                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17032                         },
17033                         outputs: []outputInfo{
17034                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17035                         },
17036                 },
17037         },
17038         {
17039                 name:   "ADCshiftRLreg",
17040                 argLen: 4,
17041                 asm:    arm.AADC,
17042                 reg: regInfo{
17043                         inputs: []inputInfo{
17044                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17045                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17046                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17047                         },
17048                         outputs: []outputInfo{
17049                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17050                         },
17051                 },
17052         },
17053         {
17054                 name:   "ADCshiftRAreg",
17055                 argLen: 4,
17056                 asm:    arm.AADC,
17057                 reg: regInfo{
17058                         inputs: []inputInfo{
17059                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17060                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17061                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17062                         },
17063                         outputs: []outputInfo{
17064                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17065                         },
17066                 },
17067         },
17068         {
17069                 name:   "SBCshiftLLreg",
17070                 argLen: 4,
17071                 asm:    arm.ASBC,
17072                 reg: regInfo{
17073                         inputs: []inputInfo{
17074                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17075                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17076                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17077                         },
17078                         outputs: []outputInfo{
17079                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17080                         },
17081                 },
17082         },
17083         {
17084                 name:   "SBCshiftRLreg",
17085                 argLen: 4,
17086                 asm:    arm.ASBC,
17087                 reg: regInfo{
17088                         inputs: []inputInfo{
17089                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17090                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17091                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17092                         },
17093                         outputs: []outputInfo{
17094                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17095                         },
17096                 },
17097         },
17098         {
17099                 name:   "SBCshiftRAreg",
17100                 argLen: 4,
17101                 asm:    arm.ASBC,
17102                 reg: regInfo{
17103                         inputs: []inputInfo{
17104                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17105                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17106                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17107                         },
17108                         outputs: []outputInfo{
17109                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17110                         },
17111                 },
17112         },
17113         {
17114                 name:   "RSCshiftLLreg",
17115                 argLen: 4,
17116                 asm:    arm.ARSC,
17117                 reg: regInfo{
17118                         inputs: []inputInfo{
17119                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17120                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17121                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17122                         },
17123                         outputs: []outputInfo{
17124                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17125                         },
17126                 },
17127         },
17128         {
17129                 name:   "RSCshiftRLreg",
17130                 argLen: 4,
17131                 asm:    arm.ARSC,
17132                 reg: regInfo{
17133                         inputs: []inputInfo{
17134                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17135                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17136                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17137                         },
17138                         outputs: []outputInfo{
17139                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17140                         },
17141                 },
17142         },
17143         {
17144                 name:   "RSCshiftRAreg",
17145                 argLen: 4,
17146                 asm:    arm.ARSC,
17147                 reg: regInfo{
17148                         inputs: []inputInfo{
17149                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17150                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17151                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17152                         },
17153                         outputs: []outputInfo{
17154                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17155                         },
17156                 },
17157         },
17158         {
17159                 name:   "ADDSshiftLLreg",
17160                 argLen: 3,
17161                 asm:    arm.AADD,
17162                 reg: regInfo{
17163                         inputs: []inputInfo{
17164                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17165                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17166                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17167                         },
17168                         outputs: []outputInfo{
17169                                 {1, 0},
17170                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17171                         },
17172                 },
17173         },
17174         {
17175                 name:   "ADDSshiftRLreg",
17176                 argLen: 3,
17177                 asm:    arm.AADD,
17178                 reg: regInfo{
17179                         inputs: []inputInfo{
17180                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17181                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17182                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17183                         },
17184                         outputs: []outputInfo{
17185                                 {1, 0},
17186                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17187                         },
17188                 },
17189         },
17190         {
17191                 name:   "ADDSshiftRAreg",
17192                 argLen: 3,
17193                 asm:    arm.AADD,
17194                 reg: regInfo{
17195                         inputs: []inputInfo{
17196                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17197                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17198                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17199                         },
17200                         outputs: []outputInfo{
17201                                 {1, 0},
17202                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17203                         },
17204                 },
17205         },
17206         {
17207                 name:   "SUBSshiftLLreg",
17208                 argLen: 3,
17209                 asm:    arm.ASUB,
17210                 reg: regInfo{
17211                         inputs: []inputInfo{
17212                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17213                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17214                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17215                         },
17216                         outputs: []outputInfo{
17217                                 {1, 0},
17218                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17219                         },
17220                 },
17221         },
17222         {
17223                 name:   "SUBSshiftRLreg",
17224                 argLen: 3,
17225                 asm:    arm.ASUB,
17226                 reg: regInfo{
17227                         inputs: []inputInfo{
17228                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17229                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17230                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17231                         },
17232                         outputs: []outputInfo{
17233                                 {1, 0},
17234                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17235                         },
17236                 },
17237         },
17238         {
17239                 name:   "SUBSshiftRAreg",
17240                 argLen: 3,
17241                 asm:    arm.ASUB,
17242                 reg: regInfo{
17243                         inputs: []inputInfo{
17244                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17245                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17246                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17247                         },
17248                         outputs: []outputInfo{
17249                                 {1, 0},
17250                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17251                         },
17252                 },
17253         },
17254         {
17255                 name:   "RSBSshiftLLreg",
17256                 argLen: 3,
17257                 asm:    arm.ARSB,
17258                 reg: regInfo{
17259                         inputs: []inputInfo{
17260                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17261                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17262                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17263                         },
17264                         outputs: []outputInfo{
17265                                 {1, 0},
17266                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17267                         },
17268                 },
17269         },
17270         {
17271                 name:   "RSBSshiftRLreg",
17272                 argLen: 3,
17273                 asm:    arm.ARSB,
17274                 reg: regInfo{
17275                         inputs: []inputInfo{
17276                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17277                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17278                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17279                         },
17280                         outputs: []outputInfo{
17281                                 {1, 0},
17282                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17283                         },
17284                 },
17285         },
17286         {
17287                 name:   "RSBSshiftRAreg",
17288                 argLen: 3,
17289                 asm:    arm.ARSB,
17290                 reg: regInfo{
17291                         inputs: []inputInfo{
17292                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17293                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17294                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17295                         },
17296                         outputs: []outputInfo{
17297                                 {1, 0},
17298                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17299                         },
17300                 },
17301         },
17302         {
17303                 name:   "CMP",
17304                 argLen: 2,
17305                 asm:    arm.ACMP,
17306                 reg: regInfo{
17307                         inputs: []inputInfo{
17308                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17309                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17310                         },
17311                 },
17312         },
17313         {
17314                 name:    "CMPconst",
17315                 auxType: auxInt32,
17316                 argLen:  1,
17317                 asm:     arm.ACMP,
17318                 reg: regInfo{
17319                         inputs: []inputInfo{
17320                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17321                         },
17322                 },
17323         },
17324         {
17325                 name:        "CMN",
17326                 argLen:      2,
17327                 commutative: true,
17328                 asm:         arm.ACMN,
17329                 reg: regInfo{
17330                         inputs: []inputInfo{
17331                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17332                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17333                         },
17334                 },
17335         },
17336         {
17337                 name:    "CMNconst",
17338                 auxType: auxInt32,
17339                 argLen:  1,
17340                 asm:     arm.ACMN,
17341                 reg: regInfo{
17342                         inputs: []inputInfo{
17343                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17344                         },
17345                 },
17346         },
17347         {
17348                 name:        "TST",
17349                 argLen:      2,
17350                 commutative: true,
17351                 asm:         arm.ATST,
17352                 reg: regInfo{
17353                         inputs: []inputInfo{
17354                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17355                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17356                         },
17357                 },
17358         },
17359         {
17360                 name:    "TSTconst",
17361                 auxType: auxInt32,
17362                 argLen:  1,
17363                 asm:     arm.ATST,
17364                 reg: regInfo{
17365                         inputs: []inputInfo{
17366                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17367                         },
17368                 },
17369         },
17370         {
17371                 name:        "TEQ",
17372                 argLen:      2,
17373                 commutative: true,
17374                 asm:         arm.ATEQ,
17375                 reg: regInfo{
17376                         inputs: []inputInfo{
17377                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17378                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17379                         },
17380                 },
17381         },
17382         {
17383                 name:    "TEQconst",
17384                 auxType: auxInt32,
17385                 argLen:  1,
17386                 asm:     arm.ATEQ,
17387                 reg: regInfo{
17388                         inputs: []inputInfo{
17389                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17390                         },
17391                 },
17392         },
17393         {
17394                 name:   "CMPF",
17395                 argLen: 2,
17396                 asm:    arm.ACMPF,
17397                 reg: regInfo{
17398                         inputs: []inputInfo{
17399                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17400                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17401                         },
17402                 },
17403         },
17404         {
17405                 name:   "CMPD",
17406                 argLen: 2,
17407                 asm:    arm.ACMPD,
17408                 reg: regInfo{
17409                         inputs: []inputInfo{
17410                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17411                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17412                         },
17413                 },
17414         },
17415         {
17416                 name:    "CMPshiftLL",
17417                 auxType: auxInt32,
17418                 argLen:  2,
17419                 asm:     arm.ACMP,
17420                 reg: regInfo{
17421                         inputs: []inputInfo{
17422                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17423                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17424                         },
17425                 },
17426         },
17427         {
17428                 name:    "CMPshiftRL",
17429                 auxType: auxInt32,
17430                 argLen:  2,
17431                 asm:     arm.ACMP,
17432                 reg: regInfo{
17433                         inputs: []inputInfo{
17434                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17435                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17436                         },
17437                 },
17438         },
17439         {
17440                 name:    "CMPshiftRA",
17441                 auxType: auxInt32,
17442                 argLen:  2,
17443                 asm:     arm.ACMP,
17444                 reg: regInfo{
17445                         inputs: []inputInfo{
17446                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17447                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17448                         },
17449                 },
17450         },
17451         {
17452                 name:    "CMNshiftLL",
17453                 auxType: auxInt32,
17454                 argLen:  2,
17455                 asm:     arm.ACMN,
17456                 reg: regInfo{
17457                         inputs: []inputInfo{
17458                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17459                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17460                         },
17461                 },
17462         },
17463         {
17464                 name:    "CMNshiftRL",
17465                 auxType: auxInt32,
17466                 argLen:  2,
17467                 asm:     arm.ACMN,
17468                 reg: regInfo{
17469                         inputs: []inputInfo{
17470                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17471                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17472                         },
17473                 },
17474         },
17475         {
17476                 name:    "CMNshiftRA",
17477                 auxType: auxInt32,
17478                 argLen:  2,
17479                 asm:     arm.ACMN,
17480                 reg: regInfo{
17481                         inputs: []inputInfo{
17482                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17483                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17484                         },
17485                 },
17486         },
17487         {
17488                 name:    "TSTshiftLL",
17489                 auxType: auxInt32,
17490                 argLen:  2,
17491                 asm:     arm.ATST,
17492                 reg: regInfo{
17493                         inputs: []inputInfo{
17494                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17495                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17496                         },
17497                 },
17498         },
17499         {
17500                 name:    "TSTshiftRL",
17501                 auxType: auxInt32,
17502                 argLen:  2,
17503                 asm:     arm.ATST,
17504                 reg: regInfo{
17505                         inputs: []inputInfo{
17506                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17507                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17508                         },
17509                 },
17510         },
17511         {
17512                 name:    "TSTshiftRA",
17513                 auxType: auxInt32,
17514                 argLen:  2,
17515                 asm:     arm.ATST,
17516                 reg: regInfo{
17517                         inputs: []inputInfo{
17518                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17519                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17520                         },
17521                 },
17522         },
17523         {
17524                 name:    "TEQshiftLL",
17525                 auxType: auxInt32,
17526                 argLen:  2,
17527                 asm:     arm.ATEQ,
17528                 reg: regInfo{
17529                         inputs: []inputInfo{
17530                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17531                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17532                         },
17533                 },
17534         },
17535         {
17536                 name:    "TEQshiftRL",
17537                 auxType: auxInt32,
17538                 argLen:  2,
17539                 asm:     arm.ATEQ,
17540                 reg: regInfo{
17541                         inputs: []inputInfo{
17542                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17543                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17544                         },
17545                 },
17546         },
17547         {
17548                 name:    "TEQshiftRA",
17549                 auxType: auxInt32,
17550                 argLen:  2,
17551                 asm:     arm.ATEQ,
17552                 reg: regInfo{
17553                         inputs: []inputInfo{
17554                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17555                                 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17556                         },
17557                 },
17558         },
17559         {
17560                 name:   "CMPshiftLLreg",
17561                 argLen: 3,
17562                 asm:    arm.ACMP,
17563                 reg: regInfo{
17564                         inputs: []inputInfo{
17565                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17566                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17567                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17568                         },
17569                 },
17570         },
17571         {
17572                 name:   "CMPshiftRLreg",
17573                 argLen: 3,
17574                 asm:    arm.ACMP,
17575                 reg: regInfo{
17576                         inputs: []inputInfo{
17577                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17578                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17579                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17580                         },
17581                 },
17582         },
17583         {
17584                 name:   "CMPshiftRAreg",
17585                 argLen: 3,
17586                 asm:    arm.ACMP,
17587                 reg: regInfo{
17588                         inputs: []inputInfo{
17589                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17590                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17591                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17592                         },
17593                 },
17594         },
17595         {
17596                 name:   "CMNshiftLLreg",
17597                 argLen: 3,
17598                 asm:    arm.ACMN,
17599                 reg: regInfo{
17600                         inputs: []inputInfo{
17601                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17602                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17603                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17604                         },
17605                 },
17606         },
17607         {
17608                 name:   "CMNshiftRLreg",
17609                 argLen: 3,
17610                 asm:    arm.ACMN,
17611                 reg: regInfo{
17612                         inputs: []inputInfo{
17613                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17614                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17615                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17616                         },
17617                 },
17618         },
17619         {
17620                 name:   "CMNshiftRAreg",
17621                 argLen: 3,
17622                 asm:    arm.ACMN,
17623                 reg: regInfo{
17624                         inputs: []inputInfo{
17625                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17626                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17627                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17628                         },
17629                 },
17630         },
17631         {
17632                 name:   "TSTshiftLLreg",
17633                 argLen: 3,
17634                 asm:    arm.ATST,
17635                 reg: regInfo{
17636                         inputs: []inputInfo{
17637                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17638                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17639                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17640                         },
17641                 },
17642         },
17643         {
17644                 name:   "TSTshiftRLreg",
17645                 argLen: 3,
17646                 asm:    arm.ATST,
17647                 reg: regInfo{
17648                         inputs: []inputInfo{
17649                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17650                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17651                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17652                         },
17653                 },
17654         },
17655         {
17656                 name:   "TSTshiftRAreg",
17657                 argLen: 3,
17658                 asm:    arm.ATST,
17659                 reg: regInfo{
17660                         inputs: []inputInfo{
17661                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17662                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17663                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17664                         },
17665                 },
17666         },
17667         {
17668                 name:   "TEQshiftLLreg",
17669                 argLen: 3,
17670                 asm:    arm.ATEQ,
17671                 reg: regInfo{
17672                         inputs: []inputInfo{
17673                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17674                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17675                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17676                         },
17677                 },
17678         },
17679         {
17680                 name:   "TEQshiftRLreg",
17681                 argLen: 3,
17682                 asm:    arm.ATEQ,
17683                 reg: regInfo{
17684                         inputs: []inputInfo{
17685                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17686                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17687                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17688                         },
17689                 },
17690         },
17691         {
17692                 name:   "TEQshiftRAreg",
17693                 argLen: 3,
17694                 asm:    arm.ATEQ,
17695                 reg: regInfo{
17696                         inputs: []inputInfo{
17697                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17698                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17699                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17700                         },
17701                 },
17702         },
17703         {
17704                 name:   "CMPF0",
17705                 argLen: 1,
17706                 asm:    arm.ACMPF,
17707                 reg: regInfo{
17708                         inputs: []inputInfo{
17709                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17710                         },
17711                 },
17712         },
17713         {
17714                 name:   "CMPD0",
17715                 argLen: 1,
17716                 asm:    arm.ACMPD,
17717                 reg: regInfo{
17718                         inputs: []inputInfo{
17719                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17720                         },
17721                 },
17722         },
17723         {
17724                 name:              "MOVWconst",
17725                 auxType:           auxInt32,
17726                 argLen:            0,
17727                 rematerializeable: true,
17728                 asm:               arm.AMOVW,
17729                 reg: regInfo{
17730                         outputs: []outputInfo{
17731                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17732                         },
17733                 },
17734         },
17735         {
17736                 name:              "MOVFconst",
17737                 auxType:           auxFloat64,
17738                 argLen:            0,
17739                 rematerializeable: true,
17740                 asm:               arm.AMOVF,
17741                 reg: regInfo{
17742                         outputs: []outputInfo{
17743                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17744                         },
17745                 },
17746         },
17747         {
17748                 name:              "MOVDconst",
17749                 auxType:           auxFloat64,
17750                 argLen:            0,
17751                 rematerializeable: true,
17752                 asm:               arm.AMOVD,
17753                 reg: regInfo{
17754                         outputs: []outputInfo{
17755                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17756                         },
17757                 },
17758         },
17759         {
17760                 name:              "MOVWaddr",
17761                 auxType:           auxSymOff,
17762                 argLen:            1,
17763                 rematerializeable: true,
17764                 symEffect:         SymAddr,
17765                 asm:               arm.AMOVW,
17766                 reg: regInfo{
17767                         inputs: []inputInfo{
17768                                 {0, 4294975488}, // SP SB
17769                         },
17770                         outputs: []outputInfo{
17771                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17772                         },
17773                 },
17774         },
17775         {
17776                 name:           "MOVBload",
17777                 auxType:        auxSymOff,
17778                 argLen:         2,
17779                 faultOnNilArg0: true,
17780                 symEffect:      SymRead,
17781                 asm:            arm.AMOVB,
17782                 reg: regInfo{
17783                         inputs: []inputInfo{
17784                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17785                         },
17786                         outputs: []outputInfo{
17787                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17788                         },
17789                 },
17790         },
17791         {
17792                 name:           "MOVBUload",
17793                 auxType:        auxSymOff,
17794                 argLen:         2,
17795                 faultOnNilArg0: true,
17796                 symEffect:      SymRead,
17797                 asm:            arm.AMOVBU,
17798                 reg: regInfo{
17799                         inputs: []inputInfo{
17800                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17801                         },
17802                         outputs: []outputInfo{
17803                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17804                         },
17805                 },
17806         },
17807         {
17808                 name:           "MOVHload",
17809                 auxType:        auxSymOff,
17810                 argLen:         2,
17811                 faultOnNilArg0: true,
17812                 symEffect:      SymRead,
17813                 asm:            arm.AMOVH,
17814                 reg: regInfo{
17815                         inputs: []inputInfo{
17816                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17817                         },
17818                         outputs: []outputInfo{
17819                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17820                         },
17821                 },
17822         },
17823         {
17824                 name:           "MOVHUload",
17825                 auxType:        auxSymOff,
17826                 argLen:         2,
17827                 faultOnNilArg0: true,
17828                 symEffect:      SymRead,
17829                 asm:            arm.AMOVHU,
17830                 reg: regInfo{
17831                         inputs: []inputInfo{
17832                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17833                         },
17834                         outputs: []outputInfo{
17835                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17836                         },
17837                 },
17838         },
17839         {
17840                 name:           "MOVWload",
17841                 auxType:        auxSymOff,
17842                 argLen:         2,
17843                 faultOnNilArg0: true,
17844                 symEffect:      SymRead,
17845                 asm:            arm.AMOVW,
17846                 reg: regInfo{
17847                         inputs: []inputInfo{
17848                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17849                         },
17850                         outputs: []outputInfo{
17851                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17852                         },
17853                 },
17854         },
17855         {
17856                 name:           "MOVFload",
17857                 auxType:        auxSymOff,
17858                 argLen:         2,
17859                 faultOnNilArg0: true,
17860                 symEffect:      SymRead,
17861                 asm:            arm.AMOVF,
17862                 reg: regInfo{
17863                         inputs: []inputInfo{
17864                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17865                         },
17866                         outputs: []outputInfo{
17867                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17868                         },
17869                 },
17870         },
17871         {
17872                 name:           "MOVDload",
17873                 auxType:        auxSymOff,
17874                 argLen:         2,
17875                 faultOnNilArg0: true,
17876                 symEffect:      SymRead,
17877                 asm:            arm.AMOVD,
17878                 reg: regInfo{
17879                         inputs: []inputInfo{
17880                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17881                         },
17882                         outputs: []outputInfo{
17883                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17884                         },
17885                 },
17886         },
17887         {
17888                 name:           "MOVBstore",
17889                 auxType:        auxSymOff,
17890                 argLen:         3,
17891                 faultOnNilArg0: true,
17892                 symEffect:      SymWrite,
17893                 asm:            arm.AMOVB,
17894                 reg: regInfo{
17895                         inputs: []inputInfo{
17896                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17897                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17898                         },
17899                 },
17900         },
17901         {
17902                 name:           "MOVHstore",
17903                 auxType:        auxSymOff,
17904                 argLen:         3,
17905                 faultOnNilArg0: true,
17906                 symEffect:      SymWrite,
17907                 asm:            arm.AMOVH,
17908                 reg: regInfo{
17909                         inputs: []inputInfo{
17910                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17911                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17912                         },
17913                 },
17914         },
17915         {
17916                 name:           "MOVWstore",
17917                 auxType:        auxSymOff,
17918                 argLen:         3,
17919                 faultOnNilArg0: true,
17920                 symEffect:      SymWrite,
17921                 asm:            arm.AMOVW,
17922                 reg: regInfo{
17923                         inputs: []inputInfo{
17924                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17925                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17926                         },
17927                 },
17928         },
17929         {
17930                 name:           "MOVFstore",
17931                 auxType:        auxSymOff,
17932                 argLen:         3,
17933                 faultOnNilArg0: true,
17934                 symEffect:      SymWrite,
17935                 asm:            arm.AMOVF,
17936                 reg: regInfo{
17937                         inputs: []inputInfo{
17938                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17939                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17940                         },
17941                 },
17942         },
17943         {
17944                 name:           "MOVDstore",
17945                 auxType:        auxSymOff,
17946                 argLen:         3,
17947                 faultOnNilArg0: true,
17948                 symEffect:      SymWrite,
17949                 asm:            arm.AMOVD,
17950                 reg: regInfo{
17951                         inputs: []inputInfo{
17952                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17953                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17954                         },
17955                 },
17956         },
17957         {
17958                 name:   "MOVWloadidx",
17959                 argLen: 3,
17960                 asm:    arm.AMOVW,
17961                 reg: regInfo{
17962                         inputs: []inputInfo{
17963                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17964                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17965                         },
17966                         outputs: []outputInfo{
17967                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17968                         },
17969                 },
17970         },
17971         {
17972                 name:    "MOVWloadshiftLL",
17973                 auxType: auxInt32,
17974                 argLen:  3,
17975                 asm:     arm.AMOVW,
17976                 reg: regInfo{
17977                         inputs: []inputInfo{
17978                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17979                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17980                         },
17981                         outputs: []outputInfo{
17982                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17983                         },
17984                 },
17985         },
17986         {
17987                 name:    "MOVWloadshiftRL",
17988                 auxType: auxInt32,
17989                 argLen:  3,
17990                 asm:     arm.AMOVW,
17991                 reg: regInfo{
17992                         inputs: []inputInfo{
17993                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17994                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
17995                         },
17996                         outputs: []outputInfo{
17997                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17998                         },
17999                 },
18000         },
18001         {
18002                 name:    "MOVWloadshiftRA",
18003                 auxType: auxInt32,
18004                 argLen:  3,
18005                 asm:     arm.AMOVW,
18006                 reg: regInfo{
18007                         inputs: []inputInfo{
18008                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18009                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18010                         },
18011                         outputs: []outputInfo{
18012                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18013                         },
18014                 },
18015         },
18016         {
18017                 name:   "MOVBUloadidx",
18018                 argLen: 3,
18019                 asm:    arm.AMOVBU,
18020                 reg: regInfo{
18021                         inputs: []inputInfo{
18022                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18023                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18024                         },
18025                         outputs: []outputInfo{
18026                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18027                         },
18028                 },
18029         },
18030         {
18031                 name:   "MOVBloadidx",
18032                 argLen: 3,
18033                 asm:    arm.AMOVB,
18034                 reg: regInfo{
18035                         inputs: []inputInfo{
18036                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18037                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18038                         },
18039                         outputs: []outputInfo{
18040                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18041                         },
18042                 },
18043         },
18044         {
18045                 name:   "MOVHUloadidx",
18046                 argLen: 3,
18047                 asm:    arm.AMOVHU,
18048                 reg: regInfo{
18049                         inputs: []inputInfo{
18050                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18051                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18052                         },
18053                         outputs: []outputInfo{
18054                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18055                         },
18056                 },
18057         },
18058         {
18059                 name:   "MOVHloadidx",
18060                 argLen: 3,
18061                 asm:    arm.AMOVH,
18062                 reg: regInfo{
18063                         inputs: []inputInfo{
18064                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18065                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18066                         },
18067                         outputs: []outputInfo{
18068                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18069                         },
18070                 },
18071         },
18072         {
18073                 name:   "MOVWstoreidx",
18074                 argLen: 4,
18075                 asm:    arm.AMOVW,
18076                 reg: regInfo{
18077                         inputs: []inputInfo{
18078                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18079                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18080                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18081                         },
18082                 },
18083         },
18084         {
18085                 name:    "MOVWstoreshiftLL",
18086                 auxType: auxInt32,
18087                 argLen:  4,
18088                 asm:     arm.AMOVW,
18089                 reg: regInfo{
18090                         inputs: []inputInfo{
18091                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18092                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18093                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18094                         },
18095                 },
18096         },
18097         {
18098                 name:    "MOVWstoreshiftRL",
18099                 auxType: auxInt32,
18100                 argLen:  4,
18101                 asm:     arm.AMOVW,
18102                 reg: regInfo{
18103                         inputs: []inputInfo{
18104                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18105                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18106                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18107                         },
18108                 },
18109         },
18110         {
18111                 name:    "MOVWstoreshiftRA",
18112                 auxType: auxInt32,
18113                 argLen:  4,
18114                 asm:     arm.AMOVW,
18115                 reg: regInfo{
18116                         inputs: []inputInfo{
18117                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18118                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18119                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18120                         },
18121                 },
18122         },
18123         {
18124                 name:   "MOVBstoreidx",
18125                 argLen: 4,
18126                 asm:    arm.AMOVB,
18127                 reg: regInfo{
18128                         inputs: []inputInfo{
18129                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18130                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18131                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18132                         },
18133                 },
18134         },
18135         {
18136                 name:   "MOVHstoreidx",
18137                 argLen: 4,
18138                 asm:    arm.AMOVH,
18139                 reg: regInfo{
18140                         inputs: []inputInfo{
18141                                 {1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18142                                 {2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18143                                 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
18144                         },
18145                 },
18146         },
18147         {
18148                 name:   "MOVBreg",
18149                 argLen: 1,
18150                 asm:    arm.AMOVBS,
18151                 reg: regInfo{
18152                         inputs: []inputInfo{
18153                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18154                         },
18155                         outputs: []outputInfo{
18156                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18157                         },
18158                 },
18159         },
18160         {
18161                 name:   "MOVBUreg",
18162                 argLen: 1,
18163                 asm:    arm.AMOVBU,
18164                 reg: regInfo{
18165                         inputs: []inputInfo{
18166                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18167                         },
18168                         outputs: []outputInfo{
18169                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18170                         },
18171                 },
18172         },
18173         {
18174                 name:   "MOVHreg",
18175                 argLen: 1,
18176                 asm:    arm.AMOVHS,
18177                 reg: regInfo{
18178                         inputs: []inputInfo{
18179                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18180                         },
18181                         outputs: []outputInfo{
18182                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18183                         },
18184                 },
18185         },
18186         {
18187                 name:   "MOVHUreg",
18188                 argLen: 1,
18189                 asm:    arm.AMOVHU,
18190                 reg: regInfo{
18191                         inputs: []inputInfo{
18192                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18193                         },
18194                         outputs: []outputInfo{
18195                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18196                         },
18197                 },
18198         },
18199         {
18200                 name:   "MOVWreg",
18201                 argLen: 1,
18202                 asm:    arm.AMOVW,
18203                 reg: regInfo{
18204                         inputs: []inputInfo{
18205                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18206                         },
18207                         outputs: []outputInfo{
18208                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18209                         },
18210                 },
18211         },
18212         {
18213                 name:         "MOVWnop",
18214                 argLen:       1,
18215                 resultInArg0: true,
18216                 reg: regInfo{
18217                         inputs: []inputInfo{
18218                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18219                         },
18220                         outputs: []outputInfo{
18221                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18222                         },
18223                 },
18224         },
18225         {
18226                 name:   "MOVWF",
18227                 argLen: 1,
18228                 asm:    arm.AMOVWF,
18229                 reg: regInfo{
18230                         inputs: []inputInfo{
18231                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18232                         },
18233                         clobbers: 2147483648, // F15
18234                         outputs: []outputInfo{
18235                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18236                         },
18237                 },
18238         },
18239         {
18240                 name:   "MOVWD",
18241                 argLen: 1,
18242                 asm:    arm.AMOVWD,
18243                 reg: regInfo{
18244                         inputs: []inputInfo{
18245                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18246                         },
18247                         clobbers: 2147483648, // F15
18248                         outputs: []outputInfo{
18249                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18250                         },
18251                 },
18252         },
18253         {
18254                 name:   "MOVWUF",
18255                 argLen: 1,
18256                 asm:    arm.AMOVWF,
18257                 reg: regInfo{
18258                         inputs: []inputInfo{
18259                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18260                         },
18261                         clobbers: 2147483648, // F15
18262                         outputs: []outputInfo{
18263                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18264                         },
18265                 },
18266         },
18267         {
18268                 name:   "MOVWUD",
18269                 argLen: 1,
18270                 asm:    arm.AMOVWD,
18271                 reg: regInfo{
18272                         inputs: []inputInfo{
18273                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18274                         },
18275                         clobbers: 2147483648, // F15
18276                         outputs: []outputInfo{
18277                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18278                         },
18279                 },
18280         },
18281         {
18282                 name:   "MOVFW",
18283                 argLen: 1,
18284                 asm:    arm.AMOVFW,
18285                 reg: regInfo{
18286                         inputs: []inputInfo{
18287                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18288                         },
18289                         clobbers: 2147483648, // F15
18290                         outputs: []outputInfo{
18291                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18292                         },
18293                 },
18294         },
18295         {
18296                 name:   "MOVDW",
18297                 argLen: 1,
18298                 asm:    arm.AMOVDW,
18299                 reg: regInfo{
18300                         inputs: []inputInfo{
18301                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18302                         },
18303                         clobbers: 2147483648, // F15
18304                         outputs: []outputInfo{
18305                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18306                         },
18307                 },
18308         },
18309         {
18310                 name:   "MOVFWU",
18311                 argLen: 1,
18312                 asm:    arm.AMOVFW,
18313                 reg: regInfo{
18314                         inputs: []inputInfo{
18315                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18316                         },
18317                         clobbers: 2147483648, // F15
18318                         outputs: []outputInfo{
18319                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18320                         },
18321                 },
18322         },
18323         {
18324                 name:   "MOVDWU",
18325                 argLen: 1,
18326                 asm:    arm.AMOVDW,
18327                 reg: regInfo{
18328                         inputs: []inputInfo{
18329                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18330                         },
18331                         clobbers: 2147483648, // F15
18332                         outputs: []outputInfo{
18333                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18334                         },
18335                 },
18336         },
18337         {
18338                 name:   "MOVFD",
18339                 argLen: 1,
18340                 asm:    arm.AMOVFD,
18341                 reg: regInfo{
18342                         inputs: []inputInfo{
18343                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18344                         },
18345                         outputs: []outputInfo{
18346                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18347                         },
18348                 },
18349         },
18350         {
18351                 name:   "MOVDF",
18352                 argLen: 1,
18353                 asm:    arm.AMOVDF,
18354                 reg: regInfo{
18355                         inputs: []inputInfo{
18356                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18357                         },
18358                         outputs: []outputInfo{
18359                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18360                         },
18361                 },
18362         },
18363         {
18364                 name:         "CMOVWHSconst",
18365                 auxType:      auxInt32,
18366                 argLen:       2,
18367                 resultInArg0: true,
18368                 asm:          arm.AMOVW,
18369                 reg: regInfo{
18370                         inputs: []inputInfo{
18371                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18372                         },
18373                         outputs: []outputInfo{
18374                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18375                         },
18376                 },
18377         },
18378         {
18379                 name:         "CMOVWLSconst",
18380                 auxType:      auxInt32,
18381                 argLen:       2,
18382                 resultInArg0: true,
18383                 asm:          arm.AMOVW,
18384                 reg: regInfo{
18385                         inputs: []inputInfo{
18386                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18387                         },
18388                         outputs: []outputInfo{
18389                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18390                         },
18391                 },
18392         },
18393         {
18394                 name:   "SRAcond",
18395                 argLen: 3,
18396                 asm:    arm.ASRA,
18397                 reg: regInfo{
18398                         inputs: []inputInfo{
18399                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18400                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18401                         },
18402                         outputs: []outputInfo{
18403                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18404                         },
18405                 },
18406         },
18407         {
18408                 name:         "CALLstatic",
18409                 auxType:      auxCallOff,
18410                 argLen:       1,
18411                 clobberFlags: true,
18412                 call:         true,
18413                 reg: regInfo{
18414                         clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18415                 },
18416         },
18417         {
18418                 name:         "CALLtail",
18419                 auxType:      auxCallOff,
18420                 argLen:       1,
18421                 clobberFlags: true,
18422                 call:         true,
18423                 tailCall:     true,
18424                 reg: regInfo{
18425                         clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18426                 },
18427         },
18428         {
18429                 name:         "CALLclosure",
18430                 auxType:      auxCallOff,
18431                 argLen:       3,
18432                 clobberFlags: true,
18433                 call:         true,
18434                 reg: regInfo{
18435                         inputs: []inputInfo{
18436                                 {1, 128},   // R7
18437                                 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
18438                         },
18439                         clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18440                 },
18441         },
18442         {
18443                 name:         "CALLinter",
18444                 auxType:      auxCallOff,
18445                 argLen:       2,
18446                 clobberFlags: true,
18447                 call:         true,
18448                 reg: regInfo{
18449                         inputs: []inputInfo{
18450                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18451                         },
18452                         clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18453                 },
18454         },
18455         {
18456                 name:           "LoweredNilCheck",
18457                 argLen:         2,
18458                 nilCheck:       true,
18459                 faultOnNilArg0: true,
18460                 reg: regInfo{
18461                         inputs: []inputInfo{
18462                                 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
18463                         },
18464                 },
18465         },
18466         {
18467                 name:   "Equal",
18468                 argLen: 1,
18469                 reg: regInfo{
18470                         outputs: []outputInfo{
18471                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18472                         },
18473                 },
18474         },
18475         {
18476                 name:   "NotEqual",
18477                 argLen: 1,
18478                 reg: regInfo{
18479                         outputs: []outputInfo{
18480                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18481                         },
18482                 },
18483         },
18484         {
18485                 name:   "LessThan",
18486                 argLen: 1,
18487                 reg: regInfo{
18488                         outputs: []outputInfo{
18489                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18490                         },
18491                 },
18492         },
18493         {
18494                 name:   "LessEqual",
18495                 argLen: 1,
18496                 reg: regInfo{
18497                         outputs: []outputInfo{
18498                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18499                         },
18500                 },
18501         },
18502         {
18503                 name:   "GreaterThan",
18504                 argLen: 1,
18505                 reg: regInfo{
18506                         outputs: []outputInfo{
18507                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18508                         },
18509                 },
18510         },
18511         {
18512                 name:   "GreaterEqual",
18513                 argLen: 1,
18514                 reg: regInfo{
18515                         outputs: []outputInfo{
18516                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18517                         },
18518                 },
18519         },
18520         {
18521                 name:   "LessThanU",
18522                 argLen: 1,
18523                 reg: regInfo{
18524                         outputs: []outputInfo{
18525                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18526                         },
18527                 },
18528         },
18529         {
18530                 name:   "LessEqualU",
18531                 argLen: 1,
18532                 reg: regInfo{
18533                         outputs: []outputInfo{
18534                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18535                         },
18536                 },
18537         },
18538         {
18539                 name:   "GreaterThanU",
18540                 argLen: 1,
18541                 reg: regInfo{
18542                         outputs: []outputInfo{
18543                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18544                         },
18545                 },
18546         },
18547         {
18548                 name:   "GreaterEqualU",
18549                 argLen: 1,
18550                 reg: regInfo{
18551                         outputs: []outputInfo{
18552                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18553                         },
18554                 },
18555         },
18556         {
18557                 name:           "DUFFZERO",
18558                 auxType:        auxInt64,
18559                 argLen:         3,
18560                 faultOnNilArg0: true,
18561                 reg: regInfo{
18562                         inputs: []inputInfo{
18563                                 {0, 2}, // R1
18564                                 {1, 1}, // R0
18565                         },
18566                         clobbers: 20482, // R1 R12 R14
18567                 },
18568         },
18569         {
18570                 name:           "DUFFCOPY",
18571                 auxType:        auxInt64,
18572                 argLen:         3,
18573                 faultOnNilArg0: true,
18574                 faultOnNilArg1: true,
18575                 reg: regInfo{
18576                         inputs: []inputInfo{
18577                                 {0, 4}, // R2
18578                                 {1, 2}, // R1
18579                         },
18580                         clobbers: 20487, // R0 R1 R2 R12 R14
18581                 },
18582         },
18583         {
18584                 name:           "LoweredZero",
18585                 auxType:        auxInt64,
18586                 argLen:         4,
18587                 clobberFlags:   true,
18588                 faultOnNilArg0: true,
18589                 reg: regInfo{
18590                         inputs: []inputInfo{
18591                                 {0, 2},     // R1
18592                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18593                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18594                         },
18595                         clobbers: 2, // R1
18596                 },
18597         },
18598         {
18599                 name:           "LoweredMove",
18600                 auxType:        auxInt64,
18601                 argLen:         4,
18602                 clobberFlags:   true,
18603                 faultOnNilArg0: true,
18604                 faultOnNilArg1: true,
18605                 reg: regInfo{
18606                         inputs: []inputInfo{
18607                                 {0, 4},     // R2
18608                                 {1, 2},     // R1
18609                                 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18610                         },
18611                         clobbers: 6, // R1 R2
18612                 },
18613         },
18614         {
18615                 name:      "LoweredGetClosurePtr",
18616                 argLen:    0,
18617                 zeroWidth: true,
18618                 reg: regInfo{
18619                         outputs: []outputInfo{
18620                                 {0, 128}, // R7
18621                         },
18622                 },
18623         },
18624         {
18625                 name:              "LoweredGetCallerSP",
18626                 argLen:            1,
18627                 rematerializeable: true,
18628                 reg: regInfo{
18629                         outputs: []outputInfo{
18630                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18631                         },
18632                 },
18633         },
18634         {
18635                 name:              "LoweredGetCallerPC",
18636                 argLen:            0,
18637                 rematerializeable: true,
18638                 reg: regInfo{
18639                         outputs: []outputInfo{
18640                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
18641                         },
18642                 },
18643         },
18644         {
18645                 name:    "LoweredPanicBoundsA",
18646                 auxType: auxInt64,
18647                 argLen:  3,
18648                 call:    true,
18649                 reg: regInfo{
18650                         inputs: []inputInfo{
18651                                 {0, 4}, // R2
18652                                 {1, 8}, // R3
18653                         },
18654                 },
18655         },
18656         {
18657                 name:    "LoweredPanicBoundsB",
18658                 auxType: auxInt64,
18659                 argLen:  3,
18660                 call:    true,
18661                 reg: regInfo{
18662                         inputs: []inputInfo{
18663                                 {0, 2}, // R1
18664                                 {1, 4}, // R2
18665                         },
18666                 },
18667         },
18668         {
18669                 name:    "LoweredPanicBoundsC",
18670                 auxType: auxInt64,
18671                 argLen:  3,
18672                 call:    true,
18673                 reg: regInfo{
18674                         inputs: []inputInfo{
18675                                 {0, 1}, // R0
18676                                 {1, 2}, // R1
18677                         },
18678                 },
18679         },
18680         {
18681                 name:    "LoweredPanicExtendA",
18682                 auxType: auxInt64,
18683                 argLen:  4,
18684                 call:    true,
18685                 reg: regInfo{
18686                         inputs: []inputInfo{
18687                                 {0, 16}, // R4
18688                                 {1, 4},  // R2
18689                                 {2, 8},  // R3
18690                         },
18691                 },
18692         },
18693         {
18694                 name:    "LoweredPanicExtendB",
18695                 auxType: auxInt64,
18696                 argLen:  4,
18697                 call:    true,
18698                 reg: regInfo{
18699                         inputs: []inputInfo{
18700                                 {0, 16}, // R4
18701                                 {1, 2},  // R1
18702                                 {2, 4},  // R2
18703                         },
18704                 },
18705         },
18706         {
18707                 name:    "LoweredPanicExtendC",
18708                 auxType: auxInt64,
18709                 argLen:  4,
18710                 call:    true,
18711                 reg: regInfo{
18712                         inputs: []inputInfo{
18713                                 {0, 16}, // R4
18714                                 {1, 1},  // R0
18715                                 {2, 2},  // R1
18716                         },
18717                 },
18718         },
18719         {
18720                 name:    "FlagConstant",
18721                 auxType: auxFlagConstant,
18722                 argLen:  0,
18723                 reg:     regInfo{},
18724         },
18725         {
18726                 name:   "InvertFlags",
18727                 argLen: 1,
18728                 reg:    regInfo{},
18729         },
18730         {
18731                 name:         "LoweredWB",
18732                 auxType:      auxInt64,
18733                 argLen:       1,
18734                 clobberFlags: true,
18735                 reg: regInfo{
18736                         clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
18737                         outputs: []outputInfo{
18738                                 {0, 256}, // R8
18739                         },
18740                 },
18741         },
18742
18743         {
18744                 name:        "ADCSflags",
18745                 argLen:      3,
18746                 commutative: true,
18747                 asm:         arm64.AADCS,
18748                 reg: regInfo{
18749                         inputs: []inputInfo{
18750                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18751                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18752                         },
18753                         outputs: []outputInfo{
18754                                 {1, 0},
18755                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18756                         },
18757                 },
18758         },
18759         {
18760                 name:   "ADCzerocarry",
18761                 argLen: 1,
18762                 asm:    arm64.AADC,
18763                 reg: regInfo{
18764                         outputs: []outputInfo{
18765                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18766                         },
18767                 },
18768         },
18769         {
18770                 name:        "ADD",
18771                 argLen:      2,
18772                 commutative: true,
18773                 asm:         arm64.AADD,
18774                 reg: regInfo{
18775                         inputs: []inputInfo{
18776                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18777                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18778                         },
18779                         outputs: []outputInfo{
18780                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18781                         },
18782                 },
18783         },
18784         {
18785                 name:    "ADDconst",
18786                 auxType: auxInt64,
18787                 argLen:  1,
18788                 asm:     arm64.AADD,
18789                 reg: regInfo{
18790                         inputs: []inputInfo{
18791                                 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
18792                         },
18793                         outputs: []outputInfo{
18794                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18795                         },
18796                 },
18797         },
18798         {
18799                 name:    "ADDSconstflags",
18800                 auxType: auxInt64,
18801                 argLen:  1,
18802                 asm:     arm64.AADDS,
18803                 reg: regInfo{
18804                         inputs: []inputInfo{
18805                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18806                         },
18807                         outputs: []outputInfo{
18808                                 {1, 0},
18809                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18810                         },
18811                 },
18812         },
18813         {
18814                 name:        "ADDSflags",
18815                 argLen:      2,
18816                 commutative: true,
18817                 asm:         arm64.AADDS,
18818                 reg: regInfo{
18819                         inputs: []inputInfo{
18820                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18821                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18822                         },
18823                         outputs: []outputInfo{
18824                                 {1, 0},
18825                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18826                         },
18827                 },
18828         },
18829         {
18830                 name:   "SUB",
18831                 argLen: 2,
18832                 asm:    arm64.ASUB,
18833                 reg: regInfo{
18834                         inputs: []inputInfo{
18835                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18836                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18837                         },
18838                         outputs: []outputInfo{
18839                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18840                         },
18841                 },
18842         },
18843         {
18844                 name:    "SUBconst",
18845                 auxType: auxInt64,
18846                 argLen:  1,
18847                 asm:     arm64.ASUB,
18848                 reg: regInfo{
18849                         inputs: []inputInfo{
18850                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18851                         },
18852                         outputs: []outputInfo{
18853                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18854                         },
18855                 },
18856         },
18857         {
18858                 name:   "SBCSflags",
18859                 argLen: 3,
18860                 asm:    arm64.ASBCS,
18861                 reg: regInfo{
18862                         inputs: []inputInfo{
18863                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18864                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18865                         },
18866                         outputs: []outputInfo{
18867                                 {1, 0},
18868                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18869                         },
18870                 },
18871         },
18872         {
18873                 name:   "SUBSflags",
18874                 argLen: 2,
18875                 asm:    arm64.ASUBS,
18876                 reg: regInfo{
18877                         inputs: []inputInfo{
18878                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18879                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18880                         },
18881                         outputs: []outputInfo{
18882                                 {1, 0},
18883                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18884                         },
18885                 },
18886         },
18887         {
18888                 name:        "MUL",
18889                 argLen:      2,
18890                 commutative: true,
18891                 asm:         arm64.AMUL,
18892                 reg: regInfo{
18893                         inputs: []inputInfo{
18894                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18895                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18896                         },
18897                         outputs: []outputInfo{
18898                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18899                         },
18900                 },
18901         },
18902         {
18903                 name:        "MULW",
18904                 argLen:      2,
18905                 commutative: true,
18906                 asm:         arm64.AMULW,
18907                 reg: regInfo{
18908                         inputs: []inputInfo{
18909                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18910                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18911                         },
18912                         outputs: []outputInfo{
18913                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18914                         },
18915                 },
18916         },
18917         {
18918                 name:        "MNEG",
18919                 argLen:      2,
18920                 commutative: true,
18921                 asm:         arm64.AMNEG,
18922                 reg: regInfo{
18923                         inputs: []inputInfo{
18924                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18925                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18926                         },
18927                         outputs: []outputInfo{
18928                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18929                         },
18930                 },
18931         },
18932         {
18933                 name:        "MNEGW",
18934                 argLen:      2,
18935                 commutative: true,
18936                 asm:         arm64.AMNEGW,
18937                 reg: regInfo{
18938                         inputs: []inputInfo{
18939                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18940                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18941                         },
18942                         outputs: []outputInfo{
18943                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18944                         },
18945                 },
18946         },
18947         {
18948                 name:        "MULH",
18949                 argLen:      2,
18950                 commutative: true,
18951                 asm:         arm64.ASMULH,
18952                 reg: regInfo{
18953                         inputs: []inputInfo{
18954                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18955                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18956                         },
18957                         outputs: []outputInfo{
18958                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18959                         },
18960                 },
18961         },
18962         {
18963                 name:        "UMULH",
18964                 argLen:      2,
18965                 commutative: true,
18966                 asm:         arm64.AUMULH,
18967                 reg: regInfo{
18968                         inputs: []inputInfo{
18969                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18970                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18971                         },
18972                         outputs: []outputInfo{
18973                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18974                         },
18975                 },
18976         },
18977         {
18978                 name:        "MULL",
18979                 argLen:      2,
18980                 commutative: true,
18981                 asm:         arm64.ASMULL,
18982                 reg: regInfo{
18983                         inputs: []inputInfo{
18984                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18985                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18986                         },
18987                         outputs: []outputInfo{
18988                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18989                         },
18990                 },
18991         },
18992         {
18993                 name:        "UMULL",
18994                 argLen:      2,
18995                 commutative: true,
18996                 asm:         arm64.AUMULL,
18997                 reg: regInfo{
18998                         inputs: []inputInfo{
18999                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19000                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19001                         },
19002                         outputs: []outputInfo{
19003                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19004                         },
19005                 },
19006         },
19007         {
19008                 name:   "DIV",
19009                 argLen: 2,
19010                 asm:    arm64.ASDIV,
19011                 reg: regInfo{
19012                         inputs: []inputInfo{
19013                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19014                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19015                         },
19016                         outputs: []outputInfo{
19017                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19018                         },
19019                 },
19020         },
19021         {
19022                 name:   "UDIV",
19023                 argLen: 2,
19024                 asm:    arm64.AUDIV,
19025                 reg: regInfo{
19026                         inputs: []inputInfo{
19027                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19028                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19029                         },
19030                         outputs: []outputInfo{
19031                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19032                         },
19033                 },
19034         },
19035         {
19036                 name:   "DIVW",
19037                 argLen: 2,
19038                 asm:    arm64.ASDIVW,
19039                 reg: regInfo{
19040                         inputs: []inputInfo{
19041                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19042                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19043                         },
19044                         outputs: []outputInfo{
19045                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19046                         },
19047                 },
19048         },
19049         {
19050                 name:   "UDIVW",
19051                 argLen: 2,
19052                 asm:    arm64.AUDIVW,
19053                 reg: regInfo{
19054                         inputs: []inputInfo{
19055                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19056                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19057                         },
19058                         outputs: []outputInfo{
19059                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19060                         },
19061                 },
19062         },
19063         {
19064                 name:   "MOD",
19065                 argLen: 2,
19066                 asm:    arm64.AREM,
19067                 reg: regInfo{
19068                         inputs: []inputInfo{
19069                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19070                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19071                         },
19072                         outputs: []outputInfo{
19073                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19074                         },
19075                 },
19076         },
19077         {
19078                 name:   "UMOD",
19079                 argLen: 2,
19080                 asm:    arm64.AUREM,
19081                 reg: regInfo{
19082                         inputs: []inputInfo{
19083                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19084                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19085                         },
19086                         outputs: []outputInfo{
19087                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19088                         },
19089                 },
19090         },
19091         {
19092                 name:   "MODW",
19093                 argLen: 2,
19094                 asm:    arm64.AREMW,
19095                 reg: regInfo{
19096                         inputs: []inputInfo{
19097                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19098                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19099                         },
19100                         outputs: []outputInfo{
19101                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19102                         },
19103                 },
19104         },
19105         {
19106                 name:   "UMODW",
19107                 argLen: 2,
19108                 asm:    arm64.AUREMW,
19109                 reg: regInfo{
19110                         inputs: []inputInfo{
19111                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19112                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19113                         },
19114                         outputs: []outputInfo{
19115                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19116                         },
19117                 },
19118         },
19119         {
19120                 name:        "FADDS",
19121                 argLen:      2,
19122                 commutative: true,
19123                 asm:         arm64.AFADDS,
19124                 reg: regInfo{
19125                         inputs: []inputInfo{
19126                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19127                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19128                         },
19129                         outputs: []outputInfo{
19130                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19131                         },
19132                 },
19133         },
19134         {
19135                 name:        "FADDD",
19136                 argLen:      2,
19137                 commutative: true,
19138                 asm:         arm64.AFADDD,
19139                 reg: regInfo{
19140                         inputs: []inputInfo{
19141                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19142                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19143                         },
19144                         outputs: []outputInfo{
19145                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19146                         },
19147                 },
19148         },
19149         {
19150                 name:   "FSUBS",
19151                 argLen: 2,
19152                 asm:    arm64.AFSUBS,
19153                 reg: regInfo{
19154                         inputs: []inputInfo{
19155                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19156                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19157                         },
19158                         outputs: []outputInfo{
19159                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19160                         },
19161                 },
19162         },
19163         {
19164                 name:   "FSUBD",
19165                 argLen: 2,
19166                 asm:    arm64.AFSUBD,
19167                 reg: regInfo{
19168                         inputs: []inputInfo{
19169                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19170                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19171                         },
19172                         outputs: []outputInfo{
19173                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19174                         },
19175                 },
19176         },
19177         {
19178                 name:        "FMULS",
19179                 argLen:      2,
19180                 commutative: true,
19181                 asm:         arm64.AFMULS,
19182                 reg: regInfo{
19183                         inputs: []inputInfo{
19184                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19185                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19186                         },
19187                         outputs: []outputInfo{
19188                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19189                         },
19190                 },
19191         },
19192         {
19193                 name:        "FMULD",
19194                 argLen:      2,
19195                 commutative: true,
19196                 asm:         arm64.AFMULD,
19197                 reg: regInfo{
19198                         inputs: []inputInfo{
19199                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19200                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19201                         },
19202                         outputs: []outputInfo{
19203                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19204                         },
19205                 },
19206         },
19207         {
19208                 name:        "FNMULS",
19209                 argLen:      2,
19210                 commutative: true,
19211                 asm:         arm64.AFNMULS,
19212                 reg: regInfo{
19213                         inputs: []inputInfo{
19214                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19215                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19216                         },
19217                         outputs: []outputInfo{
19218                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19219                         },
19220                 },
19221         },
19222         {
19223                 name:        "FNMULD",
19224                 argLen:      2,
19225                 commutative: true,
19226                 asm:         arm64.AFNMULD,
19227                 reg: regInfo{
19228                         inputs: []inputInfo{
19229                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19230                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19231                         },
19232                         outputs: []outputInfo{
19233                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19234                         },
19235                 },
19236         },
19237         {
19238                 name:   "FDIVS",
19239                 argLen: 2,
19240                 asm:    arm64.AFDIVS,
19241                 reg: regInfo{
19242                         inputs: []inputInfo{
19243                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19244                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19245                         },
19246                         outputs: []outputInfo{
19247                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19248                         },
19249                 },
19250         },
19251         {
19252                 name:   "FDIVD",
19253                 argLen: 2,
19254                 asm:    arm64.AFDIVD,
19255                 reg: regInfo{
19256                         inputs: []inputInfo{
19257                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19258                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19259                         },
19260                         outputs: []outputInfo{
19261                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19262                         },
19263                 },
19264         },
19265         {
19266                 name:        "AND",
19267                 argLen:      2,
19268                 commutative: true,
19269                 asm:         arm64.AAND,
19270                 reg: regInfo{
19271                         inputs: []inputInfo{
19272                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19273                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19274                         },
19275                         outputs: []outputInfo{
19276                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19277                         },
19278                 },
19279         },
19280         {
19281                 name:    "ANDconst",
19282                 auxType: auxInt64,
19283                 argLen:  1,
19284                 asm:     arm64.AAND,
19285                 reg: regInfo{
19286                         inputs: []inputInfo{
19287                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19288                         },
19289                         outputs: []outputInfo{
19290                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19291                         },
19292                 },
19293         },
19294         {
19295                 name:        "OR",
19296                 argLen:      2,
19297                 commutative: true,
19298                 asm:         arm64.AORR,
19299                 reg: regInfo{
19300                         inputs: []inputInfo{
19301                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19302                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19303                         },
19304                         outputs: []outputInfo{
19305                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19306                         },
19307                 },
19308         },
19309         {
19310                 name:    "ORconst",
19311                 auxType: auxInt64,
19312                 argLen:  1,
19313                 asm:     arm64.AORR,
19314                 reg: regInfo{
19315                         inputs: []inputInfo{
19316                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19317                         },
19318                         outputs: []outputInfo{
19319                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19320                         },
19321                 },
19322         },
19323         {
19324                 name:        "XOR",
19325                 argLen:      2,
19326                 commutative: true,
19327                 asm:         arm64.AEOR,
19328                 reg: regInfo{
19329                         inputs: []inputInfo{
19330                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19331                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19332                         },
19333                         outputs: []outputInfo{
19334                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19335                         },
19336                 },
19337         },
19338         {
19339                 name:    "XORconst",
19340                 auxType: auxInt64,
19341                 argLen:  1,
19342                 asm:     arm64.AEOR,
19343                 reg: regInfo{
19344                         inputs: []inputInfo{
19345                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19346                         },
19347                         outputs: []outputInfo{
19348                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19349                         },
19350                 },
19351         },
19352         {
19353                 name:   "BIC",
19354                 argLen: 2,
19355                 asm:    arm64.ABIC,
19356                 reg: regInfo{
19357                         inputs: []inputInfo{
19358                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19359                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19360                         },
19361                         outputs: []outputInfo{
19362                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19363                         },
19364                 },
19365         },
19366         {
19367                 name:   "EON",
19368                 argLen: 2,
19369                 asm:    arm64.AEON,
19370                 reg: regInfo{
19371                         inputs: []inputInfo{
19372                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19373                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19374                         },
19375                         outputs: []outputInfo{
19376                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19377                         },
19378                 },
19379         },
19380         {
19381                 name:   "ORN",
19382                 argLen: 2,
19383                 asm:    arm64.AORN,
19384                 reg: regInfo{
19385                         inputs: []inputInfo{
19386                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19387                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19388                         },
19389                         outputs: []outputInfo{
19390                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19391                         },
19392                 },
19393         },
19394         {
19395                 name:   "MVN",
19396                 argLen: 1,
19397                 asm:    arm64.AMVN,
19398                 reg: regInfo{
19399                         inputs: []inputInfo{
19400                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19401                         },
19402                         outputs: []outputInfo{
19403                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19404                         },
19405                 },
19406         },
19407         {
19408                 name:   "NEG",
19409                 argLen: 1,
19410                 asm:    arm64.ANEG,
19411                 reg: regInfo{
19412                         inputs: []inputInfo{
19413                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19414                         },
19415                         outputs: []outputInfo{
19416                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19417                         },
19418                 },
19419         },
19420         {
19421                 name:   "NEGSflags",
19422                 argLen: 1,
19423                 asm:    arm64.ANEGS,
19424                 reg: regInfo{
19425                         inputs: []inputInfo{
19426                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19427                         },
19428                         outputs: []outputInfo{
19429                                 {1, 0},
19430                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19431                         },
19432                 },
19433         },
19434         {
19435                 name:   "NGCzerocarry",
19436                 argLen: 1,
19437                 asm:    arm64.ANGC,
19438                 reg: regInfo{
19439                         outputs: []outputInfo{
19440                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19441                         },
19442                 },
19443         },
19444         {
19445                 name:   "FABSD",
19446                 argLen: 1,
19447                 asm:    arm64.AFABSD,
19448                 reg: regInfo{
19449                         inputs: []inputInfo{
19450                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19451                         },
19452                         outputs: []outputInfo{
19453                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19454                         },
19455                 },
19456         },
19457         {
19458                 name:   "FNEGS",
19459                 argLen: 1,
19460                 asm:    arm64.AFNEGS,
19461                 reg: regInfo{
19462                         inputs: []inputInfo{
19463                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19464                         },
19465                         outputs: []outputInfo{
19466                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19467                         },
19468                 },
19469         },
19470         {
19471                 name:   "FNEGD",
19472                 argLen: 1,
19473                 asm:    arm64.AFNEGD,
19474                 reg: regInfo{
19475                         inputs: []inputInfo{
19476                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19477                         },
19478                         outputs: []outputInfo{
19479                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19480                         },
19481                 },
19482         },
19483         {
19484                 name:   "FSQRTD",
19485                 argLen: 1,
19486                 asm:    arm64.AFSQRTD,
19487                 reg: regInfo{
19488                         inputs: []inputInfo{
19489                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19490                         },
19491                         outputs: []outputInfo{
19492                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19493                         },
19494                 },
19495         },
19496         {
19497                 name:   "FSQRTS",
19498                 argLen: 1,
19499                 asm:    arm64.AFSQRTS,
19500                 reg: regInfo{
19501                         inputs: []inputInfo{
19502                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19503                         },
19504                         outputs: []outputInfo{
19505                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19506                         },
19507                 },
19508         },
19509         {
19510                 name:   "FMIND",
19511                 argLen: 2,
19512                 asm:    arm64.AFMIND,
19513                 reg: regInfo{
19514                         inputs: []inputInfo{
19515                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19516                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19517                         },
19518                         outputs: []outputInfo{
19519                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19520                         },
19521                 },
19522         },
19523         {
19524                 name:   "FMINS",
19525                 argLen: 2,
19526                 asm:    arm64.AFMINS,
19527                 reg: regInfo{
19528                         inputs: []inputInfo{
19529                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19530                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19531                         },
19532                         outputs: []outputInfo{
19533                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19534                         },
19535                 },
19536         },
19537         {
19538                 name:   "FMAXD",
19539                 argLen: 2,
19540                 asm:    arm64.AFMAXD,
19541                 reg: regInfo{
19542                         inputs: []inputInfo{
19543                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19544                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19545                         },
19546                         outputs: []outputInfo{
19547                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19548                         },
19549                 },
19550         },
19551         {
19552                 name:   "FMAXS",
19553                 argLen: 2,
19554                 asm:    arm64.AFMAXS,
19555                 reg: regInfo{
19556                         inputs: []inputInfo{
19557                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19558                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19559                         },
19560                         outputs: []outputInfo{
19561                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19562                         },
19563                 },
19564         },
19565         {
19566                 name:   "REV",
19567                 argLen: 1,
19568                 asm:    arm64.AREV,
19569                 reg: regInfo{
19570                         inputs: []inputInfo{
19571                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19572                         },
19573                         outputs: []outputInfo{
19574                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19575                         },
19576                 },
19577         },
19578         {
19579                 name:   "REVW",
19580                 argLen: 1,
19581                 asm:    arm64.AREVW,
19582                 reg: regInfo{
19583                         inputs: []inputInfo{
19584                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19585                         },
19586                         outputs: []outputInfo{
19587                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19588                         },
19589                 },
19590         },
19591         {
19592                 name:   "REV16",
19593                 argLen: 1,
19594                 asm:    arm64.AREV16,
19595                 reg: regInfo{
19596                         inputs: []inputInfo{
19597                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19598                         },
19599                         outputs: []outputInfo{
19600                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19601                         },
19602                 },
19603         },
19604         {
19605                 name:   "REV16W",
19606                 argLen: 1,
19607                 asm:    arm64.AREV16W,
19608                 reg: regInfo{
19609                         inputs: []inputInfo{
19610                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19611                         },
19612                         outputs: []outputInfo{
19613                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19614                         },
19615                 },
19616         },
19617         {
19618                 name:   "RBIT",
19619                 argLen: 1,
19620                 asm:    arm64.ARBIT,
19621                 reg: regInfo{
19622                         inputs: []inputInfo{
19623                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19624                         },
19625                         outputs: []outputInfo{
19626                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19627                         },
19628                 },
19629         },
19630         {
19631                 name:   "RBITW",
19632                 argLen: 1,
19633                 asm:    arm64.ARBITW,
19634                 reg: regInfo{
19635                         inputs: []inputInfo{
19636                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19637                         },
19638                         outputs: []outputInfo{
19639                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19640                         },
19641                 },
19642         },
19643         {
19644                 name:   "CLZ",
19645                 argLen: 1,
19646                 asm:    arm64.ACLZ,
19647                 reg: regInfo{
19648                         inputs: []inputInfo{
19649                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19650                         },
19651                         outputs: []outputInfo{
19652                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19653                         },
19654                 },
19655         },
19656         {
19657                 name:   "CLZW",
19658                 argLen: 1,
19659                 asm:    arm64.ACLZW,
19660                 reg: regInfo{
19661                         inputs: []inputInfo{
19662                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19663                         },
19664                         outputs: []outputInfo{
19665                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19666                         },
19667                 },
19668         },
19669         {
19670                 name:   "VCNT",
19671                 argLen: 1,
19672                 asm:    arm64.AVCNT,
19673                 reg: regInfo{
19674                         inputs: []inputInfo{
19675                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19676                         },
19677                         outputs: []outputInfo{
19678                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19679                         },
19680                 },
19681         },
19682         {
19683                 name:   "VUADDLV",
19684                 argLen: 1,
19685                 asm:    arm64.AVUADDLV,
19686                 reg: regInfo{
19687                         inputs: []inputInfo{
19688                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19689                         },
19690                         outputs: []outputInfo{
19691                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19692                         },
19693                 },
19694         },
19695         {
19696                 name:         "LoweredRound32F",
19697                 argLen:       1,
19698                 resultInArg0: true,
19699                 zeroWidth:    true,
19700                 reg: regInfo{
19701                         inputs: []inputInfo{
19702                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19703                         },
19704                         outputs: []outputInfo{
19705                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19706                         },
19707                 },
19708         },
19709         {
19710                 name:         "LoweredRound64F",
19711                 argLen:       1,
19712                 resultInArg0: true,
19713                 zeroWidth:    true,
19714                 reg: regInfo{
19715                         inputs: []inputInfo{
19716                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19717                         },
19718                         outputs: []outputInfo{
19719                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19720                         },
19721                 },
19722         },
19723         {
19724                 name:   "FMADDS",
19725                 argLen: 3,
19726                 asm:    arm64.AFMADDS,
19727                 reg: regInfo{
19728                         inputs: []inputInfo{
19729                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19730                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19731                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19732                         },
19733                         outputs: []outputInfo{
19734                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19735                         },
19736                 },
19737         },
19738         {
19739                 name:   "FMADDD",
19740                 argLen: 3,
19741                 asm:    arm64.AFMADDD,
19742                 reg: regInfo{
19743                         inputs: []inputInfo{
19744                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19745                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19746                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19747                         },
19748                         outputs: []outputInfo{
19749                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19750                         },
19751                 },
19752         },
19753         {
19754                 name:   "FNMADDS",
19755                 argLen: 3,
19756                 asm:    arm64.AFNMADDS,
19757                 reg: regInfo{
19758                         inputs: []inputInfo{
19759                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19760                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19761                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19762                         },
19763                         outputs: []outputInfo{
19764                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19765                         },
19766                 },
19767         },
19768         {
19769                 name:   "FNMADDD",
19770                 argLen: 3,
19771                 asm:    arm64.AFNMADDD,
19772                 reg: regInfo{
19773                         inputs: []inputInfo{
19774                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19775                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19776                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19777                         },
19778                         outputs: []outputInfo{
19779                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19780                         },
19781                 },
19782         },
19783         {
19784                 name:   "FMSUBS",
19785                 argLen: 3,
19786                 asm:    arm64.AFMSUBS,
19787                 reg: regInfo{
19788                         inputs: []inputInfo{
19789                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19790                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19791                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19792                         },
19793                         outputs: []outputInfo{
19794                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19795                         },
19796                 },
19797         },
19798         {
19799                 name:   "FMSUBD",
19800                 argLen: 3,
19801                 asm:    arm64.AFMSUBD,
19802                 reg: regInfo{
19803                         inputs: []inputInfo{
19804                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19805                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19806                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19807                         },
19808                         outputs: []outputInfo{
19809                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19810                         },
19811                 },
19812         },
19813         {
19814                 name:   "FNMSUBS",
19815                 argLen: 3,
19816                 asm:    arm64.AFNMSUBS,
19817                 reg: regInfo{
19818                         inputs: []inputInfo{
19819                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19820                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19821                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19822                         },
19823                         outputs: []outputInfo{
19824                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19825                         },
19826                 },
19827         },
19828         {
19829                 name:   "FNMSUBD",
19830                 argLen: 3,
19831                 asm:    arm64.AFNMSUBD,
19832                 reg: regInfo{
19833                         inputs: []inputInfo{
19834                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19835                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19836                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19837                         },
19838                         outputs: []outputInfo{
19839                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19840                         },
19841                 },
19842         },
19843         {
19844                 name:   "MADD",
19845                 argLen: 3,
19846                 asm:    arm64.AMADD,
19847                 reg: regInfo{
19848                         inputs: []inputInfo{
19849                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19850                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19851                                 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19852                         },
19853                         outputs: []outputInfo{
19854                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19855                         },
19856                 },
19857         },
19858         {
19859                 name:   "MADDW",
19860                 argLen: 3,
19861                 asm:    arm64.AMADDW,
19862                 reg: regInfo{
19863                         inputs: []inputInfo{
19864                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19865                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19866                                 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19867                         },
19868                         outputs: []outputInfo{
19869                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19870                         },
19871                 },
19872         },
19873         {
19874                 name:   "MSUB",
19875                 argLen: 3,
19876                 asm:    arm64.AMSUB,
19877                 reg: regInfo{
19878                         inputs: []inputInfo{
19879                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19880                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19881                                 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19882                         },
19883                         outputs: []outputInfo{
19884                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19885                         },
19886                 },
19887         },
19888         {
19889                 name:   "MSUBW",
19890                 argLen: 3,
19891                 asm:    arm64.AMSUBW,
19892                 reg: regInfo{
19893                         inputs: []inputInfo{
19894                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19895                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19896                                 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19897                         },
19898                         outputs: []outputInfo{
19899                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19900                         },
19901                 },
19902         },
19903         {
19904                 name:   "SLL",
19905                 argLen: 2,
19906                 asm:    arm64.ALSL,
19907                 reg: regInfo{
19908                         inputs: []inputInfo{
19909                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19910                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19911                         },
19912                         outputs: []outputInfo{
19913                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19914                         },
19915                 },
19916         },
19917         {
19918                 name:    "SLLconst",
19919                 auxType: auxInt64,
19920                 argLen:  1,
19921                 asm:     arm64.ALSL,
19922                 reg: regInfo{
19923                         inputs: []inputInfo{
19924                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19925                         },
19926                         outputs: []outputInfo{
19927                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19928                         },
19929                 },
19930         },
19931         {
19932                 name:   "SRL",
19933                 argLen: 2,
19934                 asm:    arm64.ALSR,
19935                 reg: regInfo{
19936                         inputs: []inputInfo{
19937                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19938                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19939                         },
19940                         outputs: []outputInfo{
19941                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19942                         },
19943                 },
19944         },
19945         {
19946                 name:    "SRLconst",
19947                 auxType: auxInt64,
19948                 argLen:  1,
19949                 asm:     arm64.ALSR,
19950                 reg: regInfo{
19951                         inputs: []inputInfo{
19952                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19953                         },
19954                         outputs: []outputInfo{
19955                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19956                         },
19957                 },
19958         },
19959         {
19960                 name:   "SRA",
19961                 argLen: 2,
19962                 asm:    arm64.AASR,
19963                 reg: regInfo{
19964                         inputs: []inputInfo{
19965                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19966                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19967                         },
19968                         outputs: []outputInfo{
19969                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19970                         },
19971                 },
19972         },
19973         {
19974                 name:    "SRAconst",
19975                 auxType: auxInt64,
19976                 argLen:  1,
19977                 asm:     arm64.AASR,
19978                 reg: regInfo{
19979                         inputs: []inputInfo{
19980                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19981                         },
19982                         outputs: []outputInfo{
19983                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19984                         },
19985                 },
19986         },
19987         {
19988                 name:   "ROR",
19989                 argLen: 2,
19990                 asm:    arm64.AROR,
19991                 reg: regInfo{
19992                         inputs: []inputInfo{
19993                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19994                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19995                         },
19996                         outputs: []outputInfo{
19997                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19998                         },
19999                 },
20000         },
20001         {
20002                 name:   "RORW",
20003                 argLen: 2,
20004                 asm:    arm64.ARORW,
20005                 reg: regInfo{
20006                         inputs: []inputInfo{
20007                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20008                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20009                         },
20010                         outputs: []outputInfo{
20011                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20012                         },
20013                 },
20014         },
20015         {
20016                 name:    "RORconst",
20017                 auxType: auxInt64,
20018                 argLen:  1,
20019                 asm:     arm64.AROR,
20020                 reg: regInfo{
20021                         inputs: []inputInfo{
20022                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20023                         },
20024                         outputs: []outputInfo{
20025                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20026                         },
20027                 },
20028         },
20029         {
20030                 name:    "RORWconst",
20031                 auxType: auxInt64,
20032                 argLen:  1,
20033                 asm:     arm64.ARORW,
20034                 reg: regInfo{
20035                         inputs: []inputInfo{
20036                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20037                         },
20038                         outputs: []outputInfo{
20039                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20040                         },
20041                 },
20042         },
20043         {
20044                 name:    "EXTRconst",
20045                 auxType: auxInt64,
20046                 argLen:  2,
20047                 asm:     arm64.AEXTR,
20048                 reg: regInfo{
20049                         inputs: []inputInfo{
20050                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20051                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20052                         },
20053                         outputs: []outputInfo{
20054                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20055                         },
20056                 },
20057         },
20058         {
20059                 name:    "EXTRWconst",
20060                 auxType: auxInt64,
20061                 argLen:  2,
20062                 asm:     arm64.AEXTRW,
20063                 reg: regInfo{
20064                         inputs: []inputInfo{
20065                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20066                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20067                         },
20068                         outputs: []outputInfo{
20069                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20070                         },
20071                 },
20072         },
20073         {
20074                 name:   "CMP",
20075                 argLen: 2,
20076                 asm:    arm64.ACMP,
20077                 reg: regInfo{
20078                         inputs: []inputInfo{
20079                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20080                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20081                         },
20082                 },
20083         },
20084         {
20085                 name:    "CMPconst",
20086                 auxType: auxInt64,
20087                 argLen:  1,
20088                 asm:     arm64.ACMP,
20089                 reg: regInfo{
20090                         inputs: []inputInfo{
20091                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20092                         },
20093                 },
20094         },
20095         {
20096                 name:   "CMPW",
20097                 argLen: 2,
20098                 asm:    arm64.ACMPW,
20099                 reg: regInfo{
20100                         inputs: []inputInfo{
20101                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20102                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20103                         },
20104                 },
20105         },
20106         {
20107                 name:    "CMPWconst",
20108                 auxType: auxInt32,
20109                 argLen:  1,
20110                 asm:     arm64.ACMPW,
20111                 reg: regInfo{
20112                         inputs: []inputInfo{
20113                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20114                         },
20115                 },
20116         },
20117         {
20118                 name:        "CMN",
20119                 argLen:      2,
20120                 commutative: true,
20121                 asm:         arm64.ACMN,
20122                 reg: regInfo{
20123                         inputs: []inputInfo{
20124                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20125                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20126                         },
20127                 },
20128         },
20129         {
20130                 name:    "CMNconst",
20131                 auxType: auxInt64,
20132                 argLen:  1,
20133                 asm:     arm64.ACMN,
20134                 reg: regInfo{
20135                         inputs: []inputInfo{
20136                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20137                         },
20138                 },
20139         },
20140         {
20141                 name:        "CMNW",
20142                 argLen:      2,
20143                 commutative: true,
20144                 asm:         arm64.ACMNW,
20145                 reg: regInfo{
20146                         inputs: []inputInfo{
20147                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20148                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20149                         },
20150                 },
20151         },
20152         {
20153                 name:    "CMNWconst",
20154                 auxType: auxInt32,
20155                 argLen:  1,
20156                 asm:     arm64.ACMNW,
20157                 reg: regInfo{
20158                         inputs: []inputInfo{
20159                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20160                         },
20161                 },
20162         },
20163         {
20164                 name:        "TST",
20165                 argLen:      2,
20166                 commutative: true,
20167                 asm:         arm64.ATST,
20168                 reg: regInfo{
20169                         inputs: []inputInfo{
20170                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20171                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20172                         },
20173                 },
20174         },
20175         {
20176                 name:    "TSTconst",
20177                 auxType: auxInt64,
20178                 argLen:  1,
20179                 asm:     arm64.ATST,
20180                 reg: regInfo{
20181                         inputs: []inputInfo{
20182                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20183                         },
20184                 },
20185         },
20186         {
20187                 name:        "TSTW",
20188                 argLen:      2,
20189                 commutative: true,
20190                 asm:         arm64.ATSTW,
20191                 reg: regInfo{
20192                         inputs: []inputInfo{
20193                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20194                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20195                         },
20196                 },
20197         },
20198         {
20199                 name:    "TSTWconst",
20200                 auxType: auxInt32,
20201                 argLen:  1,
20202                 asm:     arm64.ATSTW,
20203                 reg: regInfo{
20204                         inputs: []inputInfo{
20205                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20206                         },
20207                 },
20208         },
20209         {
20210                 name:   "FCMPS",
20211                 argLen: 2,
20212                 asm:    arm64.AFCMPS,
20213                 reg: regInfo{
20214                         inputs: []inputInfo{
20215                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20216                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20217                         },
20218                 },
20219         },
20220         {
20221                 name:   "FCMPD",
20222                 argLen: 2,
20223                 asm:    arm64.AFCMPD,
20224                 reg: regInfo{
20225                         inputs: []inputInfo{
20226                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20227                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20228                         },
20229                 },
20230         },
20231         {
20232                 name:   "FCMPS0",
20233                 argLen: 1,
20234                 asm:    arm64.AFCMPS,
20235                 reg: regInfo{
20236                         inputs: []inputInfo{
20237                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20238                         },
20239                 },
20240         },
20241         {
20242                 name:   "FCMPD0",
20243                 argLen: 1,
20244                 asm:    arm64.AFCMPD,
20245                 reg: regInfo{
20246                         inputs: []inputInfo{
20247                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20248                         },
20249                 },
20250         },
20251         {
20252                 name:    "MVNshiftLL",
20253                 auxType: auxInt64,
20254                 argLen:  1,
20255                 asm:     arm64.AMVN,
20256                 reg: regInfo{
20257                         inputs: []inputInfo{
20258                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20259                         },
20260                         outputs: []outputInfo{
20261                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20262                         },
20263                 },
20264         },
20265         {
20266                 name:    "MVNshiftRL",
20267                 auxType: auxInt64,
20268                 argLen:  1,
20269                 asm:     arm64.AMVN,
20270                 reg: regInfo{
20271                         inputs: []inputInfo{
20272                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20273                         },
20274                         outputs: []outputInfo{
20275                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20276                         },
20277                 },
20278         },
20279         {
20280                 name:    "MVNshiftRA",
20281                 auxType: auxInt64,
20282                 argLen:  1,
20283                 asm:     arm64.AMVN,
20284                 reg: regInfo{
20285                         inputs: []inputInfo{
20286                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20287                         },
20288                         outputs: []outputInfo{
20289                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20290                         },
20291                 },
20292         },
20293         {
20294                 name:    "MVNshiftRO",
20295                 auxType: auxInt64,
20296                 argLen:  1,
20297                 asm:     arm64.AMVN,
20298                 reg: regInfo{
20299                         inputs: []inputInfo{
20300                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20301                         },
20302                         outputs: []outputInfo{
20303                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20304                         },
20305                 },
20306         },
20307         {
20308                 name:    "NEGshiftLL",
20309                 auxType: auxInt64,
20310                 argLen:  1,
20311                 asm:     arm64.ANEG,
20312                 reg: regInfo{
20313                         inputs: []inputInfo{
20314                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20315                         },
20316                         outputs: []outputInfo{
20317                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20318                         },
20319                 },
20320         },
20321         {
20322                 name:    "NEGshiftRL",
20323                 auxType: auxInt64,
20324                 argLen:  1,
20325                 asm:     arm64.ANEG,
20326                 reg: regInfo{
20327                         inputs: []inputInfo{
20328                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20329                         },
20330                         outputs: []outputInfo{
20331                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20332                         },
20333                 },
20334         },
20335         {
20336                 name:    "NEGshiftRA",
20337                 auxType: auxInt64,
20338                 argLen:  1,
20339                 asm:     arm64.ANEG,
20340                 reg: regInfo{
20341                         inputs: []inputInfo{
20342                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20343                         },
20344                         outputs: []outputInfo{
20345                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20346                         },
20347                 },
20348         },
20349         {
20350                 name:    "ADDshiftLL",
20351                 auxType: auxInt64,
20352                 argLen:  2,
20353                 asm:     arm64.AADD,
20354                 reg: regInfo{
20355                         inputs: []inputInfo{
20356                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20357                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20358                         },
20359                         outputs: []outputInfo{
20360                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20361                         },
20362                 },
20363         },
20364         {
20365                 name:    "ADDshiftRL",
20366                 auxType: auxInt64,
20367                 argLen:  2,
20368                 asm:     arm64.AADD,
20369                 reg: regInfo{
20370                         inputs: []inputInfo{
20371                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20372                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20373                         },
20374                         outputs: []outputInfo{
20375                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20376                         },
20377                 },
20378         },
20379         {
20380                 name:    "ADDshiftRA",
20381                 auxType: auxInt64,
20382                 argLen:  2,
20383                 asm:     arm64.AADD,
20384                 reg: regInfo{
20385                         inputs: []inputInfo{
20386                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20387                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20388                         },
20389                         outputs: []outputInfo{
20390                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20391                         },
20392                 },
20393         },
20394         {
20395                 name:    "SUBshiftLL",
20396                 auxType: auxInt64,
20397                 argLen:  2,
20398                 asm:     arm64.ASUB,
20399                 reg: regInfo{
20400                         inputs: []inputInfo{
20401                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20402                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20403                         },
20404                         outputs: []outputInfo{
20405                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20406                         },
20407                 },
20408         },
20409         {
20410                 name:    "SUBshiftRL",
20411                 auxType: auxInt64,
20412                 argLen:  2,
20413                 asm:     arm64.ASUB,
20414                 reg: regInfo{
20415                         inputs: []inputInfo{
20416                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20417                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20418                         },
20419                         outputs: []outputInfo{
20420                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20421                         },
20422                 },
20423         },
20424         {
20425                 name:    "SUBshiftRA",
20426                 auxType: auxInt64,
20427                 argLen:  2,
20428                 asm:     arm64.ASUB,
20429                 reg: regInfo{
20430                         inputs: []inputInfo{
20431                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20432                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20433                         },
20434                         outputs: []outputInfo{
20435                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20436                         },
20437                 },
20438         },
20439         {
20440                 name:    "ANDshiftLL",
20441                 auxType: auxInt64,
20442                 argLen:  2,
20443                 asm:     arm64.AAND,
20444                 reg: regInfo{
20445                         inputs: []inputInfo{
20446                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20447                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20448                         },
20449                         outputs: []outputInfo{
20450                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20451                         },
20452                 },
20453         },
20454         {
20455                 name:    "ANDshiftRL",
20456                 auxType: auxInt64,
20457                 argLen:  2,
20458                 asm:     arm64.AAND,
20459                 reg: regInfo{
20460                         inputs: []inputInfo{
20461                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20462                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20463                         },
20464                         outputs: []outputInfo{
20465                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20466                         },
20467                 },
20468         },
20469         {
20470                 name:    "ANDshiftRA",
20471                 auxType: auxInt64,
20472                 argLen:  2,
20473                 asm:     arm64.AAND,
20474                 reg: regInfo{
20475                         inputs: []inputInfo{
20476                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20477                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20478                         },
20479                         outputs: []outputInfo{
20480                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20481                         },
20482                 },
20483         },
20484         {
20485                 name:    "ANDshiftRO",
20486                 auxType: auxInt64,
20487                 argLen:  2,
20488                 asm:     arm64.AAND,
20489                 reg: regInfo{
20490                         inputs: []inputInfo{
20491                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20492                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20493                         },
20494                         outputs: []outputInfo{
20495                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20496                         },
20497                 },
20498         },
20499         {
20500                 name:    "ORshiftLL",
20501                 auxType: auxInt64,
20502                 argLen:  2,
20503                 asm:     arm64.AORR,
20504                 reg: regInfo{
20505                         inputs: []inputInfo{
20506                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20507                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20508                         },
20509                         outputs: []outputInfo{
20510                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20511                         },
20512                 },
20513         },
20514         {
20515                 name:    "ORshiftRL",
20516                 auxType: auxInt64,
20517                 argLen:  2,
20518                 asm:     arm64.AORR,
20519                 reg: regInfo{
20520                         inputs: []inputInfo{
20521                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20522                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20523                         },
20524                         outputs: []outputInfo{
20525                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20526                         },
20527                 },
20528         },
20529         {
20530                 name:    "ORshiftRA",
20531                 auxType: auxInt64,
20532                 argLen:  2,
20533                 asm:     arm64.AORR,
20534                 reg: regInfo{
20535                         inputs: []inputInfo{
20536                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20537                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20538                         },
20539                         outputs: []outputInfo{
20540                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20541                         },
20542                 },
20543         },
20544         {
20545                 name:    "ORshiftRO",
20546                 auxType: auxInt64,
20547                 argLen:  2,
20548                 asm:     arm64.AORR,
20549                 reg: regInfo{
20550                         inputs: []inputInfo{
20551                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20552                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20553                         },
20554                         outputs: []outputInfo{
20555                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20556                         },
20557                 },
20558         },
20559         {
20560                 name:    "XORshiftLL",
20561                 auxType: auxInt64,
20562                 argLen:  2,
20563                 asm:     arm64.AEOR,
20564                 reg: regInfo{
20565                         inputs: []inputInfo{
20566                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20567                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20568                         },
20569                         outputs: []outputInfo{
20570                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20571                         },
20572                 },
20573         },
20574         {
20575                 name:    "XORshiftRL",
20576                 auxType: auxInt64,
20577                 argLen:  2,
20578                 asm:     arm64.AEOR,
20579                 reg: regInfo{
20580                         inputs: []inputInfo{
20581                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20582                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20583                         },
20584                         outputs: []outputInfo{
20585                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20586                         },
20587                 },
20588         },
20589         {
20590                 name:    "XORshiftRA",
20591                 auxType: auxInt64,
20592                 argLen:  2,
20593                 asm:     arm64.AEOR,
20594                 reg: regInfo{
20595                         inputs: []inputInfo{
20596                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20597                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20598                         },
20599                         outputs: []outputInfo{
20600                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20601                         },
20602                 },
20603         },
20604         {
20605                 name:    "XORshiftRO",
20606                 auxType: auxInt64,
20607                 argLen:  2,
20608                 asm:     arm64.AEOR,
20609                 reg: regInfo{
20610                         inputs: []inputInfo{
20611                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20612                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20613                         },
20614                         outputs: []outputInfo{
20615                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20616                         },
20617                 },
20618         },
20619         {
20620                 name:    "BICshiftLL",
20621                 auxType: auxInt64,
20622                 argLen:  2,
20623                 asm:     arm64.ABIC,
20624                 reg: regInfo{
20625                         inputs: []inputInfo{
20626                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20627                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20628                         },
20629                         outputs: []outputInfo{
20630                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20631                         },
20632                 },
20633         },
20634         {
20635                 name:    "BICshiftRL",
20636                 auxType: auxInt64,
20637                 argLen:  2,
20638                 asm:     arm64.ABIC,
20639                 reg: regInfo{
20640                         inputs: []inputInfo{
20641                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20642                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20643                         },
20644                         outputs: []outputInfo{
20645                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20646                         },
20647                 },
20648         },
20649         {
20650                 name:    "BICshiftRA",
20651                 auxType: auxInt64,
20652                 argLen:  2,
20653                 asm:     arm64.ABIC,
20654                 reg: regInfo{
20655                         inputs: []inputInfo{
20656                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20657                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20658                         },
20659                         outputs: []outputInfo{
20660                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20661                         },
20662                 },
20663         },
20664         {
20665                 name:    "BICshiftRO",
20666                 auxType: auxInt64,
20667                 argLen:  2,
20668                 asm:     arm64.ABIC,
20669                 reg: regInfo{
20670                         inputs: []inputInfo{
20671                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20672                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20673                         },
20674                         outputs: []outputInfo{
20675                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20676                         },
20677                 },
20678         },
20679         {
20680                 name:    "EONshiftLL",
20681                 auxType: auxInt64,
20682                 argLen:  2,
20683                 asm:     arm64.AEON,
20684                 reg: regInfo{
20685                         inputs: []inputInfo{
20686                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20687                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20688                         },
20689                         outputs: []outputInfo{
20690                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20691                         },
20692                 },
20693         },
20694         {
20695                 name:    "EONshiftRL",
20696                 auxType: auxInt64,
20697                 argLen:  2,
20698                 asm:     arm64.AEON,
20699                 reg: regInfo{
20700                         inputs: []inputInfo{
20701                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20702                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20703                         },
20704                         outputs: []outputInfo{
20705                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20706                         },
20707                 },
20708         },
20709         {
20710                 name:    "EONshiftRA",
20711                 auxType: auxInt64,
20712                 argLen:  2,
20713                 asm:     arm64.AEON,
20714                 reg: regInfo{
20715                         inputs: []inputInfo{
20716                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20717                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20718                         },
20719                         outputs: []outputInfo{
20720                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20721                         },
20722                 },
20723         },
20724         {
20725                 name:    "EONshiftRO",
20726                 auxType: auxInt64,
20727                 argLen:  2,
20728                 asm:     arm64.AEON,
20729                 reg: regInfo{
20730                         inputs: []inputInfo{
20731                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20732                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20733                         },
20734                         outputs: []outputInfo{
20735                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20736                         },
20737                 },
20738         },
20739         {
20740                 name:    "ORNshiftLL",
20741                 auxType: auxInt64,
20742                 argLen:  2,
20743                 asm:     arm64.AORN,
20744                 reg: regInfo{
20745                         inputs: []inputInfo{
20746                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20747                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20748                         },
20749                         outputs: []outputInfo{
20750                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20751                         },
20752                 },
20753         },
20754         {
20755                 name:    "ORNshiftRL",
20756                 auxType: auxInt64,
20757                 argLen:  2,
20758                 asm:     arm64.AORN,
20759                 reg: regInfo{
20760                         inputs: []inputInfo{
20761                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20762                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20763                         },
20764                         outputs: []outputInfo{
20765                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20766                         },
20767                 },
20768         },
20769         {
20770                 name:    "ORNshiftRA",
20771                 auxType: auxInt64,
20772                 argLen:  2,
20773                 asm:     arm64.AORN,
20774                 reg: regInfo{
20775                         inputs: []inputInfo{
20776                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20777                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20778                         },
20779                         outputs: []outputInfo{
20780                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20781                         },
20782                 },
20783         },
20784         {
20785                 name:    "ORNshiftRO",
20786                 auxType: auxInt64,
20787                 argLen:  2,
20788                 asm:     arm64.AORN,
20789                 reg: regInfo{
20790                         inputs: []inputInfo{
20791                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20792                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20793                         },
20794                         outputs: []outputInfo{
20795                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20796                         },
20797                 },
20798         },
20799         {
20800                 name:    "CMPshiftLL",
20801                 auxType: auxInt64,
20802                 argLen:  2,
20803                 asm:     arm64.ACMP,
20804                 reg: regInfo{
20805                         inputs: []inputInfo{
20806                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20807                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20808                         },
20809                 },
20810         },
20811         {
20812                 name:    "CMPshiftRL",
20813                 auxType: auxInt64,
20814                 argLen:  2,
20815                 asm:     arm64.ACMP,
20816                 reg: regInfo{
20817                         inputs: []inputInfo{
20818                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20819                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20820                         },
20821                 },
20822         },
20823         {
20824                 name:    "CMPshiftRA",
20825                 auxType: auxInt64,
20826                 argLen:  2,
20827                 asm:     arm64.ACMP,
20828                 reg: regInfo{
20829                         inputs: []inputInfo{
20830                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20831                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20832                         },
20833                 },
20834         },
20835         {
20836                 name:    "CMNshiftLL",
20837                 auxType: auxInt64,
20838                 argLen:  2,
20839                 asm:     arm64.ACMN,
20840                 reg: regInfo{
20841                         inputs: []inputInfo{
20842                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20843                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20844                         },
20845                 },
20846         },
20847         {
20848                 name:    "CMNshiftRL",
20849                 auxType: auxInt64,
20850                 argLen:  2,
20851                 asm:     arm64.ACMN,
20852                 reg: regInfo{
20853                         inputs: []inputInfo{
20854                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20855                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20856                         },
20857                 },
20858         },
20859         {
20860                 name:    "CMNshiftRA",
20861                 auxType: auxInt64,
20862                 argLen:  2,
20863                 asm:     arm64.ACMN,
20864                 reg: regInfo{
20865                         inputs: []inputInfo{
20866                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20867                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20868                         },
20869                 },
20870         },
20871         {
20872                 name:    "TSTshiftLL",
20873                 auxType: auxInt64,
20874                 argLen:  2,
20875                 asm:     arm64.ATST,
20876                 reg: regInfo{
20877                         inputs: []inputInfo{
20878                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20879                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20880                         },
20881                 },
20882         },
20883         {
20884                 name:    "TSTshiftRL",
20885                 auxType: auxInt64,
20886                 argLen:  2,
20887                 asm:     arm64.ATST,
20888                 reg: regInfo{
20889                         inputs: []inputInfo{
20890                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20891                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20892                         },
20893                 },
20894         },
20895         {
20896                 name:    "TSTshiftRA",
20897                 auxType: auxInt64,
20898                 argLen:  2,
20899                 asm:     arm64.ATST,
20900                 reg: regInfo{
20901                         inputs: []inputInfo{
20902                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20903                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20904                         },
20905                 },
20906         },
20907         {
20908                 name:    "TSTshiftRO",
20909                 auxType: auxInt64,
20910                 argLen:  2,
20911                 asm:     arm64.ATST,
20912                 reg: regInfo{
20913                         inputs: []inputInfo{
20914                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20915                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20916                         },
20917                 },
20918         },
20919         {
20920                 name:         "BFI",
20921                 auxType:      auxARM64BitField,
20922                 argLen:       2,
20923                 resultInArg0: true,
20924                 asm:          arm64.ABFI,
20925                 reg: regInfo{
20926                         inputs: []inputInfo{
20927                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20928                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20929                         },
20930                         outputs: []outputInfo{
20931                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20932                         },
20933                 },
20934         },
20935         {
20936                 name:         "BFXIL",
20937                 auxType:      auxARM64BitField,
20938                 argLen:       2,
20939                 resultInArg0: true,
20940                 asm:          arm64.ABFXIL,
20941                 reg: regInfo{
20942                         inputs: []inputInfo{
20943                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20944                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20945                         },
20946                         outputs: []outputInfo{
20947                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20948                         },
20949                 },
20950         },
20951         {
20952                 name:    "SBFIZ",
20953                 auxType: auxARM64BitField,
20954                 argLen:  1,
20955                 asm:     arm64.ASBFIZ,
20956                 reg: regInfo{
20957                         inputs: []inputInfo{
20958                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20959                         },
20960                         outputs: []outputInfo{
20961                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20962                         },
20963                 },
20964         },
20965         {
20966                 name:    "SBFX",
20967                 auxType: auxARM64BitField,
20968                 argLen:  1,
20969                 asm:     arm64.ASBFX,
20970                 reg: regInfo{
20971                         inputs: []inputInfo{
20972                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20973                         },
20974                         outputs: []outputInfo{
20975                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20976                         },
20977                 },
20978         },
20979         {
20980                 name:    "UBFIZ",
20981                 auxType: auxARM64BitField,
20982                 argLen:  1,
20983                 asm:     arm64.AUBFIZ,
20984                 reg: regInfo{
20985                         inputs: []inputInfo{
20986                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20987                         },
20988                         outputs: []outputInfo{
20989                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20990                         },
20991                 },
20992         },
20993         {
20994                 name:    "UBFX",
20995                 auxType: auxARM64BitField,
20996                 argLen:  1,
20997                 asm:     arm64.AUBFX,
20998                 reg: regInfo{
20999                         inputs: []inputInfo{
21000                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21001                         },
21002                         outputs: []outputInfo{
21003                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21004                         },
21005                 },
21006         },
21007         {
21008                 name:              "MOVDconst",
21009                 auxType:           auxInt64,
21010                 argLen:            0,
21011                 rematerializeable: true,
21012                 asm:               arm64.AMOVD,
21013                 reg: regInfo{
21014                         outputs: []outputInfo{
21015                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21016                         },
21017                 },
21018         },
21019         {
21020                 name:              "FMOVSconst",
21021                 auxType:           auxFloat64,
21022                 argLen:            0,
21023                 rematerializeable: true,
21024                 asm:               arm64.AFMOVS,
21025                 reg: regInfo{
21026                         outputs: []outputInfo{
21027                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21028                         },
21029                 },
21030         },
21031         {
21032                 name:              "FMOVDconst",
21033                 auxType:           auxFloat64,
21034                 argLen:            0,
21035                 rematerializeable: true,
21036                 asm:               arm64.AFMOVD,
21037                 reg: regInfo{
21038                         outputs: []outputInfo{
21039                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21040                         },
21041                 },
21042         },
21043         {
21044                 name:              "MOVDaddr",
21045                 auxType:           auxSymOff,
21046                 argLen:            1,
21047                 rematerializeable: true,
21048                 symEffect:         SymAddr,
21049                 asm:               arm64.AMOVD,
21050                 reg: regInfo{
21051                         inputs: []inputInfo{
21052                                 {0, 9223372037928517632}, // SP SB
21053                         },
21054                         outputs: []outputInfo{
21055                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21056                         },
21057                 },
21058         },
21059         {
21060                 name:           "MOVBload",
21061                 auxType:        auxSymOff,
21062                 argLen:         2,
21063                 faultOnNilArg0: true,
21064                 symEffect:      SymRead,
21065                 asm:            arm64.AMOVB,
21066                 reg: regInfo{
21067                         inputs: []inputInfo{
21068                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21069                         },
21070                         outputs: []outputInfo{
21071                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21072                         },
21073                 },
21074         },
21075         {
21076                 name:           "MOVBUload",
21077                 auxType:        auxSymOff,
21078                 argLen:         2,
21079                 faultOnNilArg0: true,
21080                 symEffect:      SymRead,
21081                 asm:            arm64.AMOVBU,
21082                 reg: regInfo{
21083                         inputs: []inputInfo{
21084                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21085                         },
21086                         outputs: []outputInfo{
21087                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21088                         },
21089                 },
21090         },
21091         {
21092                 name:           "MOVHload",
21093                 auxType:        auxSymOff,
21094                 argLen:         2,
21095                 faultOnNilArg0: true,
21096                 symEffect:      SymRead,
21097                 asm:            arm64.AMOVH,
21098                 reg: regInfo{
21099                         inputs: []inputInfo{
21100                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21101                         },
21102                         outputs: []outputInfo{
21103                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21104                         },
21105                 },
21106         },
21107         {
21108                 name:           "MOVHUload",
21109                 auxType:        auxSymOff,
21110                 argLen:         2,
21111                 faultOnNilArg0: true,
21112                 symEffect:      SymRead,
21113                 asm:            arm64.AMOVHU,
21114                 reg: regInfo{
21115                         inputs: []inputInfo{
21116                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21117                         },
21118                         outputs: []outputInfo{
21119                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21120                         },
21121                 },
21122         },
21123         {
21124                 name:           "MOVWload",
21125                 auxType:        auxSymOff,
21126                 argLen:         2,
21127                 faultOnNilArg0: true,
21128                 symEffect:      SymRead,
21129                 asm:            arm64.AMOVW,
21130                 reg: regInfo{
21131                         inputs: []inputInfo{
21132                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21133                         },
21134                         outputs: []outputInfo{
21135                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21136                         },
21137                 },
21138         },
21139         {
21140                 name:           "MOVWUload",
21141                 auxType:        auxSymOff,
21142                 argLen:         2,
21143                 faultOnNilArg0: true,
21144                 symEffect:      SymRead,
21145                 asm:            arm64.AMOVWU,
21146                 reg: regInfo{
21147                         inputs: []inputInfo{
21148                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21149                         },
21150                         outputs: []outputInfo{
21151                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21152                         },
21153                 },
21154         },
21155         {
21156                 name:           "MOVDload",
21157                 auxType:        auxSymOff,
21158                 argLen:         2,
21159                 faultOnNilArg0: true,
21160                 symEffect:      SymRead,
21161                 asm:            arm64.AMOVD,
21162                 reg: regInfo{
21163                         inputs: []inputInfo{
21164                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21165                         },
21166                         outputs: []outputInfo{
21167                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21168                         },
21169                 },
21170         },
21171         {
21172                 name:           "LDP",
21173                 auxType:        auxSymOff,
21174                 argLen:         2,
21175                 faultOnNilArg0: true,
21176                 symEffect:      SymRead,
21177                 asm:            arm64.ALDP,
21178                 reg: regInfo{
21179                         inputs: []inputInfo{
21180                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21181                         },
21182                         outputs: []outputInfo{
21183                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21184                                 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21185                         },
21186                 },
21187         },
21188         {
21189                 name:           "FMOVSload",
21190                 auxType:        auxSymOff,
21191                 argLen:         2,
21192                 faultOnNilArg0: true,
21193                 symEffect:      SymRead,
21194                 asm:            arm64.AFMOVS,
21195                 reg: regInfo{
21196                         inputs: []inputInfo{
21197                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21198                         },
21199                         outputs: []outputInfo{
21200                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21201                         },
21202                 },
21203         },
21204         {
21205                 name:           "FMOVDload",
21206                 auxType:        auxSymOff,
21207                 argLen:         2,
21208                 faultOnNilArg0: true,
21209                 symEffect:      SymRead,
21210                 asm:            arm64.AFMOVD,
21211                 reg: regInfo{
21212                         inputs: []inputInfo{
21213                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21214                         },
21215                         outputs: []outputInfo{
21216                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21217                         },
21218                 },
21219         },
21220         {
21221                 name:   "MOVDloadidx",
21222                 argLen: 3,
21223                 asm:    arm64.AMOVD,
21224                 reg: regInfo{
21225                         inputs: []inputInfo{
21226                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21227                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21228                         },
21229                         outputs: []outputInfo{
21230                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21231                         },
21232                 },
21233         },
21234         {
21235                 name:   "MOVWloadidx",
21236                 argLen: 3,
21237                 asm:    arm64.AMOVW,
21238                 reg: regInfo{
21239                         inputs: []inputInfo{
21240                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21241                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21242                         },
21243                         outputs: []outputInfo{
21244                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21245                         },
21246                 },
21247         },
21248         {
21249                 name:   "MOVWUloadidx",
21250                 argLen: 3,
21251                 asm:    arm64.AMOVWU,
21252                 reg: regInfo{
21253                         inputs: []inputInfo{
21254                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21255                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21256                         },
21257                         outputs: []outputInfo{
21258                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21259                         },
21260                 },
21261         },
21262         {
21263                 name:   "MOVHloadidx",
21264                 argLen: 3,
21265                 asm:    arm64.AMOVH,
21266                 reg: regInfo{
21267                         inputs: []inputInfo{
21268                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21269                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21270                         },
21271                         outputs: []outputInfo{
21272                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21273                         },
21274                 },
21275         },
21276         {
21277                 name:   "MOVHUloadidx",
21278                 argLen: 3,
21279                 asm:    arm64.AMOVHU,
21280                 reg: regInfo{
21281                         inputs: []inputInfo{
21282                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21283                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21284                         },
21285                         outputs: []outputInfo{
21286                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21287                         },
21288                 },
21289         },
21290         {
21291                 name:   "MOVBloadidx",
21292                 argLen: 3,
21293                 asm:    arm64.AMOVB,
21294                 reg: regInfo{
21295                         inputs: []inputInfo{
21296                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21297                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21298                         },
21299                         outputs: []outputInfo{
21300                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21301                         },
21302                 },
21303         },
21304         {
21305                 name:   "MOVBUloadidx",
21306                 argLen: 3,
21307                 asm:    arm64.AMOVBU,
21308                 reg: regInfo{
21309                         inputs: []inputInfo{
21310                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21311                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21312                         },
21313                         outputs: []outputInfo{
21314                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21315                         },
21316                 },
21317         },
21318         {
21319                 name:   "FMOVSloadidx",
21320                 argLen: 3,
21321                 asm:    arm64.AFMOVS,
21322                 reg: regInfo{
21323                         inputs: []inputInfo{
21324                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21325                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21326                         },
21327                         outputs: []outputInfo{
21328                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21329                         },
21330                 },
21331         },
21332         {
21333                 name:   "FMOVDloadidx",
21334                 argLen: 3,
21335                 asm:    arm64.AFMOVD,
21336                 reg: regInfo{
21337                         inputs: []inputInfo{
21338                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21339                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21340                         },
21341                         outputs: []outputInfo{
21342                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21343                         },
21344                 },
21345         },
21346         {
21347                 name:   "MOVHloadidx2",
21348                 argLen: 3,
21349                 asm:    arm64.AMOVH,
21350                 reg: regInfo{
21351                         inputs: []inputInfo{
21352                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21353                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21354                         },
21355                         outputs: []outputInfo{
21356                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21357                         },
21358                 },
21359         },
21360         {
21361                 name:   "MOVHUloadidx2",
21362                 argLen: 3,
21363                 asm:    arm64.AMOVHU,
21364                 reg: regInfo{
21365                         inputs: []inputInfo{
21366                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21367                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21368                         },
21369                         outputs: []outputInfo{
21370                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21371                         },
21372                 },
21373         },
21374         {
21375                 name:   "MOVWloadidx4",
21376                 argLen: 3,
21377                 asm:    arm64.AMOVW,
21378                 reg: regInfo{
21379                         inputs: []inputInfo{
21380                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21381                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21382                         },
21383                         outputs: []outputInfo{
21384                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21385                         },
21386                 },
21387         },
21388         {
21389                 name:   "MOVWUloadidx4",
21390                 argLen: 3,
21391                 asm:    arm64.AMOVWU,
21392                 reg: regInfo{
21393                         inputs: []inputInfo{
21394                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21395                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21396                         },
21397                         outputs: []outputInfo{
21398                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21399                         },
21400                 },
21401         },
21402         {
21403                 name:   "MOVDloadidx8",
21404                 argLen: 3,
21405                 asm:    arm64.AMOVD,
21406                 reg: regInfo{
21407                         inputs: []inputInfo{
21408                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21409                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21410                         },
21411                         outputs: []outputInfo{
21412                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21413                         },
21414                 },
21415         },
21416         {
21417                 name:   "FMOVSloadidx4",
21418                 argLen: 3,
21419                 asm:    arm64.AFMOVS,
21420                 reg: regInfo{
21421                         inputs: []inputInfo{
21422                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21423                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21424                         },
21425                         outputs: []outputInfo{
21426                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21427                         },
21428                 },
21429         },
21430         {
21431                 name:   "FMOVDloadidx8",
21432                 argLen: 3,
21433                 asm:    arm64.AFMOVD,
21434                 reg: regInfo{
21435                         inputs: []inputInfo{
21436                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21437                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21438                         },
21439                         outputs: []outputInfo{
21440                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21441                         },
21442                 },
21443         },
21444         {
21445                 name:           "MOVBstore",
21446                 auxType:        auxSymOff,
21447                 argLen:         3,
21448                 faultOnNilArg0: true,
21449                 symEffect:      SymWrite,
21450                 asm:            arm64.AMOVB,
21451                 reg: regInfo{
21452                         inputs: []inputInfo{
21453                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21454                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21455                         },
21456                 },
21457         },
21458         {
21459                 name:           "MOVHstore",
21460                 auxType:        auxSymOff,
21461                 argLen:         3,
21462                 faultOnNilArg0: true,
21463                 symEffect:      SymWrite,
21464                 asm:            arm64.AMOVH,
21465                 reg: regInfo{
21466                         inputs: []inputInfo{
21467                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21468                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21469                         },
21470                 },
21471         },
21472         {
21473                 name:           "MOVWstore",
21474                 auxType:        auxSymOff,
21475                 argLen:         3,
21476                 faultOnNilArg0: true,
21477                 symEffect:      SymWrite,
21478                 asm:            arm64.AMOVW,
21479                 reg: regInfo{
21480                         inputs: []inputInfo{
21481                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21482                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21483                         },
21484                 },
21485         },
21486         {
21487                 name:           "MOVDstore",
21488                 auxType:        auxSymOff,
21489                 argLen:         3,
21490                 faultOnNilArg0: true,
21491                 symEffect:      SymWrite,
21492                 asm:            arm64.AMOVD,
21493                 reg: regInfo{
21494                         inputs: []inputInfo{
21495                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21496                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21497                         },
21498                 },
21499         },
21500         {
21501                 name:           "STP",
21502                 auxType:        auxSymOff,
21503                 argLen:         4,
21504                 faultOnNilArg0: true,
21505                 symEffect:      SymWrite,
21506                 asm:            arm64.ASTP,
21507                 reg: regInfo{
21508                         inputs: []inputInfo{
21509                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21510                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21511                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21512                         },
21513                 },
21514         },
21515         {
21516                 name:           "FMOVSstore",
21517                 auxType:        auxSymOff,
21518                 argLen:         3,
21519                 faultOnNilArg0: true,
21520                 symEffect:      SymWrite,
21521                 asm:            arm64.AFMOVS,
21522                 reg: regInfo{
21523                         inputs: []inputInfo{
21524                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21525                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21526                         },
21527                 },
21528         },
21529         {
21530                 name:           "FMOVDstore",
21531                 auxType:        auxSymOff,
21532                 argLen:         3,
21533                 faultOnNilArg0: true,
21534                 symEffect:      SymWrite,
21535                 asm:            arm64.AFMOVD,
21536                 reg: regInfo{
21537                         inputs: []inputInfo{
21538                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21539                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21540                         },
21541                 },
21542         },
21543         {
21544                 name:   "MOVBstoreidx",
21545                 argLen: 4,
21546                 asm:    arm64.AMOVB,
21547                 reg: regInfo{
21548                         inputs: []inputInfo{
21549                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21550                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21551                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21552                         },
21553                 },
21554         },
21555         {
21556                 name:   "MOVHstoreidx",
21557                 argLen: 4,
21558                 asm:    arm64.AMOVH,
21559                 reg: regInfo{
21560                         inputs: []inputInfo{
21561                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21562                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21563                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21564                         },
21565                 },
21566         },
21567         {
21568                 name:   "MOVWstoreidx",
21569                 argLen: 4,
21570                 asm:    arm64.AMOVW,
21571                 reg: regInfo{
21572                         inputs: []inputInfo{
21573                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21574                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21575                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21576                         },
21577                 },
21578         },
21579         {
21580                 name:   "MOVDstoreidx",
21581                 argLen: 4,
21582                 asm:    arm64.AMOVD,
21583                 reg: regInfo{
21584                         inputs: []inputInfo{
21585                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21586                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21587                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21588                         },
21589                 },
21590         },
21591         {
21592                 name:   "FMOVSstoreidx",
21593                 argLen: 4,
21594                 asm:    arm64.AFMOVS,
21595                 reg: regInfo{
21596                         inputs: []inputInfo{
21597                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21598                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21599                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21600                         },
21601                 },
21602         },
21603         {
21604                 name:   "FMOVDstoreidx",
21605                 argLen: 4,
21606                 asm:    arm64.AFMOVD,
21607                 reg: regInfo{
21608                         inputs: []inputInfo{
21609                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21610                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21611                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21612                         },
21613                 },
21614         },
21615         {
21616                 name:   "MOVHstoreidx2",
21617                 argLen: 4,
21618                 asm:    arm64.AMOVH,
21619                 reg: regInfo{
21620                         inputs: []inputInfo{
21621                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21622                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21623                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21624                         },
21625                 },
21626         },
21627         {
21628                 name:   "MOVWstoreidx4",
21629                 argLen: 4,
21630                 asm:    arm64.AMOVW,
21631                 reg: regInfo{
21632                         inputs: []inputInfo{
21633                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21634                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21635                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21636                         },
21637                 },
21638         },
21639         {
21640                 name:   "MOVDstoreidx8",
21641                 argLen: 4,
21642                 asm:    arm64.AMOVD,
21643                 reg: regInfo{
21644                         inputs: []inputInfo{
21645                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21646                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21647                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21648                         },
21649                 },
21650         },
21651         {
21652                 name:   "FMOVSstoreidx4",
21653                 argLen: 4,
21654                 asm:    arm64.AFMOVS,
21655                 reg: regInfo{
21656                         inputs: []inputInfo{
21657                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21658                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21659                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21660                         },
21661                 },
21662         },
21663         {
21664                 name:   "FMOVDstoreidx8",
21665                 argLen: 4,
21666                 asm:    arm64.AFMOVD,
21667                 reg: regInfo{
21668                         inputs: []inputInfo{
21669                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21670                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21671                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21672                         },
21673                 },
21674         },
21675         {
21676                 name:           "MOVBstorezero",
21677                 auxType:        auxSymOff,
21678                 argLen:         2,
21679                 faultOnNilArg0: true,
21680                 symEffect:      SymWrite,
21681                 asm:            arm64.AMOVB,
21682                 reg: regInfo{
21683                         inputs: []inputInfo{
21684                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21685                         },
21686                 },
21687         },
21688         {
21689                 name:           "MOVHstorezero",
21690                 auxType:        auxSymOff,
21691                 argLen:         2,
21692                 faultOnNilArg0: true,
21693                 symEffect:      SymWrite,
21694                 asm:            arm64.AMOVH,
21695                 reg: regInfo{
21696                         inputs: []inputInfo{
21697                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21698                         },
21699                 },
21700         },
21701         {
21702                 name:           "MOVWstorezero",
21703                 auxType:        auxSymOff,
21704                 argLen:         2,
21705                 faultOnNilArg0: true,
21706                 symEffect:      SymWrite,
21707                 asm:            arm64.AMOVW,
21708                 reg: regInfo{
21709                         inputs: []inputInfo{
21710                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21711                         },
21712                 },
21713         },
21714         {
21715                 name:           "MOVDstorezero",
21716                 auxType:        auxSymOff,
21717                 argLen:         2,
21718                 faultOnNilArg0: true,
21719                 symEffect:      SymWrite,
21720                 asm:            arm64.AMOVD,
21721                 reg: regInfo{
21722                         inputs: []inputInfo{
21723                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21724                         },
21725                 },
21726         },
21727         {
21728                 name:           "MOVQstorezero",
21729                 auxType:        auxSymOff,
21730                 argLen:         2,
21731                 faultOnNilArg0: true,
21732                 symEffect:      SymWrite,
21733                 asm:            arm64.ASTP,
21734                 reg: regInfo{
21735                         inputs: []inputInfo{
21736                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21737                         },
21738                 },
21739         },
21740         {
21741                 name:   "MOVBstorezeroidx",
21742                 argLen: 3,
21743                 asm:    arm64.AMOVB,
21744                 reg: regInfo{
21745                         inputs: []inputInfo{
21746                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21747                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21748                         },
21749                 },
21750         },
21751         {
21752                 name:   "MOVHstorezeroidx",
21753                 argLen: 3,
21754                 asm:    arm64.AMOVH,
21755                 reg: regInfo{
21756                         inputs: []inputInfo{
21757                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21758                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21759                         },
21760                 },
21761         },
21762         {
21763                 name:   "MOVWstorezeroidx",
21764                 argLen: 3,
21765                 asm:    arm64.AMOVW,
21766                 reg: regInfo{
21767                         inputs: []inputInfo{
21768                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21769                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21770                         },
21771                 },
21772         },
21773         {
21774                 name:   "MOVDstorezeroidx",
21775                 argLen: 3,
21776                 asm:    arm64.AMOVD,
21777                 reg: regInfo{
21778                         inputs: []inputInfo{
21779                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21780                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21781                         },
21782                 },
21783         },
21784         {
21785                 name:   "MOVHstorezeroidx2",
21786                 argLen: 3,
21787                 asm:    arm64.AMOVH,
21788                 reg: regInfo{
21789                         inputs: []inputInfo{
21790                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21791                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21792                         },
21793                 },
21794         },
21795         {
21796                 name:   "MOVWstorezeroidx4",
21797                 argLen: 3,
21798                 asm:    arm64.AMOVW,
21799                 reg: regInfo{
21800                         inputs: []inputInfo{
21801                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21802                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21803                         },
21804                 },
21805         },
21806         {
21807                 name:   "MOVDstorezeroidx8",
21808                 argLen: 3,
21809                 asm:    arm64.AMOVD,
21810                 reg: regInfo{
21811                         inputs: []inputInfo{
21812                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21813                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21814                         },
21815                 },
21816         },
21817         {
21818                 name:   "FMOVDgpfp",
21819                 argLen: 1,
21820                 asm:    arm64.AFMOVD,
21821                 reg: regInfo{
21822                         inputs: []inputInfo{
21823                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21824                         },
21825                         outputs: []outputInfo{
21826                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21827                         },
21828                 },
21829         },
21830         {
21831                 name:   "FMOVDfpgp",
21832                 argLen: 1,
21833                 asm:    arm64.AFMOVD,
21834                 reg: regInfo{
21835                         inputs: []inputInfo{
21836                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21837                         },
21838                         outputs: []outputInfo{
21839                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21840                         },
21841                 },
21842         },
21843         {
21844                 name:   "FMOVSgpfp",
21845                 argLen: 1,
21846                 asm:    arm64.AFMOVS,
21847                 reg: regInfo{
21848                         inputs: []inputInfo{
21849                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21850                         },
21851                         outputs: []outputInfo{
21852                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21853                         },
21854                 },
21855         },
21856         {
21857                 name:   "FMOVSfpgp",
21858                 argLen: 1,
21859                 asm:    arm64.AFMOVS,
21860                 reg: regInfo{
21861                         inputs: []inputInfo{
21862                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21863                         },
21864                         outputs: []outputInfo{
21865                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21866                         },
21867                 },
21868         },
21869         {
21870                 name:   "MOVBreg",
21871                 argLen: 1,
21872                 asm:    arm64.AMOVB,
21873                 reg: regInfo{
21874                         inputs: []inputInfo{
21875                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21876                         },
21877                         outputs: []outputInfo{
21878                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21879                         },
21880                 },
21881         },
21882         {
21883                 name:   "MOVBUreg",
21884                 argLen: 1,
21885                 asm:    arm64.AMOVBU,
21886                 reg: regInfo{
21887                         inputs: []inputInfo{
21888                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21889                         },
21890                         outputs: []outputInfo{
21891                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21892                         },
21893                 },
21894         },
21895         {
21896                 name:   "MOVHreg",
21897                 argLen: 1,
21898                 asm:    arm64.AMOVH,
21899                 reg: regInfo{
21900                         inputs: []inputInfo{
21901                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21902                         },
21903                         outputs: []outputInfo{
21904                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21905                         },
21906                 },
21907         },
21908         {
21909                 name:   "MOVHUreg",
21910                 argLen: 1,
21911                 asm:    arm64.AMOVHU,
21912                 reg: regInfo{
21913                         inputs: []inputInfo{
21914                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21915                         },
21916                         outputs: []outputInfo{
21917                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21918                         },
21919                 },
21920         },
21921         {
21922                 name:   "MOVWreg",
21923                 argLen: 1,
21924                 asm:    arm64.AMOVW,
21925                 reg: regInfo{
21926                         inputs: []inputInfo{
21927                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21928                         },
21929                         outputs: []outputInfo{
21930                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21931                         },
21932                 },
21933         },
21934         {
21935                 name:   "MOVWUreg",
21936                 argLen: 1,
21937                 asm:    arm64.AMOVWU,
21938                 reg: regInfo{
21939                         inputs: []inputInfo{
21940                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21941                         },
21942                         outputs: []outputInfo{
21943                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21944                         },
21945                 },
21946         },
21947         {
21948                 name:   "MOVDreg",
21949                 argLen: 1,
21950                 asm:    arm64.AMOVD,
21951                 reg: regInfo{
21952                         inputs: []inputInfo{
21953                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21954                         },
21955                         outputs: []outputInfo{
21956                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21957                         },
21958                 },
21959         },
21960         {
21961                 name:         "MOVDnop",
21962                 argLen:       1,
21963                 resultInArg0: true,
21964                 reg: regInfo{
21965                         inputs: []inputInfo{
21966                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21967                         },
21968                         outputs: []outputInfo{
21969                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21970                         },
21971                 },
21972         },
21973         {
21974                 name:   "SCVTFWS",
21975                 argLen: 1,
21976                 asm:    arm64.ASCVTFWS,
21977                 reg: regInfo{
21978                         inputs: []inputInfo{
21979                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21980                         },
21981                         outputs: []outputInfo{
21982                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21983                         },
21984                 },
21985         },
21986         {
21987                 name:   "SCVTFWD",
21988                 argLen: 1,
21989                 asm:    arm64.ASCVTFWD,
21990                 reg: regInfo{
21991                         inputs: []inputInfo{
21992                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21993                         },
21994                         outputs: []outputInfo{
21995                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21996                         },
21997                 },
21998         },
21999         {
22000                 name:   "UCVTFWS",
22001                 argLen: 1,
22002                 asm:    arm64.AUCVTFWS,
22003                 reg: regInfo{
22004                         inputs: []inputInfo{
22005                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22006                         },
22007                         outputs: []outputInfo{
22008                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22009                         },
22010                 },
22011         },
22012         {
22013                 name:   "UCVTFWD",
22014                 argLen: 1,
22015                 asm:    arm64.AUCVTFWD,
22016                 reg: regInfo{
22017                         inputs: []inputInfo{
22018                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22019                         },
22020                         outputs: []outputInfo{
22021                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22022                         },
22023                 },
22024         },
22025         {
22026                 name:   "SCVTFS",
22027                 argLen: 1,
22028                 asm:    arm64.ASCVTFS,
22029                 reg: regInfo{
22030                         inputs: []inputInfo{
22031                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22032                         },
22033                         outputs: []outputInfo{
22034                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22035                         },
22036                 },
22037         },
22038         {
22039                 name:   "SCVTFD",
22040                 argLen: 1,
22041                 asm:    arm64.ASCVTFD,
22042                 reg: regInfo{
22043                         inputs: []inputInfo{
22044                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22045                         },
22046                         outputs: []outputInfo{
22047                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22048                         },
22049                 },
22050         },
22051         {
22052                 name:   "UCVTFS",
22053                 argLen: 1,
22054                 asm:    arm64.AUCVTFS,
22055                 reg: regInfo{
22056                         inputs: []inputInfo{
22057                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22058                         },
22059                         outputs: []outputInfo{
22060                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22061                         },
22062                 },
22063         },
22064         {
22065                 name:   "UCVTFD",
22066                 argLen: 1,
22067                 asm:    arm64.AUCVTFD,
22068                 reg: regInfo{
22069                         inputs: []inputInfo{
22070                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22071                         },
22072                         outputs: []outputInfo{
22073                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22074                         },
22075                 },
22076         },
22077         {
22078                 name:   "FCVTZSSW",
22079                 argLen: 1,
22080                 asm:    arm64.AFCVTZSSW,
22081                 reg: regInfo{
22082                         inputs: []inputInfo{
22083                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22084                         },
22085                         outputs: []outputInfo{
22086                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22087                         },
22088                 },
22089         },
22090         {
22091                 name:   "FCVTZSDW",
22092                 argLen: 1,
22093                 asm:    arm64.AFCVTZSDW,
22094                 reg: regInfo{
22095                         inputs: []inputInfo{
22096                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22097                         },
22098                         outputs: []outputInfo{
22099                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22100                         },
22101                 },
22102         },
22103         {
22104                 name:   "FCVTZUSW",
22105                 argLen: 1,
22106                 asm:    arm64.AFCVTZUSW,
22107                 reg: regInfo{
22108                         inputs: []inputInfo{
22109                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22110                         },
22111                         outputs: []outputInfo{
22112                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22113                         },
22114                 },
22115         },
22116         {
22117                 name:   "FCVTZUDW",
22118                 argLen: 1,
22119                 asm:    arm64.AFCVTZUDW,
22120                 reg: regInfo{
22121                         inputs: []inputInfo{
22122                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22123                         },
22124                         outputs: []outputInfo{
22125                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22126                         },
22127                 },
22128         },
22129         {
22130                 name:   "FCVTZSS",
22131                 argLen: 1,
22132                 asm:    arm64.AFCVTZSS,
22133                 reg: regInfo{
22134                         inputs: []inputInfo{
22135                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22136                         },
22137                         outputs: []outputInfo{
22138                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22139                         },
22140                 },
22141         },
22142         {
22143                 name:   "FCVTZSD",
22144                 argLen: 1,
22145                 asm:    arm64.AFCVTZSD,
22146                 reg: regInfo{
22147                         inputs: []inputInfo{
22148                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22149                         },
22150                         outputs: []outputInfo{
22151                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22152                         },
22153                 },
22154         },
22155         {
22156                 name:   "FCVTZUS",
22157                 argLen: 1,
22158                 asm:    arm64.AFCVTZUS,
22159                 reg: regInfo{
22160                         inputs: []inputInfo{
22161                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22162                         },
22163                         outputs: []outputInfo{
22164                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22165                         },
22166                 },
22167         },
22168         {
22169                 name:   "FCVTZUD",
22170                 argLen: 1,
22171                 asm:    arm64.AFCVTZUD,
22172                 reg: regInfo{
22173                         inputs: []inputInfo{
22174                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22175                         },
22176                         outputs: []outputInfo{
22177                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22178                         },
22179                 },
22180         },
22181         {
22182                 name:   "FCVTSD",
22183                 argLen: 1,
22184                 asm:    arm64.AFCVTSD,
22185                 reg: regInfo{
22186                         inputs: []inputInfo{
22187                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22188                         },
22189                         outputs: []outputInfo{
22190                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22191                         },
22192                 },
22193         },
22194         {
22195                 name:   "FCVTDS",
22196                 argLen: 1,
22197                 asm:    arm64.AFCVTDS,
22198                 reg: regInfo{
22199                         inputs: []inputInfo{
22200                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22201                         },
22202                         outputs: []outputInfo{
22203                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22204                         },
22205                 },
22206         },
22207         {
22208                 name:   "FRINTAD",
22209                 argLen: 1,
22210                 asm:    arm64.AFRINTAD,
22211                 reg: regInfo{
22212                         inputs: []inputInfo{
22213                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22214                         },
22215                         outputs: []outputInfo{
22216                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22217                         },
22218                 },
22219         },
22220         {
22221                 name:   "FRINTMD",
22222                 argLen: 1,
22223                 asm:    arm64.AFRINTMD,
22224                 reg: regInfo{
22225                         inputs: []inputInfo{
22226                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22227                         },
22228                         outputs: []outputInfo{
22229                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22230                         },
22231                 },
22232         },
22233         {
22234                 name:   "FRINTND",
22235                 argLen: 1,
22236                 asm:    arm64.AFRINTND,
22237                 reg: regInfo{
22238                         inputs: []inputInfo{
22239                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22240                         },
22241                         outputs: []outputInfo{
22242                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22243                         },
22244                 },
22245         },
22246         {
22247                 name:   "FRINTPD",
22248                 argLen: 1,
22249                 asm:    arm64.AFRINTPD,
22250                 reg: regInfo{
22251                         inputs: []inputInfo{
22252                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22253                         },
22254                         outputs: []outputInfo{
22255                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22256                         },
22257                 },
22258         },
22259         {
22260                 name:   "FRINTZD",
22261                 argLen: 1,
22262                 asm:    arm64.AFRINTZD,
22263                 reg: regInfo{
22264                         inputs: []inputInfo{
22265                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22266                         },
22267                         outputs: []outputInfo{
22268                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22269                         },
22270                 },
22271         },
22272         {
22273                 name:    "CSEL",
22274                 auxType: auxCCop,
22275                 argLen:  3,
22276                 asm:     arm64.ACSEL,
22277                 reg: regInfo{
22278                         inputs: []inputInfo{
22279                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22280                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22281                         },
22282                         outputs: []outputInfo{
22283                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22284                         },
22285                 },
22286         },
22287         {
22288                 name:    "CSEL0",
22289                 auxType: auxCCop,
22290                 argLen:  2,
22291                 asm:     arm64.ACSEL,
22292                 reg: regInfo{
22293                         inputs: []inputInfo{
22294                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22295                         },
22296                         outputs: []outputInfo{
22297                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22298                         },
22299                 },
22300         },
22301         {
22302                 name:    "CSINC",
22303                 auxType: auxCCop,
22304                 argLen:  3,
22305                 asm:     arm64.ACSINC,
22306                 reg: regInfo{
22307                         inputs: []inputInfo{
22308                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22309                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22310                         },
22311                         outputs: []outputInfo{
22312                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22313                         },
22314                 },
22315         },
22316         {
22317                 name:    "CSINV",
22318                 auxType: auxCCop,
22319                 argLen:  3,
22320                 asm:     arm64.ACSINV,
22321                 reg: regInfo{
22322                         inputs: []inputInfo{
22323                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22324                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22325                         },
22326                         outputs: []outputInfo{
22327                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22328                         },
22329                 },
22330         },
22331         {
22332                 name:    "CSNEG",
22333                 auxType: auxCCop,
22334                 argLen:  3,
22335                 asm:     arm64.ACSNEG,
22336                 reg: regInfo{
22337                         inputs: []inputInfo{
22338                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22339                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22340                         },
22341                         outputs: []outputInfo{
22342                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22343                         },
22344                 },
22345         },
22346         {
22347                 name:    "CSETM",
22348                 auxType: auxCCop,
22349                 argLen:  1,
22350                 asm:     arm64.ACSETM,
22351                 reg: regInfo{
22352                         outputs: []outputInfo{
22353                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22354                         },
22355                 },
22356         },
22357         {
22358                 name:         "CALLstatic",
22359                 auxType:      auxCallOff,
22360                 argLen:       -1,
22361                 clobberFlags: true,
22362                 call:         true,
22363                 reg: regInfo{
22364                         clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22365                 },
22366         },
22367         {
22368                 name:         "CALLtail",
22369                 auxType:      auxCallOff,
22370                 argLen:       -1,
22371                 clobberFlags: true,
22372                 call:         true,
22373                 tailCall:     true,
22374                 reg: regInfo{
22375                         clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22376                 },
22377         },
22378         {
22379                 name:         "CALLclosure",
22380                 auxType:      auxCallOff,
22381                 argLen:       -1,
22382                 clobberFlags: true,
22383                 call:         true,
22384                 reg: regInfo{
22385                         inputs: []inputInfo{
22386                                 {1, 67108864},   // R26
22387                                 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
22388                         },
22389                         clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22390                 },
22391         },
22392         {
22393                 name:         "CALLinter",
22394                 auxType:      auxCallOff,
22395                 argLen:       -1,
22396                 clobberFlags: true,
22397                 call:         true,
22398                 reg: regInfo{
22399                         inputs: []inputInfo{
22400                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22401                         },
22402                         clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
22403                 },
22404         },
22405         {
22406                 name:           "LoweredNilCheck",
22407                 argLen:         2,
22408                 nilCheck:       true,
22409                 faultOnNilArg0: true,
22410                 reg: regInfo{
22411                         inputs: []inputInfo{
22412                                 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22413                         },
22414                 },
22415         },
22416         {
22417                 name:   "Equal",
22418                 argLen: 1,
22419                 reg: regInfo{
22420                         outputs: []outputInfo{
22421                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22422                         },
22423                 },
22424         },
22425         {
22426                 name:   "NotEqual",
22427                 argLen: 1,
22428                 reg: regInfo{
22429                         outputs: []outputInfo{
22430                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22431                         },
22432                 },
22433         },
22434         {
22435                 name:   "LessThan",
22436                 argLen: 1,
22437                 reg: regInfo{
22438                         outputs: []outputInfo{
22439                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22440                         },
22441                 },
22442         },
22443         {
22444                 name:   "LessEqual",
22445                 argLen: 1,
22446                 reg: regInfo{
22447                         outputs: []outputInfo{
22448                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22449                         },
22450                 },
22451         },
22452         {
22453                 name:   "GreaterThan",
22454                 argLen: 1,
22455                 reg: regInfo{
22456                         outputs: []outputInfo{
22457                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22458                         },
22459                 },
22460         },
22461         {
22462                 name:   "GreaterEqual",
22463                 argLen: 1,
22464                 reg: regInfo{
22465                         outputs: []outputInfo{
22466                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22467                         },
22468                 },
22469         },
22470         {
22471                 name:   "LessThanU",
22472                 argLen: 1,
22473                 reg: regInfo{
22474                         outputs: []outputInfo{
22475                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22476                         },
22477                 },
22478         },
22479         {
22480                 name:   "LessEqualU",
22481                 argLen: 1,
22482                 reg: regInfo{
22483                         outputs: []outputInfo{
22484                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22485                         },
22486                 },
22487         },
22488         {
22489                 name:   "GreaterThanU",
22490                 argLen: 1,
22491                 reg: regInfo{
22492                         outputs: []outputInfo{
22493                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22494                         },
22495                 },
22496         },
22497         {
22498                 name:   "GreaterEqualU",
22499                 argLen: 1,
22500                 reg: regInfo{
22501                         outputs: []outputInfo{
22502                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22503                         },
22504                 },
22505         },
22506         {
22507                 name:   "LessThanF",
22508                 argLen: 1,
22509                 reg: regInfo{
22510                         outputs: []outputInfo{
22511                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22512                         },
22513                 },
22514         },
22515         {
22516                 name:   "LessEqualF",
22517                 argLen: 1,
22518                 reg: regInfo{
22519                         outputs: []outputInfo{
22520                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22521                         },
22522                 },
22523         },
22524         {
22525                 name:   "GreaterThanF",
22526                 argLen: 1,
22527                 reg: regInfo{
22528                         outputs: []outputInfo{
22529                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22530                         },
22531                 },
22532         },
22533         {
22534                 name:   "GreaterEqualF",
22535                 argLen: 1,
22536                 reg: regInfo{
22537                         outputs: []outputInfo{
22538                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22539                         },
22540                 },
22541         },
22542         {
22543                 name:   "NotLessThanF",
22544                 argLen: 1,
22545                 reg: regInfo{
22546                         outputs: []outputInfo{
22547                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22548                         },
22549                 },
22550         },
22551         {
22552                 name:   "NotLessEqualF",
22553                 argLen: 1,
22554                 reg: regInfo{
22555                         outputs: []outputInfo{
22556                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22557                         },
22558                 },
22559         },
22560         {
22561                 name:   "NotGreaterThanF",
22562                 argLen: 1,
22563                 reg: regInfo{
22564                         outputs: []outputInfo{
22565                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22566                         },
22567                 },
22568         },
22569         {
22570                 name:   "NotGreaterEqualF",
22571                 argLen: 1,
22572                 reg: regInfo{
22573                         outputs: []outputInfo{
22574                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22575                         },
22576                 },
22577         },
22578         {
22579                 name:   "LessThanNoov",
22580                 argLen: 1,
22581                 reg: regInfo{
22582                         outputs: []outputInfo{
22583                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22584                         },
22585                 },
22586         },
22587         {
22588                 name:   "GreaterEqualNoov",
22589                 argLen: 1,
22590                 reg: regInfo{
22591                         outputs: []outputInfo{
22592                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22593                         },
22594                 },
22595         },
22596         {
22597                 name:           "DUFFZERO",
22598                 auxType:        auxInt64,
22599                 argLen:         2,
22600                 faultOnNilArg0: true,
22601                 unsafePoint:    true,
22602                 reg: regInfo{
22603                         inputs: []inputInfo{
22604                                 {0, 1048576}, // R20
22605                         },
22606                         clobbers: 538116096, // R16 R17 R20 R30
22607                 },
22608         },
22609         {
22610                 name:           "LoweredZero",
22611                 argLen:         3,
22612                 clobberFlags:   true,
22613                 faultOnNilArg0: true,
22614                 reg: regInfo{
22615                         inputs: []inputInfo{
22616                                 {0, 65536},     // R16
22617                                 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22618                         },
22619                         clobbers: 65536, // R16
22620                 },
22621         },
22622         {
22623                 name:           "DUFFCOPY",
22624                 auxType:        auxInt64,
22625                 argLen:         3,
22626                 faultOnNilArg0: true,
22627                 faultOnNilArg1: true,
22628                 unsafePoint:    true,
22629                 reg: regInfo{
22630                         inputs: []inputInfo{
22631                                 {0, 2097152}, // R21
22632                                 {1, 1048576}, // R20
22633                         },
22634                         clobbers: 607322112, // R16 R17 R20 R21 R26 R30
22635                 },
22636         },
22637         {
22638                 name:           "LoweredMove",
22639                 argLen:         4,
22640                 clobberFlags:   true,
22641                 faultOnNilArg0: true,
22642                 faultOnNilArg1: true,
22643                 reg: regInfo{
22644                         inputs: []inputInfo{
22645                                 {0, 131072},    // R17
22646                                 {1, 65536},     // R16
22647                                 {2, 637272063}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
22648                         },
22649                         clobbers: 33751040, // R16 R17 R25
22650                 },
22651         },
22652         {
22653                 name:      "LoweredGetClosurePtr",
22654                 argLen:    0,
22655                 zeroWidth: true,
22656                 reg: regInfo{
22657                         outputs: []outputInfo{
22658                                 {0, 67108864}, // R26
22659                         },
22660                 },
22661         },
22662         {
22663                 name:              "LoweredGetCallerSP",
22664                 argLen:            1,
22665                 rematerializeable: true,
22666                 reg: regInfo{
22667                         outputs: []outputInfo{
22668                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22669                         },
22670                 },
22671         },
22672         {
22673                 name:              "LoweredGetCallerPC",
22674                 argLen:            0,
22675                 rematerializeable: true,
22676                 reg: regInfo{
22677                         outputs: []outputInfo{
22678                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22679                         },
22680                 },
22681         },
22682         {
22683                 name:    "FlagConstant",
22684                 auxType: auxFlagConstant,
22685                 argLen:  0,
22686                 reg:     regInfo{},
22687         },
22688         {
22689                 name:   "InvertFlags",
22690                 argLen: 1,
22691                 reg:    regInfo{},
22692         },
22693         {
22694                 name:           "LDAR",
22695                 argLen:         2,
22696                 faultOnNilArg0: true,
22697                 asm:            arm64.ALDAR,
22698                 reg: regInfo{
22699                         inputs: []inputInfo{
22700                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22701                         },
22702                         outputs: []outputInfo{
22703                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22704                         },
22705                 },
22706         },
22707         {
22708                 name:           "LDARB",
22709                 argLen:         2,
22710                 faultOnNilArg0: true,
22711                 asm:            arm64.ALDARB,
22712                 reg: regInfo{
22713                         inputs: []inputInfo{
22714                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22715                         },
22716                         outputs: []outputInfo{
22717                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22718                         },
22719                 },
22720         },
22721         {
22722                 name:           "LDARW",
22723                 argLen:         2,
22724                 faultOnNilArg0: true,
22725                 asm:            arm64.ALDARW,
22726                 reg: regInfo{
22727                         inputs: []inputInfo{
22728                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22729                         },
22730                         outputs: []outputInfo{
22731                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22732                         },
22733                 },
22734         },
22735         {
22736                 name:           "STLRB",
22737                 argLen:         3,
22738                 faultOnNilArg0: true,
22739                 hasSideEffects: true,
22740                 asm:            arm64.ASTLRB,
22741                 reg: regInfo{
22742                         inputs: []inputInfo{
22743                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22744                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22745                         },
22746                 },
22747         },
22748         {
22749                 name:           "STLR",
22750                 argLen:         3,
22751                 faultOnNilArg0: true,
22752                 hasSideEffects: true,
22753                 asm:            arm64.ASTLR,
22754                 reg: regInfo{
22755                         inputs: []inputInfo{
22756                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22757                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22758                         },
22759                 },
22760         },
22761         {
22762                 name:           "STLRW",
22763                 argLen:         3,
22764                 faultOnNilArg0: true,
22765                 hasSideEffects: true,
22766                 asm:            arm64.ASTLRW,
22767                 reg: regInfo{
22768                         inputs: []inputInfo{
22769                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22770                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22771                         },
22772                 },
22773         },
22774         {
22775                 name:            "LoweredAtomicExchange64",
22776                 argLen:          3,
22777                 resultNotInArgs: true,
22778                 faultOnNilArg0:  true,
22779                 hasSideEffects:  true,
22780                 unsafePoint:     true,
22781                 reg: regInfo{
22782                         inputs: []inputInfo{
22783                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22784                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22785                         },
22786                         outputs: []outputInfo{
22787                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22788                         },
22789                 },
22790         },
22791         {
22792                 name:            "LoweredAtomicExchange32",
22793                 argLen:          3,
22794                 resultNotInArgs: true,
22795                 faultOnNilArg0:  true,
22796                 hasSideEffects:  true,
22797                 unsafePoint:     true,
22798                 reg: regInfo{
22799                         inputs: []inputInfo{
22800                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22801                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22802                         },
22803                         outputs: []outputInfo{
22804                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22805                         },
22806                 },
22807         },
22808         {
22809                 name:            "LoweredAtomicExchange64Variant",
22810                 argLen:          3,
22811                 resultNotInArgs: true,
22812                 faultOnNilArg0:  true,
22813                 hasSideEffects:  true,
22814                 reg: regInfo{
22815                         inputs: []inputInfo{
22816                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22817                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22818                         },
22819                         outputs: []outputInfo{
22820                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22821                         },
22822                 },
22823         },
22824         {
22825                 name:            "LoweredAtomicExchange32Variant",
22826                 argLen:          3,
22827                 resultNotInArgs: true,
22828                 faultOnNilArg0:  true,
22829                 hasSideEffects:  true,
22830                 reg: regInfo{
22831                         inputs: []inputInfo{
22832                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22833                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22834                         },
22835                         outputs: []outputInfo{
22836                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22837                         },
22838                 },
22839         },
22840         {
22841                 name:            "LoweredAtomicAdd64",
22842                 argLen:          3,
22843                 resultNotInArgs: true,
22844                 faultOnNilArg0:  true,
22845                 hasSideEffects:  true,
22846                 unsafePoint:     true,
22847                 reg: regInfo{
22848                         inputs: []inputInfo{
22849                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22850                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22851                         },
22852                         outputs: []outputInfo{
22853                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22854                         },
22855                 },
22856         },
22857         {
22858                 name:            "LoweredAtomicAdd32",
22859                 argLen:          3,
22860                 resultNotInArgs: true,
22861                 faultOnNilArg0:  true,
22862                 hasSideEffects:  true,
22863                 unsafePoint:     true,
22864                 reg: regInfo{
22865                         inputs: []inputInfo{
22866                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22867                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22868                         },
22869                         outputs: []outputInfo{
22870                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22871                         },
22872                 },
22873         },
22874         {
22875                 name:            "LoweredAtomicAdd64Variant",
22876                 argLen:          3,
22877                 resultNotInArgs: true,
22878                 faultOnNilArg0:  true,
22879                 hasSideEffects:  true,
22880                 reg: regInfo{
22881                         inputs: []inputInfo{
22882                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22883                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22884                         },
22885                         outputs: []outputInfo{
22886                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22887                         },
22888                 },
22889         },
22890         {
22891                 name:            "LoweredAtomicAdd32Variant",
22892                 argLen:          3,
22893                 resultNotInArgs: true,
22894                 faultOnNilArg0:  true,
22895                 hasSideEffects:  true,
22896                 reg: regInfo{
22897                         inputs: []inputInfo{
22898                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22899                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22900                         },
22901                         outputs: []outputInfo{
22902                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22903                         },
22904                 },
22905         },
22906         {
22907                 name:            "LoweredAtomicCas64",
22908                 argLen:          4,
22909                 resultNotInArgs: true,
22910                 clobberFlags:    true,
22911                 faultOnNilArg0:  true,
22912                 hasSideEffects:  true,
22913                 unsafePoint:     true,
22914                 reg: regInfo{
22915                         inputs: []inputInfo{
22916                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22917                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22918                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22919                         },
22920                         outputs: []outputInfo{
22921                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22922                         },
22923                 },
22924         },
22925         {
22926                 name:            "LoweredAtomicCas32",
22927                 argLen:          4,
22928                 resultNotInArgs: true,
22929                 clobberFlags:    true,
22930                 faultOnNilArg0:  true,
22931                 hasSideEffects:  true,
22932                 unsafePoint:     true,
22933                 reg: regInfo{
22934                         inputs: []inputInfo{
22935                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22936                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22937                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22938                         },
22939                         outputs: []outputInfo{
22940                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22941                         },
22942                 },
22943         },
22944         {
22945                 name:            "LoweredAtomicCas64Variant",
22946                 argLen:          4,
22947                 resultNotInArgs: true,
22948                 clobberFlags:    true,
22949                 faultOnNilArg0:  true,
22950                 hasSideEffects:  true,
22951                 unsafePoint:     true,
22952                 reg: regInfo{
22953                         inputs: []inputInfo{
22954                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22955                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22956                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22957                         },
22958                         outputs: []outputInfo{
22959                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22960                         },
22961                 },
22962         },
22963         {
22964                 name:            "LoweredAtomicCas32Variant",
22965                 argLen:          4,
22966                 resultNotInArgs: true,
22967                 clobberFlags:    true,
22968                 faultOnNilArg0:  true,
22969                 hasSideEffects:  true,
22970                 unsafePoint:     true,
22971                 reg: regInfo{
22972                         inputs: []inputInfo{
22973                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22974                                 {2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22975                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22976                         },
22977                         outputs: []outputInfo{
22978                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22979                         },
22980                 },
22981         },
22982         {
22983                 name:            "LoweredAtomicAnd8",
22984                 argLen:          3,
22985                 resultNotInArgs: true,
22986                 faultOnNilArg0:  true,
22987                 hasSideEffects:  true,
22988                 unsafePoint:     true,
22989                 asm:             arm64.AAND,
22990                 reg: regInfo{
22991                         inputs: []inputInfo{
22992                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
22993                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
22994                         },
22995                         outputs: []outputInfo{
22996                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
22997                         },
22998                 },
22999         },
23000         {
23001                 name:            "LoweredAtomicAnd32",
23002                 argLen:          3,
23003                 resultNotInArgs: true,
23004                 faultOnNilArg0:  true,
23005                 hasSideEffects:  true,
23006                 unsafePoint:     true,
23007                 asm:             arm64.AAND,
23008                 reg: regInfo{
23009                         inputs: []inputInfo{
23010                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23011                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23012                         },
23013                         outputs: []outputInfo{
23014                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23015                         },
23016                 },
23017         },
23018         {
23019                 name:            "LoweredAtomicOr8",
23020                 argLen:          3,
23021                 resultNotInArgs: true,
23022                 faultOnNilArg0:  true,
23023                 hasSideEffects:  true,
23024                 unsafePoint:     true,
23025                 asm:             arm64.AORR,
23026                 reg: regInfo{
23027                         inputs: []inputInfo{
23028                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23029                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23030                         },
23031                         outputs: []outputInfo{
23032                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23033                         },
23034                 },
23035         },
23036         {
23037                 name:            "LoweredAtomicOr32",
23038                 argLen:          3,
23039                 resultNotInArgs: true,
23040                 faultOnNilArg0:  true,
23041                 hasSideEffects:  true,
23042                 unsafePoint:     true,
23043                 asm:             arm64.AORR,
23044                 reg: regInfo{
23045                         inputs: []inputInfo{
23046                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23047                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23048                         },
23049                         outputs: []outputInfo{
23050                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23051                         },
23052                 },
23053         },
23054         {
23055                 name:            "LoweredAtomicAnd8Variant",
23056                 argLen:          3,
23057                 resultNotInArgs: true,
23058                 faultOnNilArg0:  true,
23059                 hasSideEffects:  true,
23060                 unsafePoint:     true,
23061                 reg: regInfo{
23062                         inputs: []inputInfo{
23063                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23064                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23065                         },
23066                         outputs: []outputInfo{
23067                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23068                         },
23069                 },
23070         },
23071         {
23072                 name:            "LoweredAtomicAnd32Variant",
23073                 argLen:          3,
23074                 resultNotInArgs: true,
23075                 faultOnNilArg0:  true,
23076                 hasSideEffects:  true,
23077                 unsafePoint:     true,
23078                 reg: regInfo{
23079                         inputs: []inputInfo{
23080                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23081                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23082                         },
23083                         outputs: []outputInfo{
23084                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23085                         },
23086                 },
23087         },
23088         {
23089                 name:            "LoweredAtomicOr8Variant",
23090                 argLen:          3,
23091                 resultNotInArgs: true,
23092                 faultOnNilArg0:  true,
23093                 hasSideEffects:  true,
23094                 reg: regInfo{
23095                         inputs: []inputInfo{
23096                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23097                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23098                         },
23099                         outputs: []outputInfo{
23100                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23101                         },
23102                 },
23103         },
23104         {
23105                 name:            "LoweredAtomicOr32Variant",
23106                 argLen:          3,
23107                 resultNotInArgs: true,
23108                 faultOnNilArg0:  true,
23109                 hasSideEffects:  true,
23110                 reg: regInfo{
23111                         inputs: []inputInfo{
23112                                 {1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
23113                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23114                         },
23115                         outputs: []outputInfo{
23116                                 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
23117                         },
23118                 },
23119         },
23120         {
23121                 name:         "LoweredWB",
23122                 auxType:      auxInt64,
23123                 argLen:       1,
23124                 clobberFlags: true,
23125                 reg: regInfo{
23126                         clobbers: 9223372035244359680, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23127                         outputs: []outputInfo{
23128                                 {0, 33554432}, // R25
23129                         },
23130                 },
23131         },
23132         {
23133                 name:    "LoweredPanicBoundsA",
23134                 auxType: auxInt64,
23135                 argLen:  3,
23136                 call:    true,
23137                 reg: regInfo{
23138                         inputs: []inputInfo{
23139                                 {0, 4}, // R2
23140                                 {1, 8}, // R3
23141                         },
23142                 },
23143         },
23144         {
23145                 name:    "LoweredPanicBoundsB",
23146                 auxType: auxInt64,
23147                 argLen:  3,
23148                 call:    true,
23149                 reg: regInfo{
23150                         inputs: []inputInfo{
23151                                 {0, 2}, // R1
23152                                 {1, 4}, // R2
23153                         },
23154                 },
23155         },
23156         {
23157                 name:    "LoweredPanicBoundsC",
23158                 auxType: auxInt64,
23159                 argLen:  3,
23160                 call:    true,
23161                 reg: regInfo{
23162                         inputs: []inputInfo{
23163                                 {0, 1}, // R0
23164                                 {1, 2}, // R1
23165                         },
23166                 },
23167         },
23168         {
23169                 name:           "PRFM",
23170                 auxType:        auxInt64,
23171                 argLen:         2,
23172                 hasSideEffects: true,
23173                 asm:            arm64.APRFM,
23174                 reg: regInfo{
23175                         inputs: []inputInfo{
23176                                 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
23177                         },
23178                 },
23179         },
23180         {
23181                 name:           "DMB",
23182                 auxType:        auxInt64,
23183                 argLen:         1,
23184                 hasSideEffects: true,
23185                 asm:            arm64.ADMB,
23186                 reg:            regInfo{},
23187         },
23188
23189         {
23190                 name:        "ADDV",
23191                 argLen:      2,
23192                 commutative: true,
23193                 asm:         loong64.AADDVU,
23194                 reg: regInfo{
23195                         inputs: []inputInfo{
23196                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23197                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23198                         },
23199                         outputs: []outputInfo{
23200                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23201                         },
23202                 },
23203         },
23204         {
23205                 name:    "ADDVconst",
23206                 auxType: auxInt64,
23207                 argLen:  1,
23208                 asm:     loong64.AADDVU,
23209                 reg: regInfo{
23210                         inputs: []inputInfo{
23211                                 {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23212                         },
23213                         outputs: []outputInfo{
23214                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23215                         },
23216                 },
23217         },
23218         {
23219                 name:   "SUBV",
23220                 argLen: 2,
23221                 asm:    loong64.ASUBVU,
23222                 reg: regInfo{
23223                         inputs: []inputInfo{
23224                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23225                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23226                         },
23227                         outputs: []outputInfo{
23228                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23229                         },
23230                 },
23231         },
23232         {
23233                 name:    "SUBVconst",
23234                 auxType: auxInt64,
23235                 argLen:  1,
23236                 asm:     loong64.ASUBVU,
23237                 reg: regInfo{
23238                         inputs: []inputInfo{
23239                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23240                         },
23241                         outputs: []outputInfo{
23242                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23243                         },
23244                 },
23245         },
23246         {
23247                 name:        "MULV",
23248                 argLen:      2,
23249                 commutative: true,
23250                 asm:         loong64.AMULV,
23251                 reg: regInfo{
23252                         inputs: []inputInfo{
23253                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23254                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23255                         },
23256                         outputs: []outputInfo{
23257                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23258                         },
23259                 },
23260         },
23261         {
23262                 name:        "MULHV",
23263                 argLen:      2,
23264                 commutative: true,
23265                 asm:         loong64.AMULHV,
23266                 reg: regInfo{
23267                         inputs: []inputInfo{
23268                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23269                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23270                         },
23271                         outputs: []outputInfo{
23272                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23273                         },
23274                 },
23275         },
23276         {
23277                 name:        "MULHVU",
23278                 argLen:      2,
23279                 commutative: true,
23280                 asm:         loong64.AMULHVU,
23281                 reg: regInfo{
23282                         inputs: []inputInfo{
23283                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23284                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23285                         },
23286                         outputs: []outputInfo{
23287                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23288                         },
23289                 },
23290         },
23291         {
23292                 name:   "DIVV",
23293                 argLen: 2,
23294                 asm:    loong64.ADIVV,
23295                 reg: regInfo{
23296                         inputs: []inputInfo{
23297                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23298                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23299                         },
23300                         outputs: []outputInfo{
23301                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23302                         },
23303                 },
23304         },
23305         {
23306                 name:   "DIVVU",
23307                 argLen: 2,
23308                 asm:    loong64.ADIVVU,
23309                 reg: regInfo{
23310                         inputs: []inputInfo{
23311                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23312                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23313                         },
23314                         outputs: []outputInfo{
23315                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23316                         },
23317                 },
23318         },
23319         {
23320                 name:   "REMV",
23321                 argLen: 2,
23322                 asm:    loong64.AREMV,
23323                 reg: regInfo{
23324                         inputs: []inputInfo{
23325                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23326                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23327                         },
23328                         outputs: []outputInfo{
23329                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23330                         },
23331                 },
23332         },
23333         {
23334                 name:   "REMVU",
23335                 argLen: 2,
23336                 asm:    loong64.AREMVU,
23337                 reg: regInfo{
23338                         inputs: []inputInfo{
23339                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23340                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23341                         },
23342                         outputs: []outputInfo{
23343                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23344                         },
23345                 },
23346         },
23347         {
23348                 name:        "ADDF",
23349                 argLen:      2,
23350                 commutative: true,
23351                 asm:         loong64.AADDF,
23352                 reg: regInfo{
23353                         inputs: []inputInfo{
23354                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23355                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23356                         },
23357                         outputs: []outputInfo{
23358                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23359                         },
23360                 },
23361         },
23362         {
23363                 name:        "ADDD",
23364                 argLen:      2,
23365                 commutative: true,
23366                 asm:         loong64.AADDD,
23367                 reg: regInfo{
23368                         inputs: []inputInfo{
23369                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23370                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23371                         },
23372                         outputs: []outputInfo{
23373                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23374                         },
23375                 },
23376         },
23377         {
23378                 name:   "SUBF",
23379                 argLen: 2,
23380                 asm:    loong64.ASUBF,
23381                 reg: regInfo{
23382                         inputs: []inputInfo{
23383                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23384                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23385                         },
23386                         outputs: []outputInfo{
23387                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23388                         },
23389                 },
23390         },
23391         {
23392                 name:   "SUBD",
23393                 argLen: 2,
23394                 asm:    loong64.ASUBD,
23395                 reg: regInfo{
23396                         inputs: []inputInfo{
23397                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23398                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23399                         },
23400                         outputs: []outputInfo{
23401                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23402                         },
23403                 },
23404         },
23405         {
23406                 name:        "MULF",
23407                 argLen:      2,
23408                 commutative: true,
23409                 asm:         loong64.AMULF,
23410                 reg: regInfo{
23411                         inputs: []inputInfo{
23412                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23413                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23414                         },
23415                         outputs: []outputInfo{
23416                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23417                         },
23418                 },
23419         },
23420         {
23421                 name:        "MULD",
23422                 argLen:      2,
23423                 commutative: true,
23424                 asm:         loong64.AMULD,
23425                 reg: regInfo{
23426                         inputs: []inputInfo{
23427                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23428                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23429                         },
23430                         outputs: []outputInfo{
23431                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23432                         },
23433                 },
23434         },
23435         {
23436                 name:   "DIVF",
23437                 argLen: 2,
23438                 asm:    loong64.ADIVF,
23439                 reg: regInfo{
23440                         inputs: []inputInfo{
23441                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23442                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23443                         },
23444                         outputs: []outputInfo{
23445                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23446                         },
23447                 },
23448         },
23449         {
23450                 name:   "DIVD",
23451                 argLen: 2,
23452                 asm:    loong64.ADIVD,
23453                 reg: regInfo{
23454                         inputs: []inputInfo{
23455                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23456                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23457                         },
23458                         outputs: []outputInfo{
23459                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23460                         },
23461                 },
23462         },
23463         {
23464                 name:        "AND",
23465                 argLen:      2,
23466                 commutative: true,
23467                 asm:         loong64.AAND,
23468                 reg: regInfo{
23469                         inputs: []inputInfo{
23470                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23471                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23472                         },
23473                         outputs: []outputInfo{
23474                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23475                         },
23476                 },
23477         },
23478         {
23479                 name:    "ANDconst",
23480                 auxType: auxInt64,
23481                 argLen:  1,
23482                 asm:     loong64.AAND,
23483                 reg: regInfo{
23484                         inputs: []inputInfo{
23485                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23486                         },
23487                         outputs: []outputInfo{
23488                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23489                         },
23490                 },
23491         },
23492         {
23493                 name:        "OR",
23494                 argLen:      2,
23495                 commutative: true,
23496                 asm:         loong64.AOR,
23497                 reg: regInfo{
23498                         inputs: []inputInfo{
23499                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23500                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23501                         },
23502                         outputs: []outputInfo{
23503                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23504                         },
23505                 },
23506         },
23507         {
23508                 name:    "ORconst",
23509                 auxType: auxInt64,
23510                 argLen:  1,
23511                 asm:     loong64.AOR,
23512                 reg: regInfo{
23513                         inputs: []inputInfo{
23514                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23515                         },
23516                         outputs: []outputInfo{
23517                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23518                         },
23519                 },
23520         },
23521         {
23522                 name:        "XOR",
23523                 argLen:      2,
23524                 commutative: true,
23525                 asm:         loong64.AXOR,
23526                 reg: regInfo{
23527                         inputs: []inputInfo{
23528                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23529                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23530                         },
23531                         outputs: []outputInfo{
23532                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23533                         },
23534                 },
23535         },
23536         {
23537                 name:    "XORconst",
23538                 auxType: auxInt64,
23539                 argLen:  1,
23540                 asm:     loong64.AXOR,
23541                 reg: regInfo{
23542                         inputs: []inputInfo{
23543                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23544                         },
23545                         outputs: []outputInfo{
23546                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23547                         },
23548                 },
23549         },
23550         {
23551                 name:        "NOR",
23552                 argLen:      2,
23553                 commutative: true,
23554                 asm:         loong64.ANOR,
23555                 reg: regInfo{
23556                         inputs: []inputInfo{
23557                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23558                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23559                         },
23560                         outputs: []outputInfo{
23561                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23562                         },
23563                 },
23564         },
23565         {
23566                 name:    "NORconst",
23567                 auxType: auxInt64,
23568                 argLen:  1,
23569                 asm:     loong64.ANOR,
23570                 reg: regInfo{
23571                         inputs: []inputInfo{
23572                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23573                         },
23574                         outputs: []outputInfo{
23575                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23576                         },
23577                 },
23578         },
23579         {
23580                 name:   "NEGV",
23581                 argLen: 1,
23582                 reg: regInfo{
23583                         inputs: []inputInfo{
23584                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23585                         },
23586                         outputs: []outputInfo{
23587                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23588                         },
23589                 },
23590         },
23591         {
23592                 name:   "NEGF",
23593                 argLen: 1,
23594                 asm:    loong64.ANEGF,
23595                 reg: regInfo{
23596                         inputs: []inputInfo{
23597                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23598                         },
23599                         outputs: []outputInfo{
23600                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23601                         },
23602                 },
23603         },
23604         {
23605                 name:   "NEGD",
23606                 argLen: 1,
23607                 asm:    loong64.ANEGD,
23608                 reg: regInfo{
23609                         inputs: []inputInfo{
23610                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23611                         },
23612                         outputs: []outputInfo{
23613                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23614                         },
23615                 },
23616         },
23617         {
23618                 name:   "SQRTD",
23619                 argLen: 1,
23620                 asm:    loong64.ASQRTD,
23621                 reg: regInfo{
23622                         inputs: []inputInfo{
23623                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23624                         },
23625                         outputs: []outputInfo{
23626                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23627                         },
23628                 },
23629         },
23630         {
23631                 name:   "SQRTF",
23632                 argLen: 1,
23633                 asm:    loong64.ASQRTF,
23634                 reg: regInfo{
23635                         inputs: []inputInfo{
23636                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23637                         },
23638                         outputs: []outputInfo{
23639                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23640                         },
23641                 },
23642         },
23643         {
23644                 name:   "MASKEQZ",
23645                 argLen: 2,
23646                 asm:    loong64.AMASKEQZ,
23647                 reg: regInfo{
23648                         inputs: []inputInfo{
23649                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23650                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23651                         },
23652                         outputs: []outputInfo{
23653                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23654                         },
23655                 },
23656         },
23657         {
23658                 name:   "MASKNEZ",
23659                 argLen: 2,
23660                 asm:    loong64.AMASKNEZ,
23661                 reg: regInfo{
23662                         inputs: []inputInfo{
23663                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23664                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23665                         },
23666                         outputs: []outputInfo{
23667                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23668                         },
23669                 },
23670         },
23671         {
23672                 name:   "SLLV",
23673                 argLen: 2,
23674                 asm:    loong64.ASLLV,
23675                 reg: regInfo{
23676                         inputs: []inputInfo{
23677                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23678                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23679                         },
23680                         outputs: []outputInfo{
23681                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23682                         },
23683                 },
23684         },
23685         {
23686                 name:    "SLLVconst",
23687                 auxType: auxInt64,
23688                 argLen:  1,
23689                 asm:     loong64.ASLLV,
23690                 reg: regInfo{
23691                         inputs: []inputInfo{
23692                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23693                         },
23694                         outputs: []outputInfo{
23695                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23696                         },
23697                 },
23698         },
23699         {
23700                 name:   "SRLV",
23701                 argLen: 2,
23702                 asm:    loong64.ASRLV,
23703                 reg: regInfo{
23704                         inputs: []inputInfo{
23705                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23706                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23707                         },
23708                         outputs: []outputInfo{
23709                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23710                         },
23711                 },
23712         },
23713         {
23714                 name:    "SRLVconst",
23715                 auxType: auxInt64,
23716                 argLen:  1,
23717                 asm:     loong64.ASRLV,
23718                 reg: regInfo{
23719                         inputs: []inputInfo{
23720                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23721                         },
23722                         outputs: []outputInfo{
23723                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23724                         },
23725                 },
23726         },
23727         {
23728                 name:   "SRAV",
23729                 argLen: 2,
23730                 asm:    loong64.ASRAV,
23731                 reg: regInfo{
23732                         inputs: []inputInfo{
23733                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23734                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23735                         },
23736                         outputs: []outputInfo{
23737                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23738                         },
23739                 },
23740         },
23741         {
23742                 name:    "SRAVconst",
23743                 auxType: auxInt64,
23744                 argLen:  1,
23745                 asm:     loong64.ASRAV,
23746                 reg: regInfo{
23747                         inputs: []inputInfo{
23748                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23749                         },
23750                         outputs: []outputInfo{
23751                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23752                         },
23753                 },
23754         },
23755         {
23756                 name:   "ROTR",
23757                 argLen: 2,
23758                 asm:    loong64.AROTR,
23759                 reg: regInfo{
23760                         inputs: []inputInfo{
23761                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23762                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23763                         },
23764                         outputs: []outputInfo{
23765                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23766                         },
23767                 },
23768         },
23769         {
23770                 name:   "ROTRV",
23771                 argLen: 2,
23772                 asm:    loong64.AROTRV,
23773                 reg: regInfo{
23774                         inputs: []inputInfo{
23775                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23776                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23777                         },
23778                         outputs: []outputInfo{
23779                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23780                         },
23781                 },
23782         },
23783         {
23784                 name:    "ROTRconst",
23785                 auxType: auxInt64,
23786                 argLen:  1,
23787                 asm:     loong64.AROTR,
23788                 reg: regInfo{
23789                         inputs: []inputInfo{
23790                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23791                         },
23792                         outputs: []outputInfo{
23793                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23794                         },
23795                 },
23796         },
23797         {
23798                 name:    "ROTRVconst",
23799                 auxType: auxInt64,
23800                 argLen:  1,
23801                 asm:     loong64.AROTRV,
23802                 reg: regInfo{
23803                         inputs: []inputInfo{
23804                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23805                         },
23806                         outputs: []outputInfo{
23807                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23808                         },
23809                 },
23810         },
23811         {
23812                 name:   "SGT",
23813                 argLen: 2,
23814                 asm:    loong64.ASGT,
23815                 reg: regInfo{
23816                         inputs: []inputInfo{
23817                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23818                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23819                         },
23820                         outputs: []outputInfo{
23821                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23822                         },
23823                 },
23824         },
23825         {
23826                 name:    "SGTconst",
23827                 auxType: auxInt64,
23828                 argLen:  1,
23829                 asm:     loong64.ASGT,
23830                 reg: regInfo{
23831                         inputs: []inputInfo{
23832                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23833                         },
23834                         outputs: []outputInfo{
23835                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23836                         },
23837                 },
23838         },
23839         {
23840                 name:   "SGTU",
23841                 argLen: 2,
23842                 asm:    loong64.ASGTU,
23843                 reg: regInfo{
23844                         inputs: []inputInfo{
23845                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23846                                 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23847                         },
23848                         outputs: []outputInfo{
23849                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23850                         },
23851                 },
23852         },
23853         {
23854                 name:    "SGTUconst",
23855                 auxType: auxInt64,
23856                 argLen:  1,
23857                 asm:     loong64.ASGTU,
23858                 reg: regInfo{
23859                         inputs: []inputInfo{
23860                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
23861                         },
23862                         outputs: []outputInfo{
23863                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23864                         },
23865                 },
23866         },
23867         {
23868                 name:   "CMPEQF",
23869                 argLen: 2,
23870                 asm:    loong64.ACMPEQF,
23871                 reg: regInfo{
23872                         inputs: []inputInfo{
23873                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23874                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23875                         },
23876                 },
23877         },
23878         {
23879                 name:   "CMPEQD",
23880                 argLen: 2,
23881                 asm:    loong64.ACMPEQD,
23882                 reg: regInfo{
23883                         inputs: []inputInfo{
23884                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23885                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23886                         },
23887                 },
23888         },
23889         {
23890                 name:   "CMPGEF",
23891                 argLen: 2,
23892                 asm:    loong64.ACMPGEF,
23893                 reg: regInfo{
23894                         inputs: []inputInfo{
23895                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23896                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23897                         },
23898                 },
23899         },
23900         {
23901                 name:   "CMPGED",
23902                 argLen: 2,
23903                 asm:    loong64.ACMPGED,
23904                 reg: regInfo{
23905                         inputs: []inputInfo{
23906                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23907                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23908                         },
23909                 },
23910         },
23911         {
23912                 name:   "CMPGTF",
23913                 argLen: 2,
23914                 asm:    loong64.ACMPGTF,
23915                 reg: regInfo{
23916                         inputs: []inputInfo{
23917                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23918                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23919                         },
23920                 },
23921         },
23922         {
23923                 name:   "CMPGTD",
23924                 argLen: 2,
23925                 asm:    loong64.ACMPGTD,
23926                 reg: regInfo{
23927                         inputs: []inputInfo{
23928                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23929                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23930                         },
23931                 },
23932         },
23933         {
23934                 name:              "MOVVconst",
23935                 auxType:           auxInt64,
23936                 argLen:            0,
23937                 rematerializeable: true,
23938                 asm:               loong64.AMOVV,
23939                 reg: regInfo{
23940                         outputs: []outputInfo{
23941                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23942                         },
23943                 },
23944         },
23945         {
23946                 name:              "MOVFconst",
23947                 auxType:           auxFloat64,
23948                 argLen:            0,
23949                 rematerializeable: true,
23950                 asm:               loong64.AMOVF,
23951                 reg: regInfo{
23952                         outputs: []outputInfo{
23953                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23954                         },
23955                 },
23956         },
23957         {
23958                 name:              "MOVDconst",
23959                 auxType:           auxFloat64,
23960                 argLen:            0,
23961                 rematerializeable: true,
23962                 asm:               loong64.AMOVD,
23963                 reg: regInfo{
23964                         outputs: []outputInfo{
23965                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23966                         },
23967                 },
23968         },
23969         {
23970                 name:              "MOVVaddr",
23971                 auxType:           auxSymOff,
23972                 argLen:            1,
23973                 rematerializeable: true,
23974                 symEffect:         SymAddr,
23975                 asm:               loong64.AMOVV,
23976                 reg: regInfo{
23977                         inputs: []inputInfo{
23978                                 {0, 4611686018427387908}, // SP SB
23979                         },
23980                         outputs: []outputInfo{
23981                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23982                         },
23983                 },
23984         },
23985         {
23986                 name:           "MOVBload",
23987                 auxType:        auxSymOff,
23988                 argLen:         2,
23989                 faultOnNilArg0: true,
23990                 symEffect:      SymRead,
23991                 asm:            loong64.AMOVB,
23992                 reg: regInfo{
23993                         inputs: []inputInfo{
23994                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
23995                         },
23996                         outputs: []outputInfo{
23997                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
23998                         },
23999                 },
24000         },
24001         {
24002                 name:           "MOVBUload",
24003                 auxType:        auxSymOff,
24004                 argLen:         2,
24005                 faultOnNilArg0: true,
24006                 symEffect:      SymRead,
24007                 asm:            loong64.AMOVBU,
24008                 reg: regInfo{
24009                         inputs: []inputInfo{
24010                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24011                         },
24012                         outputs: []outputInfo{
24013                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24014                         },
24015                 },
24016         },
24017         {
24018                 name:           "MOVHload",
24019                 auxType:        auxSymOff,
24020                 argLen:         2,
24021                 faultOnNilArg0: true,
24022                 symEffect:      SymRead,
24023                 asm:            loong64.AMOVH,
24024                 reg: regInfo{
24025                         inputs: []inputInfo{
24026                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24027                         },
24028                         outputs: []outputInfo{
24029                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24030                         },
24031                 },
24032         },
24033         {
24034                 name:           "MOVHUload",
24035                 auxType:        auxSymOff,
24036                 argLen:         2,
24037                 faultOnNilArg0: true,
24038                 symEffect:      SymRead,
24039                 asm:            loong64.AMOVHU,
24040                 reg: regInfo{
24041                         inputs: []inputInfo{
24042                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24043                         },
24044                         outputs: []outputInfo{
24045                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24046                         },
24047                 },
24048         },
24049         {
24050                 name:           "MOVWload",
24051                 auxType:        auxSymOff,
24052                 argLen:         2,
24053                 faultOnNilArg0: true,
24054                 symEffect:      SymRead,
24055                 asm:            loong64.AMOVW,
24056                 reg: regInfo{
24057                         inputs: []inputInfo{
24058                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24059                         },
24060                         outputs: []outputInfo{
24061                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24062                         },
24063                 },
24064         },
24065         {
24066                 name:           "MOVWUload",
24067                 auxType:        auxSymOff,
24068                 argLen:         2,
24069                 faultOnNilArg0: true,
24070                 symEffect:      SymRead,
24071                 asm:            loong64.AMOVWU,
24072                 reg: regInfo{
24073                         inputs: []inputInfo{
24074                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24075                         },
24076                         outputs: []outputInfo{
24077                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24078                         },
24079                 },
24080         },
24081         {
24082                 name:           "MOVVload",
24083                 auxType:        auxSymOff,
24084                 argLen:         2,
24085                 faultOnNilArg0: true,
24086                 symEffect:      SymRead,
24087                 asm:            loong64.AMOVV,
24088                 reg: regInfo{
24089                         inputs: []inputInfo{
24090                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24091                         },
24092                         outputs: []outputInfo{
24093                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24094                         },
24095                 },
24096         },
24097         {
24098                 name:           "MOVFload",
24099                 auxType:        auxSymOff,
24100                 argLen:         2,
24101                 faultOnNilArg0: true,
24102                 symEffect:      SymRead,
24103                 asm:            loong64.AMOVF,
24104                 reg: regInfo{
24105                         inputs: []inputInfo{
24106                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24107                         },
24108                         outputs: []outputInfo{
24109                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24110                         },
24111                 },
24112         },
24113         {
24114                 name:           "MOVDload",
24115                 auxType:        auxSymOff,
24116                 argLen:         2,
24117                 faultOnNilArg0: true,
24118                 symEffect:      SymRead,
24119                 asm:            loong64.AMOVD,
24120                 reg: regInfo{
24121                         inputs: []inputInfo{
24122                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24123                         },
24124                         outputs: []outputInfo{
24125                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24126                         },
24127                 },
24128         },
24129         {
24130                 name:           "MOVBstore",
24131                 auxType:        auxSymOff,
24132                 argLen:         3,
24133                 faultOnNilArg0: true,
24134                 symEffect:      SymWrite,
24135                 asm:            loong64.AMOVB,
24136                 reg: regInfo{
24137                         inputs: []inputInfo{
24138                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24139                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24140                         },
24141                 },
24142         },
24143         {
24144                 name:           "MOVHstore",
24145                 auxType:        auxSymOff,
24146                 argLen:         3,
24147                 faultOnNilArg0: true,
24148                 symEffect:      SymWrite,
24149                 asm:            loong64.AMOVH,
24150                 reg: regInfo{
24151                         inputs: []inputInfo{
24152                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24153                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24154                         },
24155                 },
24156         },
24157         {
24158                 name:           "MOVWstore",
24159                 auxType:        auxSymOff,
24160                 argLen:         3,
24161                 faultOnNilArg0: true,
24162                 symEffect:      SymWrite,
24163                 asm:            loong64.AMOVW,
24164                 reg: regInfo{
24165                         inputs: []inputInfo{
24166                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24167                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24168                         },
24169                 },
24170         },
24171         {
24172                 name:           "MOVVstore",
24173                 auxType:        auxSymOff,
24174                 argLen:         3,
24175                 faultOnNilArg0: true,
24176                 symEffect:      SymWrite,
24177                 asm:            loong64.AMOVV,
24178                 reg: regInfo{
24179                         inputs: []inputInfo{
24180                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24181                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24182                         },
24183                 },
24184         },
24185         {
24186                 name:           "MOVFstore",
24187                 auxType:        auxSymOff,
24188                 argLen:         3,
24189                 faultOnNilArg0: true,
24190                 symEffect:      SymWrite,
24191                 asm:            loong64.AMOVF,
24192                 reg: regInfo{
24193                         inputs: []inputInfo{
24194                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24195                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24196                         },
24197                 },
24198         },
24199         {
24200                 name:           "MOVDstore",
24201                 auxType:        auxSymOff,
24202                 argLen:         3,
24203                 faultOnNilArg0: true,
24204                 symEffect:      SymWrite,
24205                 asm:            loong64.AMOVD,
24206                 reg: regInfo{
24207                         inputs: []inputInfo{
24208                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24209                                 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24210                         },
24211                 },
24212         },
24213         {
24214                 name:           "MOVBstorezero",
24215                 auxType:        auxSymOff,
24216                 argLen:         2,
24217                 faultOnNilArg0: true,
24218                 symEffect:      SymWrite,
24219                 asm:            loong64.AMOVB,
24220                 reg: regInfo{
24221                         inputs: []inputInfo{
24222                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24223                         },
24224                 },
24225         },
24226         {
24227                 name:           "MOVHstorezero",
24228                 auxType:        auxSymOff,
24229                 argLen:         2,
24230                 faultOnNilArg0: true,
24231                 symEffect:      SymWrite,
24232                 asm:            loong64.AMOVH,
24233                 reg: regInfo{
24234                         inputs: []inputInfo{
24235                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24236                         },
24237                 },
24238         },
24239         {
24240                 name:           "MOVWstorezero",
24241                 auxType:        auxSymOff,
24242                 argLen:         2,
24243                 faultOnNilArg0: true,
24244                 symEffect:      SymWrite,
24245                 asm:            loong64.AMOVW,
24246                 reg: regInfo{
24247                         inputs: []inputInfo{
24248                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24249                         },
24250                 },
24251         },
24252         {
24253                 name:           "MOVVstorezero",
24254                 auxType:        auxSymOff,
24255                 argLen:         2,
24256                 faultOnNilArg0: true,
24257                 symEffect:      SymWrite,
24258                 asm:            loong64.AMOVV,
24259                 reg: regInfo{
24260                         inputs: []inputInfo{
24261                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24262                         },
24263                 },
24264         },
24265         {
24266                 name:   "MOVBreg",
24267                 argLen: 1,
24268                 asm:    loong64.AMOVB,
24269                 reg: regInfo{
24270                         inputs: []inputInfo{
24271                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24272                         },
24273                         outputs: []outputInfo{
24274                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24275                         },
24276                 },
24277         },
24278         {
24279                 name:   "MOVBUreg",
24280                 argLen: 1,
24281                 asm:    loong64.AMOVBU,
24282                 reg: regInfo{
24283                         inputs: []inputInfo{
24284                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24285                         },
24286                         outputs: []outputInfo{
24287                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24288                         },
24289                 },
24290         },
24291         {
24292                 name:   "MOVHreg",
24293                 argLen: 1,
24294                 asm:    loong64.AMOVH,
24295                 reg: regInfo{
24296                         inputs: []inputInfo{
24297                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24298                         },
24299                         outputs: []outputInfo{
24300                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24301                         },
24302                 },
24303         },
24304         {
24305                 name:   "MOVHUreg",
24306                 argLen: 1,
24307                 asm:    loong64.AMOVHU,
24308                 reg: regInfo{
24309                         inputs: []inputInfo{
24310                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24311                         },
24312                         outputs: []outputInfo{
24313                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24314                         },
24315                 },
24316         },
24317         {
24318                 name:   "MOVWreg",
24319                 argLen: 1,
24320                 asm:    loong64.AMOVW,
24321                 reg: regInfo{
24322                         inputs: []inputInfo{
24323                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24324                         },
24325                         outputs: []outputInfo{
24326                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24327                         },
24328                 },
24329         },
24330         {
24331                 name:   "MOVWUreg",
24332                 argLen: 1,
24333                 asm:    loong64.AMOVWU,
24334                 reg: regInfo{
24335                         inputs: []inputInfo{
24336                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24337                         },
24338                         outputs: []outputInfo{
24339                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24340                         },
24341                 },
24342         },
24343         {
24344                 name:   "MOVVreg",
24345                 argLen: 1,
24346                 asm:    loong64.AMOVV,
24347                 reg: regInfo{
24348                         inputs: []inputInfo{
24349                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24350                         },
24351                         outputs: []outputInfo{
24352                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24353                         },
24354                 },
24355         },
24356         {
24357                 name:         "MOVVnop",
24358                 argLen:       1,
24359                 resultInArg0: true,
24360                 reg: regInfo{
24361                         inputs: []inputInfo{
24362                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24363                         },
24364                         outputs: []outputInfo{
24365                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24366                         },
24367                 },
24368         },
24369         {
24370                 name:   "MOVWF",
24371                 argLen: 1,
24372                 asm:    loong64.AMOVWF,
24373                 reg: regInfo{
24374                         inputs: []inputInfo{
24375                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24376                         },
24377                         outputs: []outputInfo{
24378                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24379                         },
24380                 },
24381         },
24382         {
24383                 name:   "MOVWD",
24384                 argLen: 1,
24385                 asm:    loong64.AMOVWD,
24386                 reg: regInfo{
24387                         inputs: []inputInfo{
24388                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24389                         },
24390                         outputs: []outputInfo{
24391                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24392                         },
24393                 },
24394         },
24395         {
24396                 name:   "MOVVF",
24397                 argLen: 1,
24398                 asm:    loong64.AMOVVF,
24399                 reg: regInfo{
24400                         inputs: []inputInfo{
24401                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24402                         },
24403                         outputs: []outputInfo{
24404                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24405                         },
24406                 },
24407         },
24408         {
24409                 name:   "MOVVD",
24410                 argLen: 1,
24411                 asm:    loong64.AMOVVD,
24412                 reg: regInfo{
24413                         inputs: []inputInfo{
24414                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24415                         },
24416                         outputs: []outputInfo{
24417                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24418                         },
24419                 },
24420         },
24421         {
24422                 name:   "TRUNCFW",
24423                 argLen: 1,
24424                 asm:    loong64.ATRUNCFW,
24425                 reg: regInfo{
24426                         inputs: []inputInfo{
24427                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24428                         },
24429                         outputs: []outputInfo{
24430                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24431                         },
24432                 },
24433         },
24434         {
24435                 name:   "TRUNCDW",
24436                 argLen: 1,
24437                 asm:    loong64.ATRUNCDW,
24438                 reg: regInfo{
24439                         inputs: []inputInfo{
24440                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24441                         },
24442                         outputs: []outputInfo{
24443                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24444                         },
24445                 },
24446         },
24447         {
24448                 name:   "TRUNCFV",
24449                 argLen: 1,
24450                 asm:    loong64.ATRUNCFV,
24451                 reg: regInfo{
24452                         inputs: []inputInfo{
24453                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24454                         },
24455                         outputs: []outputInfo{
24456                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24457                         },
24458                 },
24459         },
24460         {
24461                 name:   "TRUNCDV",
24462                 argLen: 1,
24463                 asm:    loong64.ATRUNCDV,
24464                 reg: regInfo{
24465                         inputs: []inputInfo{
24466                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24467                         },
24468                         outputs: []outputInfo{
24469                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24470                         },
24471                 },
24472         },
24473         {
24474                 name:   "MOVFD",
24475                 argLen: 1,
24476                 asm:    loong64.AMOVFD,
24477                 reg: regInfo{
24478                         inputs: []inputInfo{
24479                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24480                         },
24481                         outputs: []outputInfo{
24482                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24483                         },
24484                 },
24485         },
24486         {
24487                 name:   "MOVDF",
24488                 argLen: 1,
24489                 asm:    loong64.AMOVDF,
24490                 reg: regInfo{
24491                         inputs: []inputInfo{
24492                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24493                         },
24494                         outputs: []outputInfo{
24495                                 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24496                         },
24497                 },
24498         },
24499         {
24500                 name:         "CALLstatic",
24501                 auxType:      auxCallOff,
24502                 argLen:       1,
24503                 clobberFlags: true,
24504                 call:         true,
24505                 reg: regInfo{
24506                         clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24507                 },
24508         },
24509         {
24510                 name:         "CALLtail",
24511                 auxType:      auxCallOff,
24512                 argLen:       1,
24513                 clobberFlags: true,
24514                 call:         true,
24515                 tailCall:     true,
24516                 reg: regInfo{
24517                         clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24518                 },
24519         },
24520         {
24521                 name:         "CALLclosure",
24522                 auxType:      auxCallOff,
24523                 argLen:       3,
24524                 clobberFlags: true,
24525                 call:         true,
24526                 reg: regInfo{
24527                         inputs: []inputInfo{
24528                                 {1, 268435456},  // R29
24529                                 {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24530                         },
24531                         clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24532                 },
24533         },
24534         {
24535                 name:         "CALLinter",
24536                 auxType:      auxCallOff,
24537                 argLen:       2,
24538                 clobberFlags: true,
24539                 call:         true,
24540                 reg: regInfo{
24541                         inputs: []inputInfo{
24542                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24543                         },
24544                         clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24545                 },
24546         },
24547         {
24548                 name:           "DUFFZERO",
24549                 auxType:        auxInt64,
24550                 argLen:         2,
24551                 faultOnNilArg0: true,
24552                 reg: regInfo{
24553                         inputs: []inputInfo{
24554                                 {0, 262144}, // R19
24555                         },
24556                         clobbers: 262146, // R1 R19
24557                 },
24558         },
24559         {
24560                 name:           "DUFFCOPY",
24561                 auxType:        auxInt64,
24562                 argLen:         3,
24563                 faultOnNilArg0: true,
24564                 faultOnNilArg1: true,
24565                 reg: regInfo{
24566                         inputs: []inputInfo{
24567                                 {0, 524288}, // R20
24568                                 {1, 262144}, // R19
24569                         },
24570                         clobbers: 786434, // R1 R19 R20
24571                 },
24572         },
24573         {
24574                 name:           "LoweredZero",
24575                 auxType:        auxInt64,
24576                 argLen:         3,
24577                 faultOnNilArg0: true,
24578                 reg: regInfo{
24579                         inputs: []inputInfo{
24580                                 {0, 262144},     // R19
24581                                 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24582                         },
24583                         clobbers: 262144, // R19
24584                 },
24585         },
24586         {
24587                 name:           "LoweredMove",
24588                 auxType:        auxInt64,
24589                 argLen:         4,
24590                 faultOnNilArg0: true,
24591                 faultOnNilArg1: true,
24592                 reg: regInfo{
24593                         inputs: []inputInfo{
24594                                 {0, 524288},     // R20
24595                                 {1, 262144},     // R19
24596                                 {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24597                         },
24598                         clobbers: 786432, // R19 R20
24599                 },
24600         },
24601         {
24602                 name:           "LoweredAtomicLoad8",
24603                 argLen:         2,
24604                 faultOnNilArg0: true,
24605                 reg: regInfo{
24606                         inputs: []inputInfo{
24607                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24608                         },
24609                         outputs: []outputInfo{
24610                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24611                         },
24612                 },
24613         },
24614         {
24615                 name:           "LoweredAtomicLoad32",
24616                 argLen:         2,
24617                 faultOnNilArg0: true,
24618                 reg: regInfo{
24619                         inputs: []inputInfo{
24620                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24621                         },
24622                         outputs: []outputInfo{
24623                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24624                         },
24625                 },
24626         },
24627         {
24628                 name:           "LoweredAtomicLoad64",
24629                 argLen:         2,
24630                 faultOnNilArg0: true,
24631                 reg: regInfo{
24632                         inputs: []inputInfo{
24633                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24634                         },
24635                         outputs: []outputInfo{
24636                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24637                         },
24638                 },
24639         },
24640         {
24641                 name:           "LoweredAtomicStore8",
24642                 argLen:         3,
24643                 faultOnNilArg0: true,
24644                 hasSideEffects: true,
24645                 reg: regInfo{
24646                         inputs: []inputInfo{
24647                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24648                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24649                         },
24650                 },
24651         },
24652         {
24653                 name:           "LoweredAtomicStore32",
24654                 argLen:         3,
24655                 faultOnNilArg0: true,
24656                 hasSideEffects: true,
24657                 reg: regInfo{
24658                         inputs: []inputInfo{
24659                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24660                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24661                         },
24662                 },
24663         },
24664         {
24665                 name:           "LoweredAtomicStore64",
24666                 argLen:         3,
24667                 faultOnNilArg0: true,
24668                 hasSideEffects: true,
24669                 reg: regInfo{
24670                         inputs: []inputInfo{
24671                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24672                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24673                         },
24674                 },
24675         },
24676         {
24677                 name:           "LoweredAtomicStorezero32",
24678                 argLen:         2,
24679                 faultOnNilArg0: true,
24680                 hasSideEffects: true,
24681                 reg: regInfo{
24682                         inputs: []inputInfo{
24683                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24684                         },
24685                 },
24686         },
24687         {
24688                 name:           "LoweredAtomicStorezero64",
24689                 argLen:         2,
24690                 faultOnNilArg0: true,
24691                 hasSideEffects: true,
24692                 reg: regInfo{
24693                         inputs: []inputInfo{
24694                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24695                         },
24696                 },
24697         },
24698         {
24699                 name:            "LoweredAtomicExchange32",
24700                 argLen:          3,
24701                 resultNotInArgs: true,
24702                 faultOnNilArg0:  true,
24703                 hasSideEffects:  true,
24704                 unsafePoint:     true,
24705                 reg: regInfo{
24706                         inputs: []inputInfo{
24707                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24708                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24709                         },
24710                         outputs: []outputInfo{
24711                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24712                         },
24713                 },
24714         },
24715         {
24716                 name:            "LoweredAtomicExchange64",
24717                 argLen:          3,
24718                 resultNotInArgs: true,
24719                 faultOnNilArg0:  true,
24720                 hasSideEffects:  true,
24721                 unsafePoint:     true,
24722                 reg: regInfo{
24723                         inputs: []inputInfo{
24724                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24725                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24726                         },
24727                         outputs: []outputInfo{
24728                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24729                         },
24730                 },
24731         },
24732         {
24733                 name:            "LoweredAtomicAdd32",
24734                 argLen:          3,
24735                 resultNotInArgs: true,
24736                 faultOnNilArg0:  true,
24737                 hasSideEffects:  true,
24738                 unsafePoint:     true,
24739                 reg: regInfo{
24740                         inputs: []inputInfo{
24741                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24742                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24743                         },
24744                         outputs: []outputInfo{
24745                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24746                         },
24747                 },
24748         },
24749         {
24750                 name:            "LoweredAtomicAdd64",
24751                 argLen:          3,
24752                 resultNotInArgs: true,
24753                 faultOnNilArg0:  true,
24754                 hasSideEffects:  true,
24755                 unsafePoint:     true,
24756                 reg: regInfo{
24757                         inputs: []inputInfo{
24758                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24759                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24760                         },
24761                         outputs: []outputInfo{
24762                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24763                         },
24764                 },
24765         },
24766         {
24767                 name:            "LoweredAtomicAddconst32",
24768                 auxType:         auxInt32,
24769                 argLen:          2,
24770                 resultNotInArgs: true,
24771                 faultOnNilArg0:  true,
24772                 hasSideEffects:  true,
24773                 unsafePoint:     true,
24774                 reg: regInfo{
24775                         inputs: []inputInfo{
24776                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24777                         },
24778                         outputs: []outputInfo{
24779                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24780                         },
24781                 },
24782         },
24783         {
24784                 name:            "LoweredAtomicAddconst64",
24785                 auxType:         auxInt64,
24786                 argLen:          2,
24787                 resultNotInArgs: true,
24788                 faultOnNilArg0:  true,
24789                 hasSideEffects:  true,
24790                 unsafePoint:     true,
24791                 reg: regInfo{
24792                         inputs: []inputInfo{
24793                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24794                         },
24795                         outputs: []outputInfo{
24796                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24797                         },
24798                 },
24799         },
24800         {
24801                 name:            "LoweredAtomicCas32",
24802                 argLen:          4,
24803                 resultNotInArgs: true,
24804                 faultOnNilArg0:  true,
24805                 hasSideEffects:  true,
24806                 unsafePoint:     true,
24807                 reg: regInfo{
24808                         inputs: []inputInfo{
24809                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24810                                 {2, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24811                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24812                         },
24813                         outputs: []outputInfo{
24814                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24815                         },
24816                 },
24817         },
24818         {
24819                 name:            "LoweredAtomicCas64",
24820                 argLen:          4,
24821                 resultNotInArgs: true,
24822                 faultOnNilArg0:  true,
24823                 hasSideEffects:  true,
24824                 unsafePoint:     true,
24825                 reg: regInfo{
24826                         inputs: []inputInfo{
24827                                 {1, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24828                                 {2, 1072693240},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24829                                 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB
24830                         },
24831                         outputs: []outputInfo{
24832                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24833                         },
24834                 },
24835         },
24836         {
24837                 name:           "LoweredNilCheck",
24838                 argLen:         2,
24839                 nilCheck:       true,
24840                 faultOnNilArg0: true,
24841                 reg: regInfo{
24842                         inputs: []inputInfo{
24843                                 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
24844                         },
24845                 },
24846         },
24847         {
24848                 name:   "FPFlagTrue",
24849                 argLen: 1,
24850                 reg: regInfo{
24851                         outputs: []outputInfo{
24852                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24853                         },
24854                 },
24855         },
24856         {
24857                 name:   "FPFlagFalse",
24858                 argLen: 1,
24859                 reg: regInfo{
24860                         outputs: []outputInfo{
24861                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24862                         },
24863                 },
24864         },
24865         {
24866                 name:      "LoweredGetClosurePtr",
24867                 argLen:    0,
24868                 zeroWidth: true,
24869                 reg: regInfo{
24870                         outputs: []outputInfo{
24871                                 {0, 268435456}, // R29
24872                         },
24873                 },
24874         },
24875         {
24876                 name:              "LoweredGetCallerSP",
24877                 argLen:            1,
24878                 rematerializeable: true,
24879                 reg: regInfo{
24880                         outputs: []outputInfo{
24881                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24882                         },
24883                 },
24884         },
24885         {
24886                 name:              "LoweredGetCallerPC",
24887                 argLen:            0,
24888                 rematerializeable: true,
24889                 reg: regInfo{
24890                         outputs: []outputInfo{
24891                                 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
24892                         },
24893                 },
24894         },
24895         {
24896                 name:         "LoweredWB",
24897                 auxType:      auxInt64,
24898                 argLen:       1,
24899                 clobberFlags: true,
24900                 reg: regInfo{
24901                         clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24902                         outputs: []outputInfo{
24903                                 {0, 268435456}, // R29
24904                         },
24905                 },
24906         },
24907         {
24908                 name:    "LoweredPanicBoundsA",
24909                 auxType: auxInt64,
24910                 argLen:  3,
24911                 call:    true,
24912                 reg: regInfo{
24913                         inputs: []inputInfo{
24914                                 {0, 65536}, // R17
24915                                 {1, 8},     // R4
24916                         },
24917                 },
24918         },
24919         {
24920                 name:    "LoweredPanicBoundsB",
24921                 auxType: auxInt64,
24922                 argLen:  3,
24923                 call:    true,
24924                 reg: regInfo{
24925                         inputs: []inputInfo{
24926                                 {0, 131072}, // R18
24927                                 {1, 65536},  // R17
24928                         },
24929                 },
24930         },
24931         {
24932                 name:    "LoweredPanicBoundsC",
24933                 auxType: auxInt64,
24934                 argLen:  3,
24935                 call:    true,
24936                 reg: regInfo{
24937                         inputs: []inputInfo{
24938                                 {0, 262144}, // R19
24939                                 {1, 131072}, // R18
24940                         },
24941                 },
24942         },
24943
24944         {
24945                 name:        "ADD",
24946                 argLen:      2,
24947                 commutative: true,
24948                 asm:         mips.AADDU,
24949                 reg: regInfo{
24950                         inputs: []inputInfo{
24951                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
24952                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
24953                         },
24954                         outputs: []outputInfo{
24955                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
24956                         },
24957                 },
24958         },
24959         {
24960                 name:    "ADDconst",
24961                 auxType: auxInt32,
24962                 argLen:  1,
24963                 asm:     mips.AADDU,
24964                 reg: regInfo{
24965                         inputs: []inputInfo{
24966                                 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
24967                         },
24968                         outputs: []outputInfo{
24969                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
24970                         },
24971                 },
24972         },
24973         {
24974                 name:   "SUB",
24975                 argLen: 2,
24976                 asm:    mips.ASUBU,
24977                 reg: regInfo{
24978                         inputs: []inputInfo{
24979                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
24980                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
24981                         },
24982                         outputs: []outputInfo{
24983                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
24984                         },
24985                 },
24986         },
24987         {
24988                 name:    "SUBconst",
24989                 auxType: auxInt32,
24990                 argLen:  1,
24991                 asm:     mips.ASUBU,
24992                 reg: regInfo{
24993                         inputs: []inputInfo{
24994                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
24995                         },
24996                         outputs: []outputInfo{
24997                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
24998                         },
24999                 },
25000         },
25001         {
25002                 name:        "MUL",
25003                 argLen:      2,
25004                 commutative: true,
25005                 asm:         mips.AMUL,
25006                 reg: regInfo{
25007                         inputs: []inputInfo{
25008                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25009                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25010                         },
25011                         clobbers: 105553116266496, // HI LO
25012                         outputs: []outputInfo{
25013                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25014                         },
25015                 },
25016         },
25017         {
25018                 name:        "MULT",
25019                 argLen:      2,
25020                 commutative: true,
25021                 asm:         mips.AMUL,
25022                 reg: regInfo{
25023                         inputs: []inputInfo{
25024                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25025                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25026                         },
25027                         outputs: []outputInfo{
25028                                 {0, 35184372088832}, // HI
25029                                 {1, 70368744177664}, // LO
25030                         },
25031                 },
25032         },
25033         {
25034                 name:        "MULTU",
25035                 argLen:      2,
25036                 commutative: true,
25037                 asm:         mips.AMULU,
25038                 reg: regInfo{
25039                         inputs: []inputInfo{
25040                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25041                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25042                         },
25043                         outputs: []outputInfo{
25044                                 {0, 35184372088832}, // HI
25045                                 {1, 70368744177664}, // LO
25046                         },
25047                 },
25048         },
25049         {
25050                 name:   "DIV",
25051                 argLen: 2,
25052                 asm:    mips.ADIV,
25053                 reg: regInfo{
25054                         inputs: []inputInfo{
25055                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25056                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25057                         },
25058                         outputs: []outputInfo{
25059                                 {0, 35184372088832}, // HI
25060                                 {1, 70368744177664}, // LO
25061                         },
25062                 },
25063         },
25064         {
25065                 name:   "DIVU",
25066                 argLen: 2,
25067                 asm:    mips.ADIVU,
25068                 reg: regInfo{
25069                         inputs: []inputInfo{
25070                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25071                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25072                         },
25073                         outputs: []outputInfo{
25074                                 {0, 35184372088832}, // HI
25075                                 {1, 70368744177664}, // LO
25076                         },
25077                 },
25078         },
25079         {
25080                 name:        "ADDF",
25081                 argLen:      2,
25082                 commutative: true,
25083                 asm:         mips.AADDF,
25084                 reg: regInfo{
25085                         inputs: []inputInfo{
25086                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25087                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25088                         },
25089                         outputs: []outputInfo{
25090                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25091                         },
25092                 },
25093         },
25094         {
25095                 name:        "ADDD",
25096                 argLen:      2,
25097                 commutative: true,
25098                 asm:         mips.AADDD,
25099                 reg: regInfo{
25100                         inputs: []inputInfo{
25101                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25102                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25103                         },
25104                         outputs: []outputInfo{
25105                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25106                         },
25107                 },
25108         },
25109         {
25110                 name:   "SUBF",
25111                 argLen: 2,
25112                 asm:    mips.ASUBF,
25113                 reg: regInfo{
25114                         inputs: []inputInfo{
25115                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25116                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25117                         },
25118                         outputs: []outputInfo{
25119                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25120                         },
25121                 },
25122         },
25123         {
25124                 name:   "SUBD",
25125                 argLen: 2,
25126                 asm:    mips.ASUBD,
25127                 reg: regInfo{
25128                         inputs: []inputInfo{
25129                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25130                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25131                         },
25132                         outputs: []outputInfo{
25133                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25134                         },
25135                 },
25136         },
25137         {
25138                 name:        "MULF",
25139                 argLen:      2,
25140                 commutative: true,
25141                 asm:         mips.AMULF,
25142                 reg: regInfo{
25143                         inputs: []inputInfo{
25144                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25145                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25146                         },
25147                         outputs: []outputInfo{
25148                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25149                         },
25150                 },
25151         },
25152         {
25153                 name:        "MULD",
25154                 argLen:      2,
25155                 commutative: true,
25156                 asm:         mips.AMULD,
25157                 reg: regInfo{
25158                         inputs: []inputInfo{
25159                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25160                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25161                         },
25162                         outputs: []outputInfo{
25163                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25164                         },
25165                 },
25166         },
25167         {
25168                 name:   "DIVF",
25169                 argLen: 2,
25170                 asm:    mips.ADIVF,
25171                 reg: regInfo{
25172                         inputs: []inputInfo{
25173                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25174                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25175                         },
25176                         outputs: []outputInfo{
25177                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25178                         },
25179                 },
25180         },
25181         {
25182                 name:   "DIVD",
25183                 argLen: 2,
25184                 asm:    mips.ADIVD,
25185                 reg: regInfo{
25186                         inputs: []inputInfo{
25187                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25188                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25189                         },
25190                         outputs: []outputInfo{
25191                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25192                         },
25193                 },
25194         },
25195         {
25196                 name:        "AND",
25197                 argLen:      2,
25198                 commutative: true,
25199                 asm:         mips.AAND,
25200                 reg: regInfo{
25201                         inputs: []inputInfo{
25202                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25203                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25204                         },
25205                         outputs: []outputInfo{
25206                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25207                         },
25208                 },
25209         },
25210         {
25211                 name:    "ANDconst",
25212                 auxType: auxInt32,
25213                 argLen:  1,
25214                 asm:     mips.AAND,
25215                 reg: regInfo{
25216                         inputs: []inputInfo{
25217                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25218                         },
25219                         outputs: []outputInfo{
25220                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25221                         },
25222                 },
25223         },
25224         {
25225                 name:        "OR",
25226                 argLen:      2,
25227                 commutative: true,
25228                 asm:         mips.AOR,
25229                 reg: regInfo{
25230                         inputs: []inputInfo{
25231                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25232                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25233                         },
25234                         outputs: []outputInfo{
25235                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25236                         },
25237                 },
25238         },
25239         {
25240                 name:    "ORconst",
25241                 auxType: auxInt32,
25242                 argLen:  1,
25243                 asm:     mips.AOR,
25244                 reg: regInfo{
25245                         inputs: []inputInfo{
25246                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25247                         },
25248                         outputs: []outputInfo{
25249                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25250                         },
25251                 },
25252         },
25253         {
25254                 name:        "XOR",
25255                 argLen:      2,
25256                 commutative: true,
25257                 asm:         mips.AXOR,
25258                 reg: regInfo{
25259                         inputs: []inputInfo{
25260                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25261                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25262                         },
25263                         outputs: []outputInfo{
25264                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25265                         },
25266                 },
25267         },
25268         {
25269                 name:    "XORconst",
25270                 auxType: auxInt32,
25271                 argLen:  1,
25272                 asm:     mips.AXOR,
25273                 reg: regInfo{
25274                         inputs: []inputInfo{
25275                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25276                         },
25277                         outputs: []outputInfo{
25278                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25279                         },
25280                 },
25281         },
25282         {
25283                 name:        "NOR",
25284                 argLen:      2,
25285                 commutative: true,
25286                 asm:         mips.ANOR,
25287                 reg: regInfo{
25288                         inputs: []inputInfo{
25289                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25290                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25291                         },
25292                         outputs: []outputInfo{
25293                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25294                         },
25295                 },
25296         },
25297         {
25298                 name:    "NORconst",
25299                 auxType: auxInt32,
25300                 argLen:  1,
25301                 asm:     mips.ANOR,
25302                 reg: regInfo{
25303                         inputs: []inputInfo{
25304                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25305                         },
25306                         outputs: []outputInfo{
25307                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25308                         },
25309                 },
25310         },
25311         {
25312                 name:   "NEG",
25313                 argLen: 1,
25314                 reg: regInfo{
25315                         inputs: []inputInfo{
25316                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25317                         },
25318                         outputs: []outputInfo{
25319                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25320                         },
25321                 },
25322         },
25323         {
25324                 name:   "NEGF",
25325                 argLen: 1,
25326                 asm:    mips.ANEGF,
25327                 reg: regInfo{
25328                         inputs: []inputInfo{
25329                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25330                         },
25331                         outputs: []outputInfo{
25332                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25333                         },
25334                 },
25335         },
25336         {
25337                 name:   "NEGD",
25338                 argLen: 1,
25339                 asm:    mips.ANEGD,
25340                 reg: regInfo{
25341                         inputs: []inputInfo{
25342                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25343                         },
25344                         outputs: []outputInfo{
25345                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25346                         },
25347                 },
25348         },
25349         {
25350                 name:   "ABSD",
25351                 argLen: 1,
25352                 asm:    mips.AABSD,
25353                 reg: regInfo{
25354                         inputs: []inputInfo{
25355                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25356                         },
25357                         outputs: []outputInfo{
25358                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25359                         },
25360                 },
25361         },
25362         {
25363                 name:   "SQRTD",
25364                 argLen: 1,
25365                 asm:    mips.ASQRTD,
25366                 reg: regInfo{
25367                         inputs: []inputInfo{
25368                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25369                         },
25370                         outputs: []outputInfo{
25371                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25372                         },
25373                 },
25374         },
25375         {
25376                 name:   "SQRTF",
25377                 argLen: 1,
25378                 asm:    mips.ASQRTF,
25379                 reg: regInfo{
25380                         inputs: []inputInfo{
25381                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25382                         },
25383                         outputs: []outputInfo{
25384                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25385                         },
25386                 },
25387         },
25388         {
25389                 name:   "SLL",
25390                 argLen: 2,
25391                 asm:    mips.ASLL,
25392                 reg: regInfo{
25393                         inputs: []inputInfo{
25394                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25395                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25396                         },
25397                         outputs: []outputInfo{
25398                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25399                         },
25400                 },
25401         },
25402         {
25403                 name:    "SLLconst",
25404                 auxType: auxInt32,
25405                 argLen:  1,
25406                 asm:     mips.ASLL,
25407                 reg: regInfo{
25408                         inputs: []inputInfo{
25409                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25410                         },
25411                         outputs: []outputInfo{
25412                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25413                         },
25414                 },
25415         },
25416         {
25417                 name:   "SRL",
25418                 argLen: 2,
25419                 asm:    mips.ASRL,
25420                 reg: regInfo{
25421                         inputs: []inputInfo{
25422                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25423                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25424                         },
25425                         outputs: []outputInfo{
25426                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25427                         },
25428                 },
25429         },
25430         {
25431                 name:    "SRLconst",
25432                 auxType: auxInt32,
25433                 argLen:  1,
25434                 asm:     mips.ASRL,
25435                 reg: regInfo{
25436                         inputs: []inputInfo{
25437                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25438                         },
25439                         outputs: []outputInfo{
25440                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25441                         },
25442                 },
25443         },
25444         {
25445                 name:   "SRA",
25446                 argLen: 2,
25447                 asm:    mips.ASRA,
25448                 reg: regInfo{
25449                         inputs: []inputInfo{
25450                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25451                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25452                         },
25453                         outputs: []outputInfo{
25454                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25455                         },
25456                 },
25457         },
25458         {
25459                 name:    "SRAconst",
25460                 auxType: auxInt32,
25461                 argLen:  1,
25462                 asm:     mips.ASRA,
25463                 reg: regInfo{
25464                         inputs: []inputInfo{
25465                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25466                         },
25467                         outputs: []outputInfo{
25468                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25469                         },
25470                 },
25471         },
25472         {
25473                 name:   "CLZ",
25474                 argLen: 1,
25475                 asm:    mips.ACLZ,
25476                 reg: regInfo{
25477                         inputs: []inputInfo{
25478                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25479                         },
25480                         outputs: []outputInfo{
25481                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25482                         },
25483                 },
25484         },
25485         {
25486                 name:   "SGT",
25487                 argLen: 2,
25488                 asm:    mips.ASGT,
25489                 reg: regInfo{
25490                         inputs: []inputInfo{
25491                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25492                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25493                         },
25494                         outputs: []outputInfo{
25495                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25496                         },
25497                 },
25498         },
25499         {
25500                 name:    "SGTconst",
25501                 auxType: auxInt32,
25502                 argLen:  1,
25503                 asm:     mips.ASGT,
25504                 reg: regInfo{
25505                         inputs: []inputInfo{
25506                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25507                         },
25508                         outputs: []outputInfo{
25509                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25510                         },
25511                 },
25512         },
25513         {
25514                 name:   "SGTzero",
25515                 argLen: 1,
25516                 asm:    mips.ASGT,
25517                 reg: regInfo{
25518                         inputs: []inputInfo{
25519                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25520                         },
25521                         outputs: []outputInfo{
25522                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25523                         },
25524                 },
25525         },
25526         {
25527                 name:   "SGTU",
25528                 argLen: 2,
25529                 asm:    mips.ASGTU,
25530                 reg: regInfo{
25531                         inputs: []inputInfo{
25532                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25533                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25534                         },
25535                         outputs: []outputInfo{
25536                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25537                         },
25538                 },
25539         },
25540         {
25541                 name:    "SGTUconst",
25542                 auxType: auxInt32,
25543                 argLen:  1,
25544                 asm:     mips.ASGTU,
25545                 reg: regInfo{
25546                         inputs: []inputInfo{
25547                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25548                         },
25549                         outputs: []outputInfo{
25550                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25551                         },
25552                 },
25553         },
25554         {
25555                 name:   "SGTUzero",
25556                 argLen: 1,
25557                 asm:    mips.ASGTU,
25558                 reg: regInfo{
25559                         inputs: []inputInfo{
25560                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25561                         },
25562                         outputs: []outputInfo{
25563                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25564                         },
25565                 },
25566         },
25567         {
25568                 name:   "CMPEQF",
25569                 argLen: 2,
25570                 asm:    mips.ACMPEQF,
25571                 reg: regInfo{
25572                         inputs: []inputInfo{
25573                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25574                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25575                         },
25576                 },
25577         },
25578         {
25579                 name:   "CMPEQD",
25580                 argLen: 2,
25581                 asm:    mips.ACMPEQD,
25582                 reg: regInfo{
25583                         inputs: []inputInfo{
25584                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25585                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25586                         },
25587                 },
25588         },
25589         {
25590                 name:   "CMPGEF",
25591                 argLen: 2,
25592                 asm:    mips.ACMPGEF,
25593                 reg: regInfo{
25594                         inputs: []inputInfo{
25595                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25596                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25597                         },
25598                 },
25599         },
25600         {
25601                 name:   "CMPGED",
25602                 argLen: 2,
25603                 asm:    mips.ACMPGED,
25604                 reg: regInfo{
25605                         inputs: []inputInfo{
25606                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25607                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25608                         },
25609                 },
25610         },
25611         {
25612                 name:   "CMPGTF",
25613                 argLen: 2,
25614                 asm:    mips.ACMPGTF,
25615                 reg: regInfo{
25616                         inputs: []inputInfo{
25617                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25618                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25619                         },
25620                 },
25621         },
25622         {
25623                 name:   "CMPGTD",
25624                 argLen: 2,
25625                 asm:    mips.ACMPGTD,
25626                 reg: regInfo{
25627                         inputs: []inputInfo{
25628                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25629                                 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25630                         },
25631                 },
25632         },
25633         {
25634                 name:              "MOVWconst",
25635                 auxType:           auxInt32,
25636                 argLen:            0,
25637                 rematerializeable: true,
25638                 asm:               mips.AMOVW,
25639                 reg: regInfo{
25640                         outputs: []outputInfo{
25641                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25642                         },
25643                 },
25644         },
25645         {
25646                 name:              "MOVFconst",
25647                 auxType:           auxFloat32,
25648                 argLen:            0,
25649                 rematerializeable: true,
25650                 asm:               mips.AMOVF,
25651                 reg: regInfo{
25652                         outputs: []outputInfo{
25653                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25654                         },
25655                 },
25656         },
25657         {
25658                 name:              "MOVDconst",
25659                 auxType:           auxFloat64,
25660                 argLen:            0,
25661                 rematerializeable: true,
25662                 asm:               mips.AMOVD,
25663                 reg: regInfo{
25664                         outputs: []outputInfo{
25665                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25666                         },
25667                 },
25668         },
25669         {
25670                 name:              "MOVWaddr",
25671                 auxType:           auxSymOff,
25672                 argLen:            1,
25673                 rematerializeable: true,
25674                 symEffect:         SymAddr,
25675                 asm:               mips.AMOVW,
25676                 reg: regInfo{
25677                         inputs: []inputInfo{
25678                                 {0, 140737555464192}, // SP SB
25679                         },
25680                         outputs: []outputInfo{
25681                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25682                         },
25683                 },
25684         },
25685         {
25686                 name:           "MOVBload",
25687                 auxType:        auxSymOff,
25688                 argLen:         2,
25689                 faultOnNilArg0: true,
25690                 symEffect:      SymRead,
25691                 asm:            mips.AMOVB,
25692                 reg: regInfo{
25693                         inputs: []inputInfo{
25694                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25695                         },
25696                         outputs: []outputInfo{
25697                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25698                         },
25699                 },
25700         },
25701         {
25702                 name:           "MOVBUload",
25703                 auxType:        auxSymOff,
25704                 argLen:         2,
25705                 faultOnNilArg0: true,
25706                 symEffect:      SymRead,
25707                 asm:            mips.AMOVBU,
25708                 reg: regInfo{
25709                         inputs: []inputInfo{
25710                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25711                         },
25712                         outputs: []outputInfo{
25713                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25714                         },
25715                 },
25716         },
25717         {
25718                 name:           "MOVHload",
25719                 auxType:        auxSymOff,
25720                 argLen:         2,
25721                 faultOnNilArg0: true,
25722                 symEffect:      SymRead,
25723                 asm:            mips.AMOVH,
25724                 reg: regInfo{
25725                         inputs: []inputInfo{
25726                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25727                         },
25728                         outputs: []outputInfo{
25729                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25730                         },
25731                 },
25732         },
25733         {
25734                 name:           "MOVHUload",
25735                 auxType:        auxSymOff,
25736                 argLen:         2,
25737                 faultOnNilArg0: true,
25738                 symEffect:      SymRead,
25739                 asm:            mips.AMOVHU,
25740                 reg: regInfo{
25741                         inputs: []inputInfo{
25742                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25743                         },
25744                         outputs: []outputInfo{
25745                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25746                         },
25747                 },
25748         },
25749         {
25750                 name:           "MOVWload",
25751                 auxType:        auxSymOff,
25752                 argLen:         2,
25753                 faultOnNilArg0: true,
25754                 symEffect:      SymRead,
25755                 asm:            mips.AMOVW,
25756                 reg: regInfo{
25757                         inputs: []inputInfo{
25758                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25759                         },
25760                         outputs: []outputInfo{
25761                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25762                         },
25763                 },
25764         },
25765         {
25766                 name:           "MOVFload",
25767                 auxType:        auxSymOff,
25768                 argLen:         2,
25769                 faultOnNilArg0: true,
25770                 symEffect:      SymRead,
25771                 asm:            mips.AMOVF,
25772                 reg: regInfo{
25773                         inputs: []inputInfo{
25774                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25775                         },
25776                         outputs: []outputInfo{
25777                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25778                         },
25779                 },
25780         },
25781         {
25782                 name:           "MOVDload",
25783                 auxType:        auxSymOff,
25784                 argLen:         2,
25785                 faultOnNilArg0: true,
25786                 symEffect:      SymRead,
25787                 asm:            mips.AMOVD,
25788                 reg: regInfo{
25789                         inputs: []inputInfo{
25790                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25791                         },
25792                         outputs: []outputInfo{
25793                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25794                         },
25795                 },
25796         },
25797         {
25798                 name:           "MOVBstore",
25799                 auxType:        auxSymOff,
25800                 argLen:         3,
25801                 faultOnNilArg0: true,
25802                 symEffect:      SymWrite,
25803                 asm:            mips.AMOVB,
25804                 reg: regInfo{
25805                         inputs: []inputInfo{
25806                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25807                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25808                         },
25809                 },
25810         },
25811         {
25812                 name:           "MOVHstore",
25813                 auxType:        auxSymOff,
25814                 argLen:         3,
25815                 faultOnNilArg0: true,
25816                 symEffect:      SymWrite,
25817                 asm:            mips.AMOVH,
25818                 reg: regInfo{
25819                         inputs: []inputInfo{
25820                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25821                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25822                         },
25823                 },
25824         },
25825         {
25826                 name:           "MOVWstore",
25827                 auxType:        auxSymOff,
25828                 argLen:         3,
25829                 faultOnNilArg0: true,
25830                 symEffect:      SymWrite,
25831                 asm:            mips.AMOVW,
25832                 reg: regInfo{
25833                         inputs: []inputInfo{
25834                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25835                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25836                         },
25837                 },
25838         },
25839         {
25840                 name:           "MOVFstore",
25841                 auxType:        auxSymOff,
25842                 argLen:         3,
25843                 faultOnNilArg0: true,
25844                 symEffect:      SymWrite,
25845                 asm:            mips.AMOVF,
25846                 reg: regInfo{
25847                         inputs: []inputInfo{
25848                                 {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25849                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25850                         },
25851                 },
25852         },
25853         {
25854                 name:           "MOVDstore",
25855                 auxType:        auxSymOff,
25856                 argLen:         3,
25857                 faultOnNilArg0: true,
25858                 symEffect:      SymWrite,
25859                 asm:            mips.AMOVD,
25860                 reg: regInfo{
25861                         inputs: []inputInfo{
25862                                 {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25863                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25864                         },
25865                 },
25866         },
25867         {
25868                 name:           "MOVBstorezero",
25869                 auxType:        auxSymOff,
25870                 argLen:         2,
25871                 faultOnNilArg0: true,
25872                 symEffect:      SymWrite,
25873                 asm:            mips.AMOVB,
25874                 reg: regInfo{
25875                         inputs: []inputInfo{
25876                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25877                         },
25878                 },
25879         },
25880         {
25881                 name:           "MOVHstorezero",
25882                 auxType:        auxSymOff,
25883                 argLen:         2,
25884                 faultOnNilArg0: true,
25885                 symEffect:      SymWrite,
25886                 asm:            mips.AMOVH,
25887                 reg: regInfo{
25888                         inputs: []inputInfo{
25889                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25890                         },
25891                 },
25892         },
25893         {
25894                 name:           "MOVWstorezero",
25895                 auxType:        auxSymOff,
25896                 argLen:         2,
25897                 faultOnNilArg0: true,
25898                 symEffect:      SymWrite,
25899                 asm:            mips.AMOVW,
25900                 reg: regInfo{
25901                         inputs: []inputInfo{
25902                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
25903                         },
25904                 },
25905         },
25906         {
25907                 name:   "MOVWfpgp",
25908                 argLen: 1,
25909                 asm:    mips.AMOVW,
25910                 reg: regInfo{
25911                         inputs: []inputInfo{
25912                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25913                         },
25914                         outputs: []outputInfo{
25915                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25916                         },
25917                 },
25918         },
25919         {
25920                 name:   "MOVWgpfp",
25921                 argLen: 1,
25922                 asm:    mips.AMOVW,
25923                 reg: regInfo{
25924                         inputs: []inputInfo{
25925                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25926                         },
25927                         outputs: []outputInfo{
25928                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
25929                         },
25930                 },
25931         },
25932         {
25933                 name:   "MOVBreg",
25934                 argLen: 1,
25935                 asm:    mips.AMOVB,
25936                 reg: regInfo{
25937                         inputs: []inputInfo{
25938                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25939                         },
25940                         outputs: []outputInfo{
25941                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25942                         },
25943                 },
25944         },
25945         {
25946                 name:   "MOVBUreg",
25947                 argLen: 1,
25948                 asm:    mips.AMOVBU,
25949                 reg: regInfo{
25950                         inputs: []inputInfo{
25951                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25952                         },
25953                         outputs: []outputInfo{
25954                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25955                         },
25956                 },
25957         },
25958         {
25959                 name:   "MOVHreg",
25960                 argLen: 1,
25961                 asm:    mips.AMOVH,
25962                 reg: regInfo{
25963                         inputs: []inputInfo{
25964                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25965                         },
25966                         outputs: []outputInfo{
25967                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25968                         },
25969                 },
25970         },
25971         {
25972                 name:   "MOVHUreg",
25973                 argLen: 1,
25974                 asm:    mips.AMOVHU,
25975                 reg: regInfo{
25976                         inputs: []inputInfo{
25977                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25978                         },
25979                         outputs: []outputInfo{
25980                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25981                         },
25982                 },
25983         },
25984         {
25985                 name:   "MOVWreg",
25986                 argLen: 1,
25987                 asm:    mips.AMOVW,
25988                 reg: regInfo{
25989                         inputs: []inputInfo{
25990                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
25991                         },
25992                         outputs: []outputInfo{
25993                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
25994                         },
25995                 },
25996         },
25997         {
25998                 name:         "MOVWnop",
25999                 argLen:       1,
26000                 resultInArg0: true,
26001                 reg: regInfo{
26002                         inputs: []inputInfo{
26003                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26004                         },
26005                         outputs: []outputInfo{
26006                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26007                         },
26008                 },
26009         },
26010         {
26011                 name:         "CMOVZ",
26012                 argLen:       3,
26013                 resultInArg0: true,
26014                 asm:          mips.ACMOVZ,
26015                 reg: regInfo{
26016                         inputs: []inputInfo{
26017                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26018                                 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26019                                 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26020                         },
26021                         outputs: []outputInfo{
26022                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26023                         },
26024                 },
26025         },
26026         {
26027                 name:         "CMOVZzero",
26028                 argLen:       2,
26029                 resultInArg0: true,
26030                 asm:          mips.ACMOVZ,
26031                 reg: regInfo{
26032                         inputs: []inputInfo{
26033                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26034                                 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26035                         },
26036                         outputs: []outputInfo{
26037                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26038                         },
26039                 },
26040         },
26041         {
26042                 name:   "MOVWF",
26043                 argLen: 1,
26044                 asm:    mips.AMOVWF,
26045                 reg: regInfo{
26046                         inputs: []inputInfo{
26047                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26048                         },
26049                         outputs: []outputInfo{
26050                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26051                         },
26052                 },
26053         },
26054         {
26055                 name:   "MOVWD",
26056                 argLen: 1,
26057                 asm:    mips.AMOVWD,
26058                 reg: regInfo{
26059                         inputs: []inputInfo{
26060                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26061                         },
26062                         outputs: []outputInfo{
26063                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26064                         },
26065                 },
26066         },
26067         {
26068                 name:   "TRUNCFW",
26069                 argLen: 1,
26070                 asm:    mips.ATRUNCFW,
26071                 reg: regInfo{
26072                         inputs: []inputInfo{
26073                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26074                         },
26075                         outputs: []outputInfo{
26076                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26077                         },
26078                 },
26079         },
26080         {
26081                 name:   "TRUNCDW",
26082                 argLen: 1,
26083                 asm:    mips.ATRUNCDW,
26084                 reg: regInfo{
26085                         inputs: []inputInfo{
26086                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26087                         },
26088                         outputs: []outputInfo{
26089                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26090                         },
26091                 },
26092         },
26093         {
26094                 name:   "MOVFD",
26095                 argLen: 1,
26096                 asm:    mips.AMOVFD,
26097                 reg: regInfo{
26098                         inputs: []inputInfo{
26099                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26100                         },
26101                         outputs: []outputInfo{
26102                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26103                         },
26104                 },
26105         },
26106         {
26107                 name:   "MOVDF",
26108                 argLen: 1,
26109                 asm:    mips.AMOVDF,
26110                 reg: regInfo{
26111                         inputs: []inputInfo{
26112                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26113                         },
26114                         outputs: []outputInfo{
26115                                 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
26116                         },
26117                 },
26118         },
26119         {
26120                 name:         "CALLstatic",
26121                 auxType:      auxCallOff,
26122                 argLen:       1,
26123                 clobberFlags: true,
26124                 call:         true,
26125                 reg: regInfo{
26126                         clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
26127                 },
26128         },
26129         {
26130                 name:         "CALLtail",
26131                 auxType:      auxCallOff,
26132                 argLen:       1,
26133                 clobberFlags: true,
26134                 call:         true,
26135                 tailCall:     true,
26136                 reg: regInfo{
26137                         clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
26138                 },
26139         },
26140         {
26141                 name:         "CALLclosure",
26142                 auxType:      auxCallOff,
26143                 argLen:       3,
26144                 clobberFlags: true,
26145                 call:         true,
26146                 reg: regInfo{
26147                         inputs: []inputInfo{
26148                                 {1, 4194304},   // R22
26149                                 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
26150                         },
26151                         clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
26152                 },
26153         },
26154         {
26155                 name:         "CALLinter",
26156                 auxType:      auxCallOff,
26157                 argLen:       2,
26158                 clobberFlags: true,
26159                 call:         true,
26160                 reg: regInfo{
26161                         inputs: []inputInfo{
26162                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26163                         },
26164                         clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
26165                 },
26166         },
26167         {
26168                 name:           "LoweredAtomicLoad8",
26169                 argLen:         2,
26170                 faultOnNilArg0: true,
26171                 reg: regInfo{
26172                         inputs: []inputInfo{
26173                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26174                         },
26175                         outputs: []outputInfo{
26176                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26177                         },
26178                 },
26179         },
26180         {
26181                 name:           "LoweredAtomicLoad32",
26182                 argLen:         2,
26183                 faultOnNilArg0: true,
26184                 reg: regInfo{
26185                         inputs: []inputInfo{
26186                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26187                         },
26188                         outputs: []outputInfo{
26189                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26190                         },
26191                 },
26192         },
26193         {
26194                 name:           "LoweredAtomicStore8",
26195                 argLen:         3,
26196                 faultOnNilArg0: true,
26197                 hasSideEffects: true,
26198                 reg: regInfo{
26199                         inputs: []inputInfo{
26200                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26201                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26202                         },
26203                 },
26204         },
26205         {
26206                 name:           "LoweredAtomicStore32",
26207                 argLen:         3,
26208                 faultOnNilArg0: true,
26209                 hasSideEffects: true,
26210                 reg: regInfo{
26211                         inputs: []inputInfo{
26212                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26213                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26214                         },
26215                 },
26216         },
26217         {
26218                 name:           "LoweredAtomicStorezero",
26219                 argLen:         2,
26220                 faultOnNilArg0: true,
26221                 hasSideEffects: true,
26222                 reg: regInfo{
26223                         inputs: []inputInfo{
26224                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26225                         },
26226                 },
26227         },
26228         {
26229                 name:            "LoweredAtomicExchange",
26230                 argLen:          3,
26231                 resultNotInArgs: true,
26232                 faultOnNilArg0:  true,
26233                 hasSideEffects:  true,
26234                 unsafePoint:     true,
26235                 reg: regInfo{
26236                         inputs: []inputInfo{
26237                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26238                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26239                         },
26240                         outputs: []outputInfo{
26241                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26242                         },
26243                 },
26244         },
26245         {
26246                 name:            "LoweredAtomicAdd",
26247                 argLen:          3,
26248                 resultNotInArgs: true,
26249                 faultOnNilArg0:  true,
26250                 hasSideEffects:  true,
26251                 unsafePoint:     true,
26252                 reg: regInfo{
26253                         inputs: []inputInfo{
26254                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26255                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26256                         },
26257                         outputs: []outputInfo{
26258                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26259                         },
26260                 },
26261         },
26262         {
26263                 name:            "LoweredAtomicAddconst",
26264                 auxType:         auxInt32,
26265                 argLen:          2,
26266                 resultNotInArgs: true,
26267                 faultOnNilArg0:  true,
26268                 hasSideEffects:  true,
26269                 unsafePoint:     true,
26270                 reg: regInfo{
26271                         inputs: []inputInfo{
26272                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26273                         },
26274                         outputs: []outputInfo{
26275                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26276                         },
26277                 },
26278         },
26279         {
26280                 name:            "LoweredAtomicCas",
26281                 argLen:          4,
26282                 resultNotInArgs: true,
26283                 faultOnNilArg0:  true,
26284                 hasSideEffects:  true,
26285                 unsafePoint:     true,
26286                 reg: regInfo{
26287                         inputs: []inputInfo{
26288                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26289                                 {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26290                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26291                         },
26292                         outputs: []outputInfo{
26293                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26294                         },
26295                 },
26296         },
26297         {
26298                 name:           "LoweredAtomicAnd",
26299                 argLen:         3,
26300                 faultOnNilArg0: true,
26301                 hasSideEffects: true,
26302                 unsafePoint:    true,
26303                 asm:            mips.AAND,
26304                 reg: regInfo{
26305                         inputs: []inputInfo{
26306                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26307                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26308                         },
26309                 },
26310         },
26311         {
26312                 name:           "LoweredAtomicOr",
26313                 argLen:         3,
26314                 faultOnNilArg0: true,
26315                 hasSideEffects: true,
26316                 unsafePoint:    true,
26317                 asm:            mips.AOR,
26318                 reg: regInfo{
26319                         inputs: []inputInfo{
26320                                 {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26321                                 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
26322                         },
26323                 },
26324         },
26325         {
26326                 name:           "LoweredZero",
26327                 auxType:        auxInt32,
26328                 argLen:         3,
26329                 faultOnNilArg0: true,
26330                 reg: regInfo{
26331                         inputs: []inputInfo{
26332                                 {0, 2},         // R1
26333                                 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26334                         },
26335                         clobbers: 2, // R1
26336                 },
26337         },
26338         {
26339                 name:           "LoweredMove",
26340                 auxType:        auxInt32,
26341                 argLen:         4,
26342                 faultOnNilArg0: true,
26343                 faultOnNilArg1: true,
26344                 reg: regInfo{
26345                         inputs: []inputInfo{
26346                                 {0, 4},         // R2
26347                                 {1, 2},         // R1
26348                                 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26349                         },
26350                         clobbers: 6, // R1 R2
26351                 },
26352         },
26353         {
26354                 name:           "LoweredNilCheck",
26355                 argLen:         2,
26356                 nilCheck:       true,
26357                 faultOnNilArg0: true,
26358                 reg: regInfo{
26359                         inputs: []inputInfo{
26360                                 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
26361                         },
26362                 },
26363         },
26364         {
26365                 name:   "FPFlagTrue",
26366                 argLen: 1,
26367                 reg: regInfo{
26368                         outputs: []outputInfo{
26369                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26370                         },
26371                 },
26372         },
26373         {
26374                 name:   "FPFlagFalse",
26375                 argLen: 1,
26376                 reg: regInfo{
26377                         outputs: []outputInfo{
26378                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26379                         },
26380                 },
26381         },
26382         {
26383                 name:      "LoweredGetClosurePtr",
26384                 argLen:    0,
26385                 zeroWidth: true,
26386                 reg: regInfo{
26387                         outputs: []outputInfo{
26388                                 {0, 4194304}, // R22
26389                         },
26390                 },
26391         },
26392         {
26393                 name:              "LoweredGetCallerSP",
26394                 argLen:            1,
26395                 rematerializeable: true,
26396                 reg: regInfo{
26397                         outputs: []outputInfo{
26398                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26399                         },
26400                 },
26401         },
26402         {
26403                 name:              "LoweredGetCallerPC",
26404                 argLen:            0,
26405                 rematerializeable: true,
26406                 reg: regInfo{
26407                         outputs: []outputInfo{
26408                                 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
26409                         },
26410                 },
26411         },
26412         {
26413                 name:         "LoweredWB",
26414                 auxType:      auxInt64,
26415                 argLen:       1,
26416                 clobberFlags: true,
26417                 reg: regInfo{
26418                         clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
26419                         outputs: []outputInfo{
26420                                 {0, 16777216}, // R25
26421                         },
26422                 },
26423         },
26424         {
26425                 name:    "LoweredPanicBoundsA",
26426                 auxType: auxInt64,
26427                 argLen:  3,
26428                 call:    true,
26429                 reg: regInfo{
26430                         inputs: []inputInfo{
26431                                 {0, 8},  // R3
26432                                 {1, 16}, // R4
26433                         },
26434                 },
26435         },
26436         {
26437                 name:    "LoweredPanicBoundsB",
26438                 auxType: auxInt64,
26439                 argLen:  3,
26440                 call:    true,
26441                 reg: regInfo{
26442                         inputs: []inputInfo{
26443                                 {0, 4}, // R2
26444                                 {1, 8}, // R3
26445                         },
26446                 },
26447         },
26448         {
26449                 name:    "LoweredPanicBoundsC",
26450                 auxType: auxInt64,
26451                 argLen:  3,
26452                 call:    true,
26453                 reg: regInfo{
26454                         inputs: []inputInfo{
26455                                 {0, 2}, // R1
26456                                 {1, 4}, // R2
26457                         },
26458                 },
26459         },
26460         {
26461                 name:    "LoweredPanicExtendA",
26462                 auxType: auxInt64,
26463                 argLen:  4,
26464                 call:    true,
26465                 reg: regInfo{
26466                         inputs: []inputInfo{
26467                                 {0, 32}, // R5
26468                                 {1, 8},  // R3
26469                                 {2, 16}, // R4
26470                         },
26471                 },
26472         },
26473         {
26474                 name:    "LoweredPanicExtendB",
26475                 auxType: auxInt64,
26476                 argLen:  4,
26477                 call:    true,
26478                 reg: regInfo{
26479                         inputs: []inputInfo{
26480                                 {0, 32}, // R5
26481                                 {1, 4},  // R2
26482                                 {2, 8},  // R3
26483                         },
26484                 },
26485         },
26486         {
26487                 name:    "LoweredPanicExtendC",
26488                 auxType: auxInt64,
26489                 argLen:  4,
26490                 call:    true,
26491                 reg: regInfo{
26492                         inputs: []inputInfo{
26493                                 {0, 32}, // R5
26494                                 {1, 2},  // R1
26495                                 {2, 4},  // R2
26496                         },
26497                 },
26498         },
26499
26500         {
26501                 name:        "ADDV",
26502                 argLen:      2,
26503                 commutative: true,
26504                 asm:         mips.AADDVU,
26505                 reg: regInfo{
26506                         inputs: []inputInfo{
26507                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26508                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26509                         },
26510                         outputs: []outputInfo{
26511                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26512                         },
26513                 },
26514         },
26515         {
26516                 name:    "ADDVconst",
26517                 auxType: auxInt64,
26518                 argLen:  1,
26519                 asm:     mips.AADDVU,
26520                 reg: regInfo{
26521                         inputs: []inputInfo{
26522                                 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
26523                         },
26524                         outputs: []outputInfo{
26525                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26526                         },
26527                 },
26528         },
26529         {
26530                 name:   "SUBV",
26531                 argLen: 2,
26532                 asm:    mips.ASUBVU,
26533                 reg: regInfo{
26534                         inputs: []inputInfo{
26535                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26536                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26537                         },
26538                         outputs: []outputInfo{
26539                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26540                         },
26541                 },
26542         },
26543         {
26544                 name:    "SUBVconst",
26545                 auxType: auxInt64,
26546                 argLen:  1,
26547                 asm:     mips.ASUBVU,
26548                 reg: regInfo{
26549                         inputs: []inputInfo{
26550                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26551                         },
26552                         outputs: []outputInfo{
26553                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26554                         },
26555                 },
26556         },
26557         {
26558                 name:        "MULV",
26559                 argLen:      2,
26560                 commutative: true,
26561                 asm:         mips.AMULV,
26562                 reg: regInfo{
26563                         inputs: []inputInfo{
26564                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26565                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26566                         },
26567                         outputs: []outputInfo{
26568                                 {0, 1152921504606846976}, // HI
26569                                 {1, 2305843009213693952}, // LO
26570                         },
26571                 },
26572         },
26573         {
26574                 name:        "MULVU",
26575                 argLen:      2,
26576                 commutative: true,
26577                 asm:         mips.AMULVU,
26578                 reg: regInfo{
26579                         inputs: []inputInfo{
26580                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26581                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26582                         },
26583                         outputs: []outputInfo{
26584                                 {0, 1152921504606846976}, // HI
26585                                 {1, 2305843009213693952}, // LO
26586                         },
26587                 },
26588         },
26589         {
26590                 name:   "DIVV",
26591                 argLen: 2,
26592                 asm:    mips.ADIVV,
26593                 reg: regInfo{
26594                         inputs: []inputInfo{
26595                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26596                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26597                         },
26598                         outputs: []outputInfo{
26599                                 {0, 1152921504606846976}, // HI
26600                                 {1, 2305843009213693952}, // LO
26601                         },
26602                 },
26603         },
26604         {
26605                 name:   "DIVVU",
26606                 argLen: 2,
26607                 asm:    mips.ADIVVU,
26608                 reg: regInfo{
26609                         inputs: []inputInfo{
26610                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26611                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26612                         },
26613                         outputs: []outputInfo{
26614                                 {0, 1152921504606846976}, // HI
26615                                 {1, 2305843009213693952}, // LO
26616                         },
26617                 },
26618         },
26619         {
26620                 name:        "ADDF",
26621                 argLen:      2,
26622                 commutative: true,
26623                 asm:         mips.AADDF,
26624                 reg: regInfo{
26625                         inputs: []inputInfo{
26626                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26627                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26628                         },
26629                         outputs: []outputInfo{
26630                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26631                         },
26632                 },
26633         },
26634         {
26635                 name:        "ADDD",
26636                 argLen:      2,
26637                 commutative: true,
26638                 asm:         mips.AADDD,
26639                 reg: regInfo{
26640                         inputs: []inputInfo{
26641                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26642                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26643                         },
26644                         outputs: []outputInfo{
26645                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26646                         },
26647                 },
26648         },
26649         {
26650                 name:   "SUBF",
26651                 argLen: 2,
26652                 asm:    mips.ASUBF,
26653                 reg: regInfo{
26654                         inputs: []inputInfo{
26655                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26656                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26657                         },
26658                         outputs: []outputInfo{
26659                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26660                         },
26661                 },
26662         },
26663         {
26664                 name:   "SUBD",
26665                 argLen: 2,
26666                 asm:    mips.ASUBD,
26667                 reg: regInfo{
26668                         inputs: []inputInfo{
26669                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26670                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26671                         },
26672                         outputs: []outputInfo{
26673                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26674                         },
26675                 },
26676         },
26677         {
26678                 name:        "MULF",
26679                 argLen:      2,
26680                 commutative: true,
26681                 asm:         mips.AMULF,
26682                 reg: regInfo{
26683                         inputs: []inputInfo{
26684                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26685                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26686                         },
26687                         outputs: []outputInfo{
26688                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26689                         },
26690                 },
26691         },
26692         {
26693                 name:        "MULD",
26694                 argLen:      2,
26695                 commutative: true,
26696                 asm:         mips.AMULD,
26697                 reg: regInfo{
26698                         inputs: []inputInfo{
26699                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26700                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26701                         },
26702                         outputs: []outputInfo{
26703                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26704                         },
26705                 },
26706         },
26707         {
26708                 name:   "DIVF",
26709                 argLen: 2,
26710                 asm:    mips.ADIVF,
26711                 reg: regInfo{
26712                         inputs: []inputInfo{
26713                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26714                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26715                         },
26716                         outputs: []outputInfo{
26717                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26718                         },
26719                 },
26720         },
26721         {
26722                 name:   "DIVD",
26723                 argLen: 2,
26724                 asm:    mips.ADIVD,
26725                 reg: regInfo{
26726                         inputs: []inputInfo{
26727                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26728                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26729                         },
26730                         outputs: []outputInfo{
26731                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26732                         },
26733                 },
26734         },
26735         {
26736                 name:        "AND",
26737                 argLen:      2,
26738                 commutative: true,
26739                 asm:         mips.AAND,
26740                 reg: regInfo{
26741                         inputs: []inputInfo{
26742                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26743                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26744                         },
26745                         outputs: []outputInfo{
26746                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26747                         },
26748                 },
26749         },
26750         {
26751                 name:    "ANDconst",
26752                 auxType: auxInt64,
26753                 argLen:  1,
26754                 asm:     mips.AAND,
26755                 reg: regInfo{
26756                         inputs: []inputInfo{
26757                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26758                         },
26759                         outputs: []outputInfo{
26760                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26761                         },
26762                 },
26763         },
26764         {
26765                 name:        "OR",
26766                 argLen:      2,
26767                 commutative: true,
26768                 asm:         mips.AOR,
26769                 reg: regInfo{
26770                         inputs: []inputInfo{
26771                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26772                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26773                         },
26774                         outputs: []outputInfo{
26775                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26776                         },
26777                 },
26778         },
26779         {
26780                 name:    "ORconst",
26781                 auxType: auxInt64,
26782                 argLen:  1,
26783                 asm:     mips.AOR,
26784                 reg: regInfo{
26785                         inputs: []inputInfo{
26786                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26787                         },
26788                         outputs: []outputInfo{
26789                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26790                         },
26791                 },
26792         },
26793         {
26794                 name:        "XOR",
26795                 argLen:      2,
26796                 commutative: true,
26797                 asm:         mips.AXOR,
26798                 reg: regInfo{
26799                         inputs: []inputInfo{
26800                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26801                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26802                         },
26803                         outputs: []outputInfo{
26804                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26805                         },
26806                 },
26807         },
26808         {
26809                 name:    "XORconst",
26810                 auxType: auxInt64,
26811                 argLen:  1,
26812                 asm:     mips.AXOR,
26813                 reg: regInfo{
26814                         inputs: []inputInfo{
26815                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26816                         },
26817                         outputs: []outputInfo{
26818                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26819                         },
26820                 },
26821         },
26822         {
26823                 name:        "NOR",
26824                 argLen:      2,
26825                 commutative: true,
26826                 asm:         mips.ANOR,
26827                 reg: regInfo{
26828                         inputs: []inputInfo{
26829                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26830                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26831                         },
26832                         outputs: []outputInfo{
26833                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26834                         },
26835                 },
26836         },
26837         {
26838                 name:    "NORconst",
26839                 auxType: auxInt64,
26840                 argLen:  1,
26841                 asm:     mips.ANOR,
26842                 reg: regInfo{
26843                         inputs: []inputInfo{
26844                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26845                         },
26846                         outputs: []outputInfo{
26847                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26848                         },
26849                 },
26850         },
26851         {
26852                 name:   "NEGV",
26853                 argLen: 1,
26854                 reg: regInfo{
26855                         inputs: []inputInfo{
26856                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26857                         },
26858                         outputs: []outputInfo{
26859                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26860                         },
26861                 },
26862         },
26863         {
26864                 name:   "NEGF",
26865                 argLen: 1,
26866                 asm:    mips.ANEGF,
26867                 reg: regInfo{
26868                         inputs: []inputInfo{
26869                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26870                         },
26871                         outputs: []outputInfo{
26872                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26873                         },
26874                 },
26875         },
26876         {
26877                 name:   "NEGD",
26878                 argLen: 1,
26879                 asm:    mips.ANEGD,
26880                 reg: regInfo{
26881                         inputs: []inputInfo{
26882                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26883                         },
26884                         outputs: []outputInfo{
26885                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26886                         },
26887                 },
26888         },
26889         {
26890                 name:   "ABSD",
26891                 argLen: 1,
26892                 asm:    mips.AABSD,
26893                 reg: regInfo{
26894                         inputs: []inputInfo{
26895                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26896                         },
26897                         outputs: []outputInfo{
26898                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26899                         },
26900                 },
26901         },
26902         {
26903                 name:   "SQRTD",
26904                 argLen: 1,
26905                 asm:    mips.ASQRTD,
26906                 reg: regInfo{
26907                         inputs: []inputInfo{
26908                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26909                         },
26910                         outputs: []outputInfo{
26911                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26912                         },
26913                 },
26914         },
26915         {
26916                 name:   "SQRTF",
26917                 argLen: 1,
26918                 asm:    mips.ASQRTF,
26919                 reg: regInfo{
26920                         inputs: []inputInfo{
26921                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26922                         },
26923                         outputs: []outputInfo{
26924                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26925                         },
26926                 },
26927         },
26928         {
26929                 name:   "SLLV",
26930                 argLen: 2,
26931                 asm:    mips.ASLLV,
26932                 reg: regInfo{
26933                         inputs: []inputInfo{
26934                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26935                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26936                         },
26937                         outputs: []outputInfo{
26938                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26939                         },
26940                 },
26941         },
26942         {
26943                 name:    "SLLVconst",
26944                 auxType: auxInt64,
26945                 argLen:  1,
26946                 asm:     mips.ASLLV,
26947                 reg: regInfo{
26948                         inputs: []inputInfo{
26949                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26950                         },
26951                         outputs: []outputInfo{
26952                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26953                         },
26954                 },
26955         },
26956         {
26957                 name:   "SRLV",
26958                 argLen: 2,
26959                 asm:    mips.ASRLV,
26960                 reg: regInfo{
26961                         inputs: []inputInfo{
26962                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26963                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26964                         },
26965                         outputs: []outputInfo{
26966                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26967                         },
26968                 },
26969         },
26970         {
26971                 name:    "SRLVconst",
26972                 auxType: auxInt64,
26973                 argLen:  1,
26974                 asm:     mips.ASRLV,
26975                 reg: regInfo{
26976                         inputs: []inputInfo{
26977                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26978                         },
26979                         outputs: []outputInfo{
26980                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26981                         },
26982                 },
26983         },
26984         {
26985                 name:   "SRAV",
26986                 argLen: 2,
26987                 asm:    mips.ASRAV,
26988                 reg: regInfo{
26989                         inputs: []inputInfo{
26990                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26991                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
26992                         },
26993                         outputs: []outputInfo{
26994                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
26995                         },
26996                 },
26997         },
26998         {
26999                 name:    "SRAVconst",
27000                 auxType: auxInt64,
27001                 argLen:  1,
27002                 asm:     mips.ASRAV,
27003                 reg: regInfo{
27004                         inputs: []inputInfo{
27005                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27006                         },
27007                         outputs: []outputInfo{
27008                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27009                         },
27010                 },
27011         },
27012         {
27013                 name:   "SGT",
27014                 argLen: 2,
27015                 asm:    mips.ASGT,
27016                 reg: regInfo{
27017                         inputs: []inputInfo{
27018                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27019                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27020                         },
27021                         outputs: []outputInfo{
27022                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27023                         },
27024                 },
27025         },
27026         {
27027                 name:    "SGTconst",
27028                 auxType: auxInt64,
27029                 argLen:  1,
27030                 asm:     mips.ASGT,
27031                 reg: regInfo{
27032                         inputs: []inputInfo{
27033                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27034                         },
27035                         outputs: []outputInfo{
27036                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27037                         },
27038                 },
27039         },
27040         {
27041                 name:   "SGTU",
27042                 argLen: 2,
27043                 asm:    mips.ASGTU,
27044                 reg: regInfo{
27045                         inputs: []inputInfo{
27046                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27047                                 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27048                         },
27049                         outputs: []outputInfo{
27050                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27051                         },
27052                 },
27053         },
27054         {
27055                 name:    "SGTUconst",
27056                 auxType: auxInt64,
27057                 argLen:  1,
27058                 asm:     mips.ASGTU,
27059                 reg: regInfo{
27060                         inputs: []inputInfo{
27061                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27062                         },
27063                         outputs: []outputInfo{
27064                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27065                         },
27066                 },
27067         },
27068         {
27069                 name:   "CMPEQF",
27070                 argLen: 2,
27071                 asm:    mips.ACMPEQF,
27072                 reg: regInfo{
27073                         inputs: []inputInfo{
27074                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27075                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27076                         },
27077                 },
27078         },
27079         {
27080                 name:   "CMPEQD",
27081                 argLen: 2,
27082                 asm:    mips.ACMPEQD,
27083                 reg: regInfo{
27084                         inputs: []inputInfo{
27085                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27086                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27087                         },
27088                 },
27089         },
27090         {
27091                 name:   "CMPGEF",
27092                 argLen: 2,
27093                 asm:    mips.ACMPGEF,
27094                 reg: regInfo{
27095                         inputs: []inputInfo{
27096                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27097                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27098                         },
27099                 },
27100         },
27101         {
27102                 name:   "CMPGED",
27103                 argLen: 2,
27104                 asm:    mips.ACMPGED,
27105                 reg: regInfo{
27106                         inputs: []inputInfo{
27107                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27108                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27109                         },
27110                 },
27111         },
27112         {
27113                 name:   "CMPGTF",
27114                 argLen: 2,
27115                 asm:    mips.ACMPGTF,
27116                 reg: regInfo{
27117                         inputs: []inputInfo{
27118                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27119                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27120                         },
27121                 },
27122         },
27123         {
27124                 name:   "CMPGTD",
27125                 argLen: 2,
27126                 asm:    mips.ACMPGTD,
27127                 reg: regInfo{
27128                         inputs: []inputInfo{
27129                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27130                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27131                         },
27132                 },
27133         },
27134         {
27135                 name:              "MOVVconst",
27136                 auxType:           auxInt64,
27137                 argLen:            0,
27138                 rematerializeable: true,
27139                 asm:               mips.AMOVV,
27140                 reg: regInfo{
27141                         outputs: []outputInfo{
27142                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27143                         },
27144                 },
27145         },
27146         {
27147                 name:              "MOVFconst",
27148                 auxType:           auxFloat64,
27149                 argLen:            0,
27150                 rematerializeable: true,
27151                 asm:               mips.AMOVF,
27152                 reg: regInfo{
27153                         outputs: []outputInfo{
27154                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27155                         },
27156                 },
27157         },
27158         {
27159                 name:              "MOVDconst",
27160                 auxType:           auxFloat64,
27161                 argLen:            0,
27162                 rematerializeable: true,
27163                 asm:               mips.AMOVD,
27164                 reg: regInfo{
27165                         outputs: []outputInfo{
27166                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27167                         },
27168                 },
27169         },
27170         {
27171                 name:              "MOVVaddr",
27172                 auxType:           auxSymOff,
27173                 argLen:            1,
27174                 rematerializeable: true,
27175                 symEffect:         SymAddr,
27176                 asm:               mips.AMOVV,
27177                 reg: regInfo{
27178                         inputs: []inputInfo{
27179                                 {0, 4611686018460942336}, // SP SB
27180                         },
27181                         outputs: []outputInfo{
27182                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27183                         },
27184                 },
27185         },
27186         {
27187                 name:           "MOVBload",
27188                 auxType:        auxSymOff,
27189                 argLen:         2,
27190                 faultOnNilArg0: true,
27191                 symEffect:      SymRead,
27192                 asm:            mips.AMOVB,
27193                 reg: regInfo{
27194                         inputs: []inputInfo{
27195                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27196                         },
27197                         outputs: []outputInfo{
27198                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27199                         },
27200                 },
27201         },
27202         {
27203                 name:           "MOVBUload",
27204                 auxType:        auxSymOff,
27205                 argLen:         2,
27206                 faultOnNilArg0: true,
27207                 symEffect:      SymRead,
27208                 asm:            mips.AMOVBU,
27209                 reg: regInfo{
27210                         inputs: []inputInfo{
27211                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27212                         },
27213                         outputs: []outputInfo{
27214                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27215                         },
27216                 },
27217         },
27218         {
27219                 name:           "MOVHload",
27220                 auxType:        auxSymOff,
27221                 argLen:         2,
27222                 faultOnNilArg0: true,
27223                 symEffect:      SymRead,
27224                 asm:            mips.AMOVH,
27225                 reg: regInfo{
27226                         inputs: []inputInfo{
27227                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27228                         },
27229                         outputs: []outputInfo{
27230                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27231                         },
27232                 },
27233         },
27234         {
27235                 name:           "MOVHUload",
27236                 auxType:        auxSymOff,
27237                 argLen:         2,
27238                 faultOnNilArg0: true,
27239                 symEffect:      SymRead,
27240                 asm:            mips.AMOVHU,
27241                 reg: regInfo{
27242                         inputs: []inputInfo{
27243                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27244                         },
27245                         outputs: []outputInfo{
27246                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27247                         },
27248                 },
27249         },
27250         {
27251                 name:           "MOVWload",
27252                 auxType:        auxSymOff,
27253                 argLen:         2,
27254                 faultOnNilArg0: true,
27255                 symEffect:      SymRead,
27256                 asm:            mips.AMOVW,
27257                 reg: regInfo{
27258                         inputs: []inputInfo{
27259                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27260                         },
27261                         outputs: []outputInfo{
27262                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27263                         },
27264                 },
27265         },
27266         {
27267                 name:           "MOVWUload",
27268                 auxType:        auxSymOff,
27269                 argLen:         2,
27270                 faultOnNilArg0: true,
27271                 symEffect:      SymRead,
27272                 asm:            mips.AMOVWU,
27273                 reg: regInfo{
27274                         inputs: []inputInfo{
27275                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27276                         },
27277                         outputs: []outputInfo{
27278                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27279                         },
27280                 },
27281         },
27282         {
27283                 name:           "MOVVload",
27284                 auxType:        auxSymOff,
27285                 argLen:         2,
27286                 faultOnNilArg0: true,
27287                 symEffect:      SymRead,
27288                 asm:            mips.AMOVV,
27289                 reg: regInfo{
27290                         inputs: []inputInfo{
27291                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27292                         },
27293                         outputs: []outputInfo{
27294                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27295                         },
27296                 },
27297         },
27298         {
27299                 name:           "MOVFload",
27300                 auxType:        auxSymOff,
27301                 argLen:         2,
27302                 faultOnNilArg0: true,
27303                 symEffect:      SymRead,
27304                 asm:            mips.AMOVF,
27305                 reg: regInfo{
27306                         inputs: []inputInfo{
27307                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27308                         },
27309                         outputs: []outputInfo{
27310                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27311                         },
27312                 },
27313         },
27314         {
27315                 name:           "MOVDload",
27316                 auxType:        auxSymOff,
27317                 argLen:         2,
27318                 faultOnNilArg0: true,
27319                 symEffect:      SymRead,
27320                 asm:            mips.AMOVD,
27321                 reg: regInfo{
27322                         inputs: []inputInfo{
27323                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27324                         },
27325                         outputs: []outputInfo{
27326                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27327                         },
27328                 },
27329         },
27330         {
27331                 name:           "MOVBstore",
27332                 auxType:        auxSymOff,
27333                 argLen:         3,
27334                 faultOnNilArg0: true,
27335                 symEffect:      SymWrite,
27336                 asm:            mips.AMOVB,
27337                 reg: regInfo{
27338                         inputs: []inputInfo{
27339                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27340                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27341                         },
27342                 },
27343         },
27344         {
27345                 name:           "MOVHstore",
27346                 auxType:        auxSymOff,
27347                 argLen:         3,
27348                 faultOnNilArg0: true,
27349                 symEffect:      SymWrite,
27350                 asm:            mips.AMOVH,
27351                 reg: regInfo{
27352                         inputs: []inputInfo{
27353                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27354                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27355                         },
27356                 },
27357         },
27358         {
27359                 name:           "MOVWstore",
27360                 auxType:        auxSymOff,
27361                 argLen:         3,
27362                 faultOnNilArg0: true,
27363                 symEffect:      SymWrite,
27364                 asm:            mips.AMOVW,
27365                 reg: regInfo{
27366                         inputs: []inputInfo{
27367                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27368                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27369                         },
27370                 },
27371         },
27372         {
27373                 name:           "MOVVstore",
27374                 auxType:        auxSymOff,
27375                 argLen:         3,
27376                 faultOnNilArg0: true,
27377                 symEffect:      SymWrite,
27378                 asm:            mips.AMOVV,
27379                 reg: regInfo{
27380                         inputs: []inputInfo{
27381                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27382                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27383                         },
27384                 },
27385         },
27386         {
27387                 name:           "MOVFstore",
27388                 auxType:        auxSymOff,
27389                 argLen:         3,
27390                 faultOnNilArg0: true,
27391                 symEffect:      SymWrite,
27392                 asm:            mips.AMOVF,
27393                 reg: regInfo{
27394                         inputs: []inputInfo{
27395                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27396                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27397                         },
27398                 },
27399         },
27400         {
27401                 name:           "MOVDstore",
27402                 auxType:        auxSymOff,
27403                 argLen:         3,
27404                 faultOnNilArg0: true,
27405                 symEffect:      SymWrite,
27406                 asm:            mips.AMOVD,
27407                 reg: regInfo{
27408                         inputs: []inputInfo{
27409                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27410                                 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27411                         },
27412                 },
27413         },
27414         {
27415                 name:           "MOVBstorezero",
27416                 auxType:        auxSymOff,
27417                 argLen:         2,
27418                 faultOnNilArg0: true,
27419                 symEffect:      SymWrite,
27420                 asm:            mips.AMOVB,
27421                 reg: regInfo{
27422                         inputs: []inputInfo{
27423                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27424                         },
27425                 },
27426         },
27427         {
27428                 name:           "MOVHstorezero",
27429                 auxType:        auxSymOff,
27430                 argLen:         2,
27431                 faultOnNilArg0: true,
27432                 symEffect:      SymWrite,
27433                 asm:            mips.AMOVH,
27434                 reg: regInfo{
27435                         inputs: []inputInfo{
27436                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27437                         },
27438                 },
27439         },
27440         {
27441                 name:           "MOVWstorezero",
27442                 auxType:        auxSymOff,
27443                 argLen:         2,
27444                 faultOnNilArg0: true,
27445                 symEffect:      SymWrite,
27446                 asm:            mips.AMOVW,
27447                 reg: regInfo{
27448                         inputs: []inputInfo{
27449                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27450                         },
27451                 },
27452         },
27453         {
27454                 name:           "MOVVstorezero",
27455                 auxType:        auxSymOff,
27456                 argLen:         2,
27457                 faultOnNilArg0: true,
27458                 symEffect:      SymWrite,
27459                 asm:            mips.AMOVV,
27460                 reg: regInfo{
27461                         inputs: []inputInfo{
27462                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27463                         },
27464                 },
27465         },
27466         {
27467                 name:   "MOVWfpgp",
27468                 argLen: 1,
27469                 asm:    mips.AMOVW,
27470                 reg: regInfo{
27471                         inputs: []inputInfo{
27472                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27473                         },
27474                         outputs: []outputInfo{
27475                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27476                         },
27477                 },
27478         },
27479         {
27480                 name:   "MOVWgpfp",
27481                 argLen: 1,
27482                 asm:    mips.AMOVW,
27483                 reg: regInfo{
27484                         inputs: []inputInfo{
27485                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27486                         },
27487                         outputs: []outputInfo{
27488                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27489                         },
27490                 },
27491         },
27492         {
27493                 name:   "MOVVfpgp",
27494                 argLen: 1,
27495                 asm:    mips.AMOVV,
27496                 reg: regInfo{
27497                         inputs: []inputInfo{
27498                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27499                         },
27500                         outputs: []outputInfo{
27501                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27502                         },
27503                 },
27504         },
27505         {
27506                 name:   "MOVVgpfp",
27507                 argLen: 1,
27508                 asm:    mips.AMOVV,
27509                 reg: regInfo{
27510                         inputs: []inputInfo{
27511                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27512                         },
27513                         outputs: []outputInfo{
27514                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27515                         },
27516                 },
27517         },
27518         {
27519                 name:   "MOVBreg",
27520                 argLen: 1,
27521                 asm:    mips.AMOVB,
27522                 reg: regInfo{
27523                         inputs: []inputInfo{
27524                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27525                         },
27526                         outputs: []outputInfo{
27527                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27528                         },
27529                 },
27530         },
27531         {
27532                 name:   "MOVBUreg",
27533                 argLen: 1,
27534                 asm:    mips.AMOVBU,
27535                 reg: regInfo{
27536                         inputs: []inputInfo{
27537                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27538                         },
27539                         outputs: []outputInfo{
27540                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27541                         },
27542                 },
27543         },
27544         {
27545                 name:   "MOVHreg",
27546                 argLen: 1,
27547                 asm:    mips.AMOVH,
27548                 reg: regInfo{
27549                         inputs: []inputInfo{
27550                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27551                         },
27552                         outputs: []outputInfo{
27553                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27554                         },
27555                 },
27556         },
27557         {
27558                 name:   "MOVHUreg",
27559                 argLen: 1,
27560                 asm:    mips.AMOVHU,
27561                 reg: regInfo{
27562                         inputs: []inputInfo{
27563                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27564                         },
27565                         outputs: []outputInfo{
27566                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27567                         },
27568                 },
27569         },
27570         {
27571                 name:   "MOVWreg",
27572                 argLen: 1,
27573                 asm:    mips.AMOVW,
27574                 reg: regInfo{
27575                         inputs: []inputInfo{
27576                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27577                         },
27578                         outputs: []outputInfo{
27579                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27580                         },
27581                 },
27582         },
27583         {
27584                 name:   "MOVWUreg",
27585                 argLen: 1,
27586                 asm:    mips.AMOVWU,
27587                 reg: regInfo{
27588                         inputs: []inputInfo{
27589                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27590                         },
27591                         outputs: []outputInfo{
27592                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27593                         },
27594                 },
27595         },
27596         {
27597                 name:   "MOVVreg",
27598                 argLen: 1,
27599                 asm:    mips.AMOVV,
27600                 reg: regInfo{
27601                         inputs: []inputInfo{
27602                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27603                         },
27604                         outputs: []outputInfo{
27605                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27606                         },
27607                 },
27608         },
27609         {
27610                 name:         "MOVVnop",
27611                 argLen:       1,
27612                 resultInArg0: true,
27613                 reg: regInfo{
27614                         inputs: []inputInfo{
27615                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27616                         },
27617                         outputs: []outputInfo{
27618                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27619                         },
27620                 },
27621         },
27622         {
27623                 name:   "MOVWF",
27624                 argLen: 1,
27625                 asm:    mips.AMOVWF,
27626                 reg: regInfo{
27627                         inputs: []inputInfo{
27628                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27629                         },
27630                         outputs: []outputInfo{
27631                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27632                         },
27633                 },
27634         },
27635         {
27636                 name:   "MOVWD",
27637                 argLen: 1,
27638                 asm:    mips.AMOVWD,
27639                 reg: regInfo{
27640                         inputs: []inputInfo{
27641                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27642                         },
27643                         outputs: []outputInfo{
27644                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27645                         },
27646                 },
27647         },
27648         {
27649                 name:   "MOVVF",
27650                 argLen: 1,
27651                 asm:    mips.AMOVVF,
27652                 reg: regInfo{
27653                         inputs: []inputInfo{
27654                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27655                         },
27656                         outputs: []outputInfo{
27657                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27658                         },
27659                 },
27660         },
27661         {
27662                 name:   "MOVVD",
27663                 argLen: 1,
27664                 asm:    mips.AMOVVD,
27665                 reg: regInfo{
27666                         inputs: []inputInfo{
27667                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27668                         },
27669                         outputs: []outputInfo{
27670                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27671                         },
27672                 },
27673         },
27674         {
27675                 name:   "TRUNCFW",
27676                 argLen: 1,
27677                 asm:    mips.ATRUNCFW,
27678                 reg: regInfo{
27679                         inputs: []inputInfo{
27680                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27681                         },
27682                         outputs: []outputInfo{
27683                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27684                         },
27685                 },
27686         },
27687         {
27688                 name:   "TRUNCDW",
27689                 argLen: 1,
27690                 asm:    mips.ATRUNCDW,
27691                 reg: regInfo{
27692                         inputs: []inputInfo{
27693                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27694                         },
27695                         outputs: []outputInfo{
27696                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27697                         },
27698                 },
27699         },
27700         {
27701                 name:   "TRUNCFV",
27702                 argLen: 1,
27703                 asm:    mips.ATRUNCFV,
27704                 reg: regInfo{
27705                         inputs: []inputInfo{
27706                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27707                         },
27708                         outputs: []outputInfo{
27709                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27710                         },
27711                 },
27712         },
27713         {
27714                 name:   "TRUNCDV",
27715                 argLen: 1,
27716                 asm:    mips.ATRUNCDV,
27717                 reg: regInfo{
27718                         inputs: []inputInfo{
27719                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27720                         },
27721                         outputs: []outputInfo{
27722                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27723                         },
27724                 },
27725         },
27726         {
27727                 name:   "MOVFD",
27728                 argLen: 1,
27729                 asm:    mips.AMOVFD,
27730                 reg: regInfo{
27731                         inputs: []inputInfo{
27732                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27733                         },
27734                         outputs: []outputInfo{
27735                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27736                         },
27737                 },
27738         },
27739         {
27740                 name:   "MOVDF",
27741                 argLen: 1,
27742                 asm:    mips.AMOVDF,
27743                 reg: regInfo{
27744                         inputs: []inputInfo{
27745                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27746                         },
27747                         outputs: []outputInfo{
27748                                 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
27749                         },
27750                 },
27751         },
27752         {
27753                 name:         "CALLstatic",
27754                 auxType:      auxCallOff,
27755                 argLen:       1,
27756                 clobberFlags: true,
27757                 call:         true,
27758                 reg: regInfo{
27759                         clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
27760                 },
27761         },
27762         {
27763                 name:         "CALLtail",
27764                 auxType:      auxCallOff,
27765                 argLen:       1,
27766                 clobberFlags: true,
27767                 call:         true,
27768                 tailCall:     true,
27769                 reg: regInfo{
27770                         clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
27771                 },
27772         },
27773         {
27774                 name:         "CALLclosure",
27775                 auxType:      auxCallOff,
27776                 argLen:       3,
27777                 clobberFlags: true,
27778                 call:         true,
27779                 reg: regInfo{
27780                         inputs: []inputInfo{
27781                                 {1, 4194304},   // R22
27782                                 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
27783                         },
27784                         clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
27785                 },
27786         },
27787         {
27788                 name:         "CALLinter",
27789                 auxType:      auxCallOff,
27790                 argLen:       2,
27791                 clobberFlags: true,
27792                 call:         true,
27793                 reg: regInfo{
27794                         inputs: []inputInfo{
27795                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27796                         },
27797                         clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
27798                 },
27799         },
27800         {
27801                 name:           "DUFFZERO",
27802                 auxType:        auxInt64,
27803                 argLen:         2,
27804                 faultOnNilArg0: true,
27805                 reg: regInfo{
27806                         inputs: []inputInfo{
27807                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27808                         },
27809                         clobbers: 134217730, // R1 R31
27810                 },
27811         },
27812         {
27813                 name:           "DUFFCOPY",
27814                 auxType:        auxInt64,
27815                 argLen:         3,
27816                 faultOnNilArg0: true,
27817                 faultOnNilArg1: true,
27818                 reg: regInfo{
27819                         inputs: []inputInfo{
27820                                 {0, 4}, // R2
27821                                 {1, 2}, // R1
27822                         },
27823                         clobbers: 134217734, // R1 R2 R31
27824                 },
27825         },
27826         {
27827                 name:           "LoweredZero",
27828                 auxType:        auxInt64,
27829                 argLen:         3,
27830                 clobberFlags:   true,
27831                 faultOnNilArg0: true,
27832                 reg: regInfo{
27833                         inputs: []inputInfo{
27834                                 {0, 2},         // R1
27835                                 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27836                         },
27837                         clobbers: 2, // R1
27838                 },
27839         },
27840         {
27841                 name:           "LoweredMove",
27842                 auxType:        auxInt64,
27843                 argLen:         4,
27844                 clobberFlags:   true,
27845                 faultOnNilArg0: true,
27846                 faultOnNilArg1: true,
27847                 reg: regInfo{
27848                         inputs: []inputInfo{
27849                                 {0, 4},         // R2
27850                                 {1, 2},         // R1
27851                                 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27852                         },
27853                         clobbers: 6, // R1 R2
27854                 },
27855         },
27856         {
27857                 name:           "LoweredAtomicAnd32",
27858                 argLen:         3,
27859                 faultOnNilArg0: true,
27860                 hasSideEffects: true,
27861                 unsafePoint:    true,
27862                 asm:            mips.AAND,
27863                 reg: regInfo{
27864                         inputs: []inputInfo{
27865                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27866                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27867                         },
27868                 },
27869         },
27870         {
27871                 name:           "LoweredAtomicOr32",
27872                 argLen:         3,
27873                 faultOnNilArg0: true,
27874                 hasSideEffects: true,
27875                 unsafePoint:    true,
27876                 asm:            mips.AOR,
27877                 reg: regInfo{
27878                         inputs: []inputInfo{
27879                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27880                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27881                         },
27882                 },
27883         },
27884         {
27885                 name:           "LoweredAtomicLoad8",
27886                 argLen:         2,
27887                 faultOnNilArg0: true,
27888                 reg: regInfo{
27889                         inputs: []inputInfo{
27890                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27891                         },
27892                         outputs: []outputInfo{
27893                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27894                         },
27895                 },
27896         },
27897         {
27898                 name:           "LoweredAtomicLoad32",
27899                 argLen:         2,
27900                 faultOnNilArg0: true,
27901                 reg: regInfo{
27902                         inputs: []inputInfo{
27903                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27904                         },
27905                         outputs: []outputInfo{
27906                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27907                         },
27908                 },
27909         },
27910         {
27911                 name:           "LoweredAtomicLoad64",
27912                 argLen:         2,
27913                 faultOnNilArg0: true,
27914                 reg: regInfo{
27915                         inputs: []inputInfo{
27916                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27917                         },
27918                         outputs: []outputInfo{
27919                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27920                         },
27921                 },
27922         },
27923         {
27924                 name:           "LoweredAtomicStore8",
27925                 argLen:         3,
27926                 faultOnNilArg0: true,
27927                 hasSideEffects: true,
27928                 reg: regInfo{
27929                         inputs: []inputInfo{
27930                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27931                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27932                         },
27933                 },
27934         },
27935         {
27936                 name:           "LoweredAtomicStore32",
27937                 argLen:         3,
27938                 faultOnNilArg0: true,
27939                 hasSideEffects: true,
27940                 reg: regInfo{
27941                         inputs: []inputInfo{
27942                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27943                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27944                         },
27945                 },
27946         },
27947         {
27948                 name:           "LoweredAtomicStore64",
27949                 argLen:         3,
27950                 faultOnNilArg0: true,
27951                 hasSideEffects: true,
27952                 reg: regInfo{
27953                         inputs: []inputInfo{
27954                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27955                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27956                         },
27957                 },
27958         },
27959         {
27960                 name:           "LoweredAtomicStorezero32",
27961                 argLen:         2,
27962                 faultOnNilArg0: true,
27963                 hasSideEffects: true,
27964                 reg: regInfo{
27965                         inputs: []inputInfo{
27966                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27967                         },
27968                 },
27969         },
27970         {
27971                 name:           "LoweredAtomicStorezero64",
27972                 argLen:         2,
27973                 faultOnNilArg0: true,
27974                 hasSideEffects: true,
27975                 reg: regInfo{
27976                         inputs: []inputInfo{
27977                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27978                         },
27979                 },
27980         },
27981         {
27982                 name:            "LoweredAtomicExchange32",
27983                 argLen:          3,
27984                 resultNotInArgs: true,
27985                 faultOnNilArg0:  true,
27986                 hasSideEffects:  true,
27987                 unsafePoint:     true,
27988                 reg: regInfo{
27989                         inputs: []inputInfo{
27990                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
27991                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
27992                         },
27993                         outputs: []outputInfo{
27994                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
27995                         },
27996                 },
27997         },
27998         {
27999                 name:            "LoweredAtomicExchange64",
28000                 argLen:          3,
28001                 resultNotInArgs: true,
28002                 faultOnNilArg0:  true,
28003                 hasSideEffects:  true,
28004                 unsafePoint:     true,
28005                 reg: regInfo{
28006                         inputs: []inputInfo{
28007                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28008                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28009                         },
28010                         outputs: []outputInfo{
28011                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28012                         },
28013                 },
28014         },
28015         {
28016                 name:            "LoweredAtomicAdd32",
28017                 argLen:          3,
28018                 resultNotInArgs: true,
28019                 faultOnNilArg0:  true,
28020                 hasSideEffects:  true,
28021                 unsafePoint:     true,
28022                 reg: regInfo{
28023                         inputs: []inputInfo{
28024                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28025                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28026                         },
28027                         outputs: []outputInfo{
28028                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28029                         },
28030                 },
28031         },
28032         {
28033                 name:            "LoweredAtomicAdd64",
28034                 argLen:          3,
28035                 resultNotInArgs: true,
28036                 faultOnNilArg0:  true,
28037                 hasSideEffects:  true,
28038                 unsafePoint:     true,
28039                 reg: regInfo{
28040                         inputs: []inputInfo{
28041                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28042                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28043                         },
28044                         outputs: []outputInfo{
28045                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28046                         },
28047                 },
28048         },
28049         {
28050                 name:            "LoweredAtomicAddconst32",
28051                 auxType:         auxInt32,
28052                 argLen:          2,
28053                 resultNotInArgs: true,
28054                 faultOnNilArg0:  true,
28055                 hasSideEffects:  true,
28056                 unsafePoint:     true,
28057                 reg: regInfo{
28058                         inputs: []inputInfo{
28059                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28060                         },
28061                         outputs: []outputInfo{
28062                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28063                         },
28064                 },
28065         },
28066         {
28067                 name:            "LoweredAtomicAddconst64",
28068                 auxType:         auxInt64,
28069                 argLen:          2,
28070                 resultNotInArgs: true,
28071                 faultOnNilArg0:  true,
28072                 hasSideEffects:  true,
28073                 unsafePoint:     true,
28074                 reg: regInfo{
28075                         inputs: []inputInfo{
28076                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28077                         },
28078                         outputs: []outputInfo{
28079                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28080                         },
28081                 },
28082         },
28083         {
28084                 name:            "LoweredAtomicCas32",
28085                 argLen:          4,
28086                 resultNotInArgs: true,
28087                 faultOnNilArg0:  true,
28088                 hasSideEffects:  true,
28089                 unsafePoint:     true,
28090                 reg: regInfo{
28091                         inputs: []inputInfo{
28092                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28093                                 {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28094                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28095                         },
28096                         outputs: []outputInfo{
28097                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28098                         },
28099                 },
28100         },
28101         {
28102                 name:            "LoweredAtomicCas64",
28103                 argLen:          4,
28104                 resultNotInArgs: true,
28105                 faultOnNilArg0:  true,
28106                 hasSideEffects:  true,
28107                 unsafePoint:     true,
28108                 reg: regInfo{
28109                         inputs: []inputInfo{
28110                                 {1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28111                                 {2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28112                                 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
28113                         },
28114                         outputs: []outputInfo{
28115                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28116                         },
28117                 },
28118         },
28119         {
28120                 name:           "LoweredNilCheck",
28121                 argLen:         2,
28122                 nilCheck:       true,
28123                 faultOnNilArg0: true,
28124                 reg: regInfo{
28125                         inputs: []inputInfo{
28126                                 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
28127                         },
28128                 },
28129         },
28130         {
28131                 name:   "FPFlagTrue",
28132                 argLen: 1,
28133                 reg: regInfo{
28134                         outputs: []outputInfo{
28135                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28136                         },
28137                 },
28138         },
28139         {
28140                 name:   "FPFlagFalse",
28141                 argLen: 1,
28142                 reg: regInfo{
28143                         outputs: []outputInfo{
28144                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28145                         },
28146                 },
28147         },
28148         {
28149                 name:      "LoweredGetClosurePtr",
28150                 argLen:    0,
28151                 zeroWidth: true,
28152                 reg: regInfo{
28153                         outputs: []outputInfo{
28154                                 {0, 4194304}, // R22
28155                         },
28156                 },
28157         },
28158         {
28159                 name:              "LoweredGetCallerSP",
28160                 argLen:            1,
28161                 rematerializeable: true,
28162                 reg: regInfo{
28163                         outputs: []outputInfo{
28164                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28165                         },
28166                 },
28167         },
28168         {
28169                 name:              "LoweredGetCallerPC",
28170                 argLen:            0,
28171                 rematerializeable: true,
28172                 reg: regInfo{
28173                         outputs: []outputInfo{
28174                                 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
28175                         },
28176                 },
28177         },
28178         {
28179                 name:         "LoweredWB",
28180                 auxType:      auxInt64,
28181                 argLen:       1,
28182                 clobberFlags: true,
28183                 reg: regInfo{
28184                         clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
28185                         outputs: []outputInfo{
28186                                 {0, 16777216}, // R25
28187                         },
28188                 },
28189         },
28190         {
28191                 name:    "LoweredPanicBoundsA",
28192                 auxType: auxInt64,
28193                 argLen:  3,
28194                 call:    true,
28195                 reg: regInfo{
28196                         inputs: []inputInfo{
28197                                 {0, 8},  // R3
28198                                 {1, 16}, // R4
28199                         },
28200                 },
28201         },
28202         {
28203                 name:    "LoweredPanicBoundsB",
28204                 auxType: auxInt64,
28205                 argLen:  3,
28206                 call:    true,
28207                 reg: regInfo{
28208                         inputs: []inputInfo{
28209                                 {0, 4}, // R2
28210                                 {1, 8}, // R3
28211                         },
28212                 },
28213         },
28214         {
28215                 name:    "LoweredPanicBoundsC",
28216                 auxType: auxInt64,
28217                 argLen:  3,
28218                 call:    true,
28219                 reg: regInfo{
28220                         inputs: []inputInfo{
28221                                 {0, 2}, // R1
28222                                 {1, 4}, // R2
28223                         },
28224                 },
28225         },
28226
28227         {
28228                 name:        "ADD",
28229                 argLen:      2,
28230                 commutative: true,
28231                 asm:         ppc64.AADD,
28232                 reg: regInfo{
28233                         inputs: []inputInfo{
28234                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28235                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28236                         },
28237                         outputs: []outputInfo{
28238                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28239                         },
28240                 },
28241         },
28242         {
28243                 name:        "ADDCC",
28244                 argLen:      2,
28245                 commutative: true,
28246                 asm:         ppc64.AADDCC,
28247                 reg: regInfo{
28248                         inputs: []inputInfo{
28249                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28250                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28251                         },
28252                         outputs: []outputInfo{
28253                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28254                         },
28255                 },
28256         },
28257         {
28258                 name:    "ADDconst",
28259                 auxType: auxInt64,
28260                 argLen:  1,
28261                 asm:     ppc64.AADD,
28262                 reg: regInfo{
28263                         inputs: []inputInfo{
28264                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28265                         },
28266                         outputs: []outputInfo{
28267                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28268                         },
28269                 },
28270         },
28271         {
28272                 name:    "ADDCCconst",
28273                 auxType: auxInt64,
28274                 argLen:  1,
28275                 asm:     ppc64.AADDCCC,
28276                 reg: regInfo{
28277                         inputs: []inputInfo{
28278                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28279                         },
28280                         clobbers: 9223372036854775808, // XER
28281                         outputs: []outputInfo{
28282                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28283                         },
28284                 },
28285         },
28286         {
28287                 name:        "FADD",
28288                 argLen:      2,
28289                 commutative: true,
28290                 asm:         ppc64.AFADD,
28291                 reg: regInfo{
28292                         inputs: []inputInfo{
28293                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28294                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28295                         },
28296                         outputs: []outputInfo{
28297                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28298                         },
28299                 },
28300         },
28301         {
28302                 name:        "FADDS",
28303                 argLen:      2,
28304                 commutative: true,
28305                 asm:         ppc64.AFADDS,
28306                 reg: regInfo{
28307                         inputs: []inputInfo{
28308                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28309                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28310                         },
28311                         outputs: []outputInfo{
28312                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28313                         },
28314                 },
28315         },
28316         {
28317                 name:   "SUB",
28318                 argLen: 2,
28319                 asm:    ppc64.ASUB,
28320                 reg: regInfo{
28321                         inputs: []inputInfo{
28322                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28323                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28324                         },
28325                         outputs: []outputInfo{
28326                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28327                         },
28328                 },
28329         },
28330         {
28331                 name:   "SUBCC",
28332                 argLen: 2,
28333                 asm:    ppc64.ASUBCC,
28334                 reg: regInfo{
28335                         inputs: []inputInfo{
28336                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28337                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28338                         },
28339                         outputs: []outputInfo{
28340                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28341                         },
28342                 },
28343         },
28344         {
28345                 name:    "SUBFCconst",
28346                 auxType: auxInt64,
28347                 argLen:  1,
28348                 asm:     ppc64.ASUBC,
28349                 reg: regInfo{
28350                         inputs: []inputInfo{
28351                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28352                         },
28353                         clobbers: 9223372036854775808, // XER
28354                         outputs: []outputInfo{
28355                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28356                         },
28357                 },
28358         },
28359         {
28360                 name:   "FSUB",
28361                 argLen: 2,
28362                 asm:    ppc64.AFSUB,
28363                 reg: regInfo{
28364                         inputs: []inputInfo{
28365                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28366                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28367                         },
28368                         outputs: []outputInfo{
28369                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28370                         },
28371                 },
28372         },
28373         {
28374                 name:   "FSUBS",
28375                 argLen: 2,
28376                 asm:    ppc64.AFSUBS,
28377                 reg: regInfo{
28378                         inputs: []inputInfo{
28379                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28380                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28381                         },
28382                         outputs: []outputInfo{
28383                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28384                         },
28385                 },
28386         },
28387         {
28388                 name:        "MULLD",
28389                 argLen:      2,
28390                 commutative: true,
28391                 asm:         ppc64.AMULLD,
28392                 reg: regInfo{
28393                         inputs: []inputInfo{
28394                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28395                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28396                         },
28397                         outputs: []outputInfo{
28398                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28399                         },
28400                 },
28401         },
28402         {
28403                 name:        "MULLW",
28404                 argLen:      2,
28405                 commutative: true,
28406                 asm:         ppc64.AMULLW,
28407                 reg: regInfo{
28408                         inputs: []inputInfo{
28409                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28410                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28411                         },
28412                         outputs: []outputInfo{
28413                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28414                         },
28415                 },
28416         },
28417         {
28418                 name:    "MULLDconst",
28419                 auxType: auxInt32,
28420                 argLen:  1,
28421                 asm:     ppc64.AMULLD,
28422                 reg: regInfo{
28423                         inputs: []inputInfo{
28424                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28425                         },
28426                         outputs: []outputInfo{
28427                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28428                         },
28429                 },
28430         },
28431         {
28432                 name:    "MULLWconst",
28433                 auxType: auxInt32,
28434                 argLen:  1,
28435                 asm:     ppc64.AMULLW,
28436                 reg: regInfo{
28437                         inputs: []inputInfo{
28438                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28439                         },
28440                         outputs: []outputInfo{
28441                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28442                         },
28443                 },
28444         },
28445         {
28446                 name:   "MADDLD",
28447                 argLen: 3,
28448                 asm:    ppc64.AMADDLD,
28449                 reg: regInfo{
28450                         inputs: []inputInfo{
28451                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28452                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28453                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28454                         },
28455                         outputs: []outputInfo{
28456                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28457                         },
28458                 },
28459         },
28460         {
28461                 name:        "MULHD",
28462                 argLen:      2,
28463                 commutative: true,
28464                 asm:         ppc64.AMULHD,
28465                 reg: regInfo{
28466                         inputs: []inputInfo{
28467                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28468                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28469                         },
28470                         outputs: []outputInfo{
28471                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28472                         },
28473                 },
28474         },
28475         {
28476                 name:        "MULHW",
28477                 argLen:      2,
28478                 commutative: true,
28479                 asm:         ppc64.AMULHW,
28480                 reg: regInfo{
28481                         inputs: []inputInfo{
28482                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28483                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28484                         },
28485                         outputs: []outputInfo{
28486                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28487                         },
28488                 },
28489         },
28490         {
28491                 name:        "MULHDU",
28492                 argLen:      2,
28493                 commutative: true,
28494                 asm:         ppc64.AMULHDU,
28495                 reg: regInfo{
28496                         inputs: []inputInfo{
28497                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28498                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28499                         },
28500                         outputs: []outputInfo{
28501                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28502                         },
28503                 },
28504         },
28505         {
28506                 name:        "MULHWU",
28507                 argLen:      2,
28508                 commutative: true,
28509                 asm:         ppc64.AMULHWU,
28510                 reg: regInfo{
28511                         inputs: []inputInfo{
28512                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28513                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28514                         },
28515                         outputs: []outputInfo{
28516                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28517                         },
28518                 },
28519         },
28520         {
28521                 name:        "FMUL",
28522                 argLen:      2,
28523                 commutative: true,
28524                 asm:         ppc64.AFMUL,
28525                 reg: regInfo{
28526                         inputs: []inputInfo{
28527                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28528                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28529                         },
28530                         outputs: []outputInfo{
28531                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28532                         },
28533                 },
28534         },
28535         {
28536                 name:        "FMULS",
28537                 argLen:      2,
28538                 commutative: true,
28539                 asm:         ppc64.AFMULS,
28540                 reg: regInfo{
28541                         inputs: []inputInfo{
28542                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28543                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28544                         },
28545                         outputs: []outputInfo{
28546                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28547                         },
28548                 },
28549         },
28550         {
28551                 name:   "FMADD",
28552                 argLen: 3,
28553                 asm:    ppc64.AFMADD,
28554                 reg: regInfo{
28555                         inputs: []inputInfo{
28556                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28557                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28558                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28559                         },
28560                         outputs: []outputInfo{
28561                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28562                         },
28563                 },
28564         },
28565         {
28566                 name:   "FMADDS",
28567                 argLen: 3,
28568                 asm:    ppc64.AFMADDS,
28569                 reg: regInfo{
28570                         inputs: []inputInfo{
28571                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28572                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28573                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28574                         },
28575                         outputs: []outputInfo{
28576                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28577                         },
28578                 },
28579         },
28580         {
28581                 name:   "FMSUB",
28582                 argLen: 3,
28583                 asm:    ppc64.AFMSUB,
28584                 reg: regInfo{
28585                         inputs: []inputInfo{
28586                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28587                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28588                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28589                         },
28590                         outputs: []outputInfo{
28591                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28592                         },
28593                 },
28594         },
28595         {
28596                 name:   "FMSUBS",
28597                 argLen: 3,
28598                 asm:    ppc64.AFMSUBS,
28599                 reg: regInfo{
28600                         inputs: []inputInfo{
28601                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28602                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28603                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28604                         },
28605                         outputs: []outputInfo{
28606                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
28607                         },
28608                 },
28609         },
28610         {
28611                 name:   "SRAD",
28612                 argLen: 2,
28613                 asm:    ppc64.ASRAD,
28614                 reg: regInfo{
28615                         inputs: []inputInfo{
28616                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28617                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28618                         },
28619                         clobbers: 9223372036854775808, // XER
28620                         outputs: []outputInfo{
28621                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28622                         },
28623                 },
28624         },
28625         {
28626                 name:   "SRAW",
28627                 argLen: 2,
28628                 asm:    ppc64.ASRAW,
28629                 reg: regInfo{
28630                         inputs: []inputInfo{
28631                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28632                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28633                         },
28634                         clobbers: 9223372036854775808, // XER
28635                         outputs: []outputInfo{
28636                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28637                         },
28638                 },
28639         },
28640         {
28641                 name:   "SRD",
28642                 argLen: 2,
28643                 asm:    ppc64.ASRD,
28644                 reg: regInfo{
28645                         inputs: []inputInfo{
28646                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28647                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28648                         },
28649                         outputs: []outputInfo{
28650                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28651                         },
28652                 },
28653         },
28654         {
28655                 name:   "SRW",
28656                 argLen: 2,
28657                 asm:    ppc64.ASRW,
28658                 reg: regInfo{
28659                         inputs: []inputInfo{
28660                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28661                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28662                         },
28663                         outputs: []outputInfo{
28664                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28665                         },
28666                 },
28667         },
28668         {
28669                 name:   "SLD",
28670                 argLen: 2,
28671                 asm:    ppc64.ASLD,
28672                 reg: regInfo{
28673                         inputs: []inputInfo{
28674                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28675                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28676                         },
28677                         outputs: []outputInfo{
28678                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28679                         },
28680                 },
28681         },
28682         {
28683                 name:   "SLW",
28684                 argLen: 2,
28685                 asm:    ppc64.ASLW,
28686                 reg: regInfo{
28687                         inputs: []inputInfo{
28688                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28689                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28690                         },
28691                         outputs: []outputInfo{
28692                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28693                         },
28694                 },
28695         },
28696         {
28697                 name:   "ROTL",
28698                 argLen: 2,
28699                 asm:    ppc64.AROTL,
28700                 reg: regInfo{
28701                         inputs: []inputInfo{
28702                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28703                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28704                         },
28705                         outputs: []outputInfo{
28706                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28707                         },
28708                 },
28709         },
28710         {
28711                 name:   "ROTLW",
28712                 argLen: 2,
28713                 asm:    ppc64.AROTLW,
28714                 reg: regInfo{
28715                         inputs: []inputInfo{
28716                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28717                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28718                         },
28719                         outputs: []outputInfo{
28720                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28721                         },
28722                 },
28723         },
28724         {
28725                 name:    "CLRLSLWI",
28726                 auxType: auxInt32,
28727                 argLen:  1,
28728                 asm:     ppc64.ACLRLSLWI,
28729                 reg: regInfo{
28730                         inputs: []inputInfo{
28731                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28732                         },
28733                         outputs: []outputInfo{
28734                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28735                         },
28736                 },
28737         },
28738         {
28739                 name:    "CLRLSLDI",
28740                 auxType: auxInt32,
28741                 argLen:  1,
28742                 asm:     ppc64.ACLRLSLDI,
28743                 reg: regInfo{
28744                         inputs: []inputInfo{
28745                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28746                         },
28747                         outputs: []outputInfo{
28748                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28749                         },
28750                 },
28751         },
28752         {
28753                 name:        "ADDC",
28754                 argLen:      2,
28755                 commutative: true,
28756                 asm:         ppc64.AADDC,
28757                 reg: regInfo{
28758                         inputs: []inputInfo{
28759                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28760                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28761                         },
28762                         clobbers: 9223372036854775808, // XER
28763                         outputs: []outputInfo{
28764                                 {1, 9223372036854775808}, // XER
28765                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28766                         },
28767                 },
28768         },
28769         {
28770                 name:   "SUBC",
28771                 argLen: 2,
28772                 asm:    ppc64.ASUBC,
28773                 reg: regInfo{
28774                         inputs: []inputInfo{
28775                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28776                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28777                         },
28778                         clobbers: 9223372036854775808, // XER
28779                         outputs: []outputInfo{
28780                                 {1, 9223372036854775808}, // XER
28781                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28782                         },
28783                 },
28784         },
28785         {
28786                 name:    "ADDCconst",
28787                 auxType: auxInt64,
28788                 argLen:  1,
28789                 asm:     ppc64.AADDC,
28790                 reg: regInfo{
28791                         inputs: []inputInfo{
28792                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28793                         },
28794                         outputs: []outputInfo{
28795                                 {1, 9223372036854775808}, // XER
28796                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28797                         },
28798                 },
28799         },
28800         {
28801                 name:    "SUBCconst",
28802                 auxType: auxInt64,
28803                 argLen:  1,
28804                 asm:     ppc64.ASUBC,
28805                 reg: regInfo{
28806                         inputs: []inputInfo{
28807                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28808                         },
28809                         outputs: []outputInfo{
28810                                 {1, 9223372036854775808}, // XER
28811                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28812                         },
28813                 },
28814         },
28815         {
28816                 name:        "ADDE",
28817                 argLen:      3,
28818                 commutative: true,
28819                 asm:         ppc64.AADDE,
28820                 reg: regInfo{
28821                         inputs: []inputInfo{
28822                                 {2, 9223372036854775808}, // XER
28823                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28824                                 {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28825                         },
28826                         clobbers: 9223372036854775808, // XER
28827                         outputs: []outputInfo{
28828                                 {1, 9223372036854775808}, // XER
28829                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28830                         },
28831                 },
28832         },
28833         {
28834                 name:   "SUBE",
28835                 argLen: 3,
28836                 asm:    ppc64.ASUBE,
28837                 reg: regInfo{
28838                         inputs: []inputInfo{
28839                                 {2, 9223372036854775808}, // XER
28840                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28841                                 {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28842                         },
28843                         clobbers: 9223372036854775808, // XER
28844                         outputs: []outputInfo{
28845                                 {1, 9223372036854775808}, // XER
28846                                 {0, 1073733624},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28847                         },
28848                 },
28849         },
28850         {
28851                 name:   "ADDZEzero",
28852                 argLen: 1,
28853                 asm:    ppc64.AADDZE,
28854                 reg: regInfo{
28855                         inputs: []inputInfo{
28856                                 {0, 9223372036854775808}, // XER
28857                         },
28858                         clobbers: 9223372036854775808, // XER
28859                         outputs: []outputInfo{
28860                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28861                         },
28862                 },
28863         },
28864         {
28865                 name:   "SUBZEzero",
28866                 argLen: 1,
28867                 asm:    ppc64.ASUBZE,
28868                 reg: regInfo{
28869                         inputs: []inputInfo{
28870                                 {0, 9223372036854775808}, // XER
28871                         },
28872                         clobbers: 9223372036854775808, // XER
28873                         outputs: []outputInfo{
28874                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28875                         },
28876                 },
28877         },
28878         {
28879                 name:    "SRADconst",
28880                 auxType: auxInt64,
28881                 argLen:  1,
28882                 asm:     ppc64.ASRAD,
28883                 reg: regInfo{
28884                         inputs: []inputInfo{
28885                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28886                         },
28887                         clobbers: 9223372036854775808, // XER
28888                         outputs: []outputInfo{
28889                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28890                         },
28891                 },
28892         },
28893         {
28894                 name:    "SRAWconst",
28895                 auxType: auxInt64,
28896                 argLen:  1,
28897                 asm:     ppc64.ASRAW,
28898                 reg: regInfo{
28899                         inputs: []inputInfo{
28900                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28901                         },
28902                         clobbers: 9223372036854775808, // XER
28903                         outputs: []outputInfo{
28904                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28905                         },
28906                 },
28907         },
28908         {
28909                 name:    "SRDconst",
28910                 auxType: auxInt64,
28911                 argLen:  1,
28912                 asm:     ppc64.ASRD,
28913                 reg: regInfo{
28914                         inputs: []inputInfo{
28915                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28916                         },
28917                         outputs: []outputInfo{
28918                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28919                         },
28920                 },
28921         },
28922         {
28923                 name:    "SRWconst",
28924                 auxType: auxInt64,
28925                 argLen:  1,
28926                 asm:     ppc64.ASRW,
28927                 reg: regInfo{
28928                         inputs: []inputInfo{
28929                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28930                         },
28931                         outputs: []outputInfo{
28932                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28933                         },
28934                 },
28935         },
28936         {
28937                 name:    "SLDconst",
28938                 auxType: auxInt64,
28939                 argLen:  1,
28940                 asm:     ppc64.ASLD,
28941                 reg: regInfo{
28942                         inputs: []inputInfo{
28943                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28944                         },
28945                         outputs: []outputInfo{
28946                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28947                         },
28948                 },
28949         },
28950         {
28951                 name:    "SLWconst",
28952                 auxType: auxInt64,
28953                 argLen:  1,
28954                 asm:     ppc64.ASLW,
28955                 reg: regInfo{
28956                         inputs: []inputInfo{
28957                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28958                         },
28959                         outputs: []outputInfo{
28960                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28961                         },
28962                 },
28963         },
28964         {
28965                 name:    "ROTLconst",
28966                 auxType: auxInt64,
28967                 argLen:  1,
28968                 asm:     ppc64.AROTL,
28969                 reg: regInfo{
28970                         inputs: []inputInfo{
28971                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28972                         },
28973                         outputs: []outputInfo{
28974                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28975                         },
28976                 },
28977         },
28978         {
28979                 name:    "ROTLWconst",
28980                 auxType: auxInt64,
28981                 argLen:  1,
28982                 asm:     ppc64.AROTLW,
28983                 reg: regInfo{
28984                         inputs: []inputInfo{
28985                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28986                         },
28987                         outputs: []outputInfo{
28988                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
28989                         },
28990                 },
28991         },
28992         {
28993                 name:    "EXTSWSLconst",
28994                 auxType: auxInt64,
28995                 argLen:  1,
28996                 asm:     ppc64.AEXTSWSLI,
28997                 reg: regInfo{
28998                         inputs: []inputInfo{
28999                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29000                         },
29001                         outputs: []outputInfo{
29002                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29003                         },
29004                 },
29005         },
29006         {
29007                 name:    "RLWINM",
29008                 auxType: auxInt64,
29009                 argLen:  1,
29010                 asm:     ppc64.ARLWNM,
29011                 reg: regInfo{
29012                         inputs: []inputInfo{
29013                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29014                         },
29015                         outputs: []outputInfo{
29016                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29017                         },
29018                 },
29019         },
29020         {
29021                 name:    "RLWNM",
29022                 auxType: auxInt64,
29023                 argLen:  2,
29024                 asm:     ppc64.ARLWNM,
29025                 reg: regInfo{
29026                         inputs: []inputInfo{
29027                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29028                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29029                         },
29030                         outputs: []outputInfo{
29031                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29032                         },
29033                 },
29034         },
29035         {
29036                 name:         "RLWMI",
29037                 auxType:      auxInt64,
29038                 argLen:       2,
29039                 resultInArg0: true,
29040                 asm:          ppc64.ARLWMI,
29041                 reg: regInfo{
29042                         inputs: []inputInfo{
29043                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29044                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29045                         },
29046                         outputs: []outputInfo{
29047                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29048                         },
29049                 },
29050         },
29051         {
29052                 name:    "RLDICL",
29053                 auxType: auxInt64,
29054                 argLen:  1,
29055                 asm:     ppc64.ARLDICL,
29056                 reg: regInfo{
29057                         inputs: []inputInfo{
29058                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29059                         },
29060                         outputs: []outputInfo{
29061                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29062                         },
29063                 },
29064         },
29065         {
29066                 name:    "RLDICR",
29067                 auxType: auxInt64,
29068                 argLen:  1,
29069                 asm:     ppc64.ARLDICR,
29070                 reg: regInfo{
29071                         inputs: []inputInfo{
29072                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29073                         },
29074                         outputs: []outputInfo{
29075                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29076                         },
29077                 },
29078         },
29079         {
29080                 name:   "CNTLZD",
29081                 argLen: 1,
29082                 asm:    ppc64.ACNTLZD,
29083                 reg: regInfo{
29084                         inputs: []inputInfo{
29085                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29086                         },
29087                         outputs: []outputInfo{
29088                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29089                         },
29090                 },
29091         },
29092         {
29093                 name:   "CNTLZDCC",
29094                 argLen: 1,
29095                 asm:    ppc64.ACNTLZDCC,
29096                 reg: regInfo{
29097                         inputs: []inputInfo{
29098                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29099                         },
29100                         outputs: []outputInfo{
29101                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29102                         },
29103                 },
29104         },
29105         {
29106                 name:   "CNTLZW",
29107                 argLen: 1,
29108                 asm:    ppc64.ACNTLZW,
29109                 reg: regInfo{
29110                         inputs: []inputInfo{
29111                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29112                         },
29113                         outputs: []outputInfo{
29114                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29115                         },
29116                 },
29117         },
29118         {
29119                 name:   "CNTTZD",
29120                 argLen: 1,
29121                 asm:    ppc64.ACNTTZD,
29122                 reg: regInfo{
29123                         inputs: []inputInfo{
29124                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29125                         },
29126                         outputs: []outputInfo{
29127                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29128                         },
29129                 },
29130         },
29131         {
29132                 name:   "CNTTZW",
29133                 argLen: 1,
29134                 asm:    ppc64.ACNTTZW,
29135                 reg: regInfo{
29136                         inputs: []inputInfo{
29137                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29138                         },
29139                         outputs: []outputInfo{
29140                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29141                         },
29142                 },
29143         },
29144         {
29145                 name:   "POPCNTD",
29146                 argLen: 1,
29147                 asm:    ppc64.APOPCNTD,
29148                 reg: regInfo{
29149                         inputs: []inputInfo{
29150                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29151                         },
29152                         outputs: []outputInfo{
29153                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29154                         },
29155                 },
29156         },
29157         {
29158                 name:   "POPCNTW",
29159                 argLen: 1,
29160                 asm:    ppc64.APOPCNTW,
29161                 reg: regInfo{
29162                         inputs: []inputInfo{
29163                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29164                         },
29165                         outputs: []outputInfo{
29166                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29167                         },
29168                 },
29169         },
29170         {
29171                 name:   "POPCNTB",
29172                 argLen: 1,
29173                 asm:    ppc64.APOPCNTB,
29174                 reg: regInfo{
29175                         inputs: []inputInfo{
29176                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29177                         },
29178                         outputs: []outputInfo{
29179                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29180                         },
29181                 },
29182         },
29183         {
29184                 name:   "FDIV",
29185                 argLen: 2,
29186                 asm:    ppc64.AFDIV,
29187                 reg: regInfo{
29188                         inputs: []inputInfo{
29189                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29190                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29191                         },
29192                         outputs: []outputInfo{
29193                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29194                         },
29195                 },
29196         },
29197         {
29198                 name:   "FDIVS",
29199                 argLen: 2,
29200                 asm:    ppc64.AFDIVS,
29201                 reg: regInfo{
29202                         inputs: []inputInfo{
29203                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29204                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29205                         },
29206                         outputs: []outputInfo{
29207                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29208                         },
29209                 },
29210         },
29211         {
29212                 name:   "DIVD",
29213                 argLen: 2,
29214                 asm:    ppc64.ADIVD,
29215                 reg: regInfo{
29216                         inputs: []inputInfo{
29217                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29218                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29219                         },
29220                         outputs: []outputInfo{
29221                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29222                         },
29223                 },
29224         },
29225         {
29226                 name:   "DIVW",
29227                 argLen: 2,
29228                 asm:    ppc64.ADIVW,
29229                 reg: regInfo{
29230                         inputs: []inputInfo{
29231                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29232                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29233                         },
29234                         outputs: []outputInfo{
29235                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29236                         },
29237                 },
29238         },
29239         {
29240                 name:   "DIVDU",
29241                 argLen: 2,
29242                 asm:    ppc64.ADIVDU,
29243                 reg: regInfo{
29244                         inputs: []inputInfo{
29245                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29246                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29247                         },
29248                         outputs: []outputInfo{
29249                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29250                         },
29251                 },
29252         },
29253         {
29254                 name:   "DIVWU",
29255                 argLen: 2,
29256                 asm:    ppc64.ADIVWU,
29257                 reg: regInfo{
29258                         inputs: []inputInfo{
29259                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29260                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29261                         },
29262                         outputs: []outputInfo{
29263                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29264                         },
29265                 },
29266         },
29267         {
29268                 name:   "MODUD",
29269                 argLen: 2,
29270                 asm:    ppc64.AMODUD,
29271                 reg: regInfo{
29272                         inputs: []inputInfo{
29273                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29274                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29275                         },
29276                         outputs: []outputInfo{
29277                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29278                         },
29279                 },
29280         },
29281         {
29282                 name:   "MODSD",
29283                 argLen: 2,
29284                 asm:    ppc64.AMODSD,
29285                 reg: regInfo{
29286                         inputs: []inputInfo{
29287                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29288                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29289                         },
29290                         outputs: []outputInfo{
29291                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29292                         },
29293                 },
29294         },
29295         {
29296                 name:   "MODUW",
29297                 argLen: 2,
29298                 asm:    ppc64.AMODUW,
29299                 reg: regInfo{
29300                         inputs: []inputInfo{
29301                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29302                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29303                         },
29304                         outputs: []outputInfo{
29305                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29306                         },
29307                 },
29308         },
29309         {
29310                 name:   "MODSW",
29311                 argLen: 2,
29312                 asm:    ppc64.AMODSW,
29313                 reg: regInfo{
29314                         inputs: []inputInfo{
29315                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29316                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29317                         },
29318                         outputs: []outputInfo{
29319                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29320                         },
29321                 },
29322         },
29323         {
29324                 name:   "FCTIDZ",
29325                 argLen: 1,
29326                 asm:    ppc64.AFCTIDZ,
29327                 reg: regInfo{
29328                         inputs: []inputInfo{
29329                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29330                         },
29331                         outputs: []outputInfo{
29332                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29333                         },
29334                 },
29335         },
29336         {
29337                 name:   "FCTIWZ",
29338                 argLen: 1,
29339                 asm:    ppc64.AFCTIWZ,
29340                 reg: regInfo{
29341                         inputs: []inputInfo{
29342                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29343                         },
29344                         outputs: []outputInfo{
29345                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29346                         },
29347                 },
29348         },
29349         {
29350                 name:   "FCFID",
29351                 argLen: 1,
29352                 asm:    ppc64.AFCFID,
29353                 reg: regInfo{
29354                         inputs: []inputInfo{
29355                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29356                         },
29357                         outputs: []outputInfo{
29358                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29359                         },
29360                 },
29361         },
29362         {
29363                 name:   "FCFIDS",
29364                 argLen: 1,
29365                 asm:    ppc64.AFCFIDS,
29366                 reg: regInfo{
29367                         inputs: []inputInfo{
29368                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29369                         },
29370                         outputs: []outputInfo{
29371                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29372                         },
29373                 },
29374         },
29375         {
29376                 name:   "FRSP",
29377                 argLen: 1,
29378                 asm:    ppc64.AFRSP,
29379                 reg: regInfo{
29380                         inputs: []inputInfo{
29381                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29382                         },
29383                         outputs: []outputInfo{
29384                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29385                         },
29386                 },
29387         },
29388         {
29389                 name:   "MFVSRD",
29390                 argLen: 1,
29391                 asm:    ppc64.AMFVSRD,
29392                 reg: regInfo{
29393                         inputs: []inputInfo{
29394                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29395                         },
29396                         outputs: []outputInfo{
29397                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29398                         },
29399                 },
29400         },
29401         {
29402                 name:   "MTVSRD",
29403                 argLen: 1,
29404                 asm:    ppc64.AMTVSRD,
29405                 reg: regInfo{
29406                         inputs: []inputInfo{
29407                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29408                         },
29409                         outputs: []outputInfo{
29410                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29411                         },
29412                 },
29413         },
29414         {
29415                 name:        "AND",
29416                 argLen:      2,
29417                 commutative: true,
29418                 asm:         ppc64.AAND,
29419                 reg: regInfo{
29420                         inputs: []inputInfo{
29421                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29422                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29423                         },
29424                         outputs: []outputInfo{
29425                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29426                         },
29427                 },
29428         },
29429         {
29430                 name:   "ANDN",
29431                 argLen: 2,
29432                 asm:    ppc64.AANDN,
29433                 reg: regInfo{
29434                         inputs: []inputInfo{
29435                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29436                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29437                         },
29438                         outputs: []outputInfo{
29439                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29440                         },
29441                 },
29442         },
29443         {
29444                 name:   "ANDNCC",
29445                 argLen: 2,
29446                 asm:    ppc64.AANDNCC,
29447                 reg: regInfo{
29448                         inputs: []inputInfo{
29449                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29450                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29451                         },
29452                         outputs: []outputInfo{
29453                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29454                         },
29455                 },
29456         },
29457         {
29458                 name:        "ANDCC",
29459                 argLen:      2,
29460                 commutative: true,
29461                 asm:         ppc64.AANDCC,
29462                 reg: regInfo{
29463                         inputs: []inputInfo{
29464                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29465                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29466                         },
29467                         outputs: []outputInfo{
29468                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29469                         },
29470                 },
29471         },
29472         {
29473                 name:        "OR",
29474                 argLen:      2,
29475                 commutative: true,
29476                 asm:         ppc64.AOR,
29477                 reg: regInfo{
29478                         inputs: []inputInfo{
29479                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29480                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29481                         },
29482                         outputs: []outputInfo{
29483                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29484                         },
29485                 },
29486         },
29487         {
29488                 name:   "ORN",
29489                 argLen: 2,
29490                 asm:    ppc64.AORN,
29491                 reg: regInfo{
29492                         inputs: []inputInfo{
29493                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29494                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29495                         },
29496                         outputs: []outputInfo{
29497                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29498                         },
29499                 },
29500         },
29501         {
29502                 name:        "ORCC",
29503                 argLen:      2,
29504                 commutative: true,
29505                 asm:         ppc64.AORCC,
29506                 reg: regInfo{
29507                         inputs: []inputInfo{
29508                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29509                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29510                         },
29511                         outputs: []outputInfo{
29512                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29513                         },
29514                 },
29515         },
29516         {
29517                 name:        "NOR",
29518                 argLen:      2,
29519                 commutative: true,
29520                 asm:         ppc64.ANOR,
29521                 reg: regInfo{
29522                         inputs: []inputInfo{
29523                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29524                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29525                         },
29526                         outputs: []outputInfo{
29527                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29528                         },
29529                 },
29530         },
29531         {
29532                 name:        "NORCC",
29533                 argLen:      2,
29534                 commutative: true,
29535                 asm:         ppc64.ANORCC,
29536                 reg: regInfo{
29537                         inputs: []inputInfo{
29538                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29539                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29540                         },
29541                         outputs: []outputInfo{
29542                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29543                         },
29544                 },
29545         },
29546         {
29547                 name:        "XOR",
29548                 argLen:      2,
29549                 commutative: true,
29550                 asm:         ppc64.AXOR,
29551                 reg: regInfo{
29552                         inputs: []inputInfo{
29553                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29554                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29555                         },
29556                         outputs: []outputInfo{
29557                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29558                         },
29559                 },
29560         },
29561         {
29562                 name:        "XORCC",
29563                 argLen:      2,
29564                 commutative: true,
29565                 asm:         ppc64.AXORCC,
29566                 reg: regInfo{
29567                         inputs: []inputInfo{
29568                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29569                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29570                         },
29571                         outputs: []outputInfo{
29572                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29573                         },
29574                 },
29575         },
29576         {
29577                 name:        "EQV",
29578                 argLen:      2,
29579                 commutative: true,
29580                 asm:         ppc64.AEQV,
29581                 reg: regInfo{
29582                         inputs: []inputInfo{
29583                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29584                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29585                         },
29586                         outputs: []outputInfo{
29587                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29588                         },
29589                 },
29590         },
29591         {
29592                 name:   "NEG",
29593                 argLen: 1,
29594                 asm:    ppc64.ANEG,
29595                 reg: regInfo{
29596                         inputs: []inputInfo{
29597                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29598                         },
29599                         outputs: []outputInfo{
29600                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29601                         },
29602                 },
29603         },
29604         {
29605                 name:   "NEGCC",
29606                 argLen: 1,
29607                 asm:    ppc64.ANEGCC,
29608                 reg: regInfo{
29609                         inputs: []inputInfo{
29610                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29611                         },
29612                         outputs: []outputInfo{
29613                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29614                         },
29615                 },
29616         },
29617         {
29618                 name:   "BRD",
29619                 argLen: 1,
29620                 asm:    ppc64.ABRD,
29621                 reg: regInfo{
29622                         inputs: []inputInfo{
29623                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29624                         },
29625                         outputs: []outputInfo{
29626                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29627                         },
29628                 },
29629         },
29630         {
29631                 name:   "BRW",
29632                 argLen: 1,
29633                 asm:    ppc64.ABRW,
29634                 reg: regInfo{
29635                         inputs: []inputInfo{
29636                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29637                         },
29638                         outputs: []outputInfo{
29639                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29640                         },
29641                 },
29642         },
29643         {
29644                 name:   "BRH",
29645                 argLen: 1,
29646                 asm:    ppc64.ABRH,
29647                 reg: regInfo{
29648                         inputs: []inputInfo{
29649                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29650                         },
29651                         outputs: []outputInfo{
29652                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29653                         },
29654                 },
29655         },
29656         {
29657                 name:   "FNEG",
29658                 argLen: 1,
29659                 asm:    ppc64.AFNEG,
29660                 reg: regInfo{
29661                         inputs: []inputInfo{
29662                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29663                         },
29664                         outputs: []outputInfo{
29665                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29666                         },
29667                 },
29668         },
29669         {
29670                 name:   "FSQRT",
29671                 argLen: 1,
29672                 asm:    ppc64.AFSQRT,
29673                 reg: regInfo{
29674                         inputs: []inputInfo{
29675                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29676                         },
29677                         outputs: []outputInfo{
29678                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29679                         },
29680                 },
29681         },
29682         {
29683                 name:   "FSQRTS",
29684                 argLen: 1,
29685                 asm:    ppc64.AFSQRTS,
29686                 reg: regInfo{
29687                         inputs: []inputInfo{
29688                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29689                         },
29690                         outputs: []outputInfo{
29691                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29692                         },
29693                 },
29694         },
29695         {
29696                 name:   "FFLOOR",
29697                 argLen: 1,
29698                 asm:    ppc64.AFRIM,
29699                 reg: regInfo{
29700                         inputs: []inputInfo{
29701                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29702                         },
29703                         outputs: []outputInfo{
29704                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29705                         },
29706                 },
29707         },
29708         {
29709                 name:   "FCEIL",
29710                 argLen: 1,
29711                 asm:    ppc64.AFRIP,
29712                 reg: regInfo{
29713                         inputs: []inputInfo{
29714                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29715                         },
29716                         outputs: []outputInfo{
29717                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29718                         },
29719                 },
29720         },
29721         {
29722                 name:   "FTRUNC",
29723                 argLen: 1,
29724                 asm:    ppc64.AFRIZ,
29725                 reg: regInfo{
29726                         inputs: []inputInfo{
29727                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29728                         },
29729                         outputs: []outputInfo{
29730                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29731                         },
29732                 },
29733         },
29734         {
29735                 name:   "FROUND",
29736                 argLen: 1,
29737                 asm:    ppc64.AFRIN,
29738                 reg: regInfo{
29739                         inputs: []inputInfo{
29740                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29741                         },
29742                         outputs: []outputInfo{
29743                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29744                         },
29745                 },
29746         },
29747         {
29748                 name:   "FABS",
29749                 argLen: 1,
29750                 asm:    ppc64.AFABS,
29751                 reg: regInfo{
29752                         inputs: []inputInfo{
29753                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29754                         },
29755                         outputs: []outputInfo{
29756                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29757                         },
29758                 },
29759         },
29760         {
29761                 name:   "FNABS",
29762                 argLen: 1,
29763                 asm:    ppc64.AFNABS,
29764                 reg: regInfo{
29765                         inputs: []inputInfo{
29766                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29767                         },
29768                         outputs: []outputInfo{
29769                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29770                         },
29771                 },
29772         },
29773         {
29774                 name:   "FCPSGN",
29775                 argLen: 2,
29776                 asm:    ppc64.AFCPSGN,
29777                 reg: regInfo{
29778                         inputs: []inputInfo{
29779                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29780                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29781                         },
29782                         outputs: []outputInfo{
29783                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
29784                         },
29785                 },
29786         },
29787         {
29788                 name:    "ORconst",
29789                 auxType: auxInt64,
29790                 argLen:  1,
29791                 asm:     ppc64.AOR,
29792                 reg: regInfo{
29793                         inputs: []inputInfo{
29794                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29795                         },
29796                         outputs: []outputInfo{
29797                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29798                         },
29799                 },
29800         },
29801         {
29802                 name:    "XORconst",
29803                 auxType: auxInt64,
29804                 argLen:  1,
29805                 asm:     ppc64.AXOR,
29806                 reg: regInfo{
29807                         inputs: []inputInfo{
29808                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29809                         },
29810                         outputs: []outputInfo{
29811                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29812                         },
29813                 },
29814         },
29815         {
29816                 name:    "ANDCCconst",
29817                 auxType: auxInt64,
29818                 argLen:  1,
29819                 asm:     ppc64.AANDCC,
29820                 reg: regInfo{
29821                         inputs: []inputInfo{
29822                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29823                         },
29824                         outputs: []outputInfo{
29825                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29826                         },
29827                 },
29828         },
29829         {
29830                 name:   "MOVBreg",
29831                 argLen: 1,
29832                 asm:    ppc64.AMOVB,
29833                 reg: regInfo{
29834                         inputs: []inputInfo{
29835                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29836                         },
29837                         outputs: []outputInfo{
29838                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29839                         },
29840                 },
29841         },
29842         {
29843                 name:   "MOVBZreg",
29844                 argLen: 1,
29845                 asm:    ppc64.AMOVBZ,
29846                 reg: regInfo{
29847                         inputs: []inputInfo{
29848                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29849                         },
29850                         outputs: []outputInfo{
29851                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29852                         },
29853                 },
29854         },
29855         {
29856                 name:   "MOVHreg",
29857                 argLen: 1,
29858                 asm:    ppc64.AMOVH,
29859                 reg: regInfo{
29860                         inputs: []inputInfo{
29861                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29862                         },
29863                         outputs: []outputInfo{
29864                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29865                         },
29866                 },
29867         },
29868         {
29869                 name:   "MOVHZreg",
29870                 argLen: 1,
29871                 asm:    ppc64.AMOVHZ,
29872                 reg: regInfo{
29873                         inputs: []inputInfo{
29874                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29875                         },
29876                         outputs: []outputInfo{
29877                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29878                         },
29879                 },
29880         },
29881         {
29882                 name:   "MOVWreg",
29883                 argLen: 1,
29884                 asm:    ppc64.AMOVW,
29885                 reg: regInfo{
29886                         inputs: []inputInfo{
29887                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29888                         },
29889                         outputs: []outputInfo{
29890                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29891                         },
29892                 },
29893         },
29894         {
29895                 name:   "MOVWZreg",
29896                 argLen: 1,
29897                 asm:    ppc64.AMOVWZ,
29898                 reg: regInfo{
29899                         inputs: []inputInfo{
29900                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29901                         },
29902                         outputs: []outputInfo{
29903                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29904                         },
29905                 },
29906         },
29907         {
29908                 name:           "MOVBZload",
29909                 auxType:        auxSymOff,
29910                 argLen:         2,
29911                 faultOnNilArg0: true,
29912                 symEffect:      SymRead,
29913                 asm:            ppc64.AMOVBZ,
29914                 reg: regInfo{
29915                         inputs: []inputInfo{
29916                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29917                         },
29918                         outputs: []outputInfo{
29919                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29920                         },
29921                 },
29922         },
29923         {
29924                 name:           "MOVHload",
29925                 auxType:        auxSymOff,
29926                 argLen:         2,
29927                 faultOnNilArg0: true,
29928                 symEffect:      SymRead,
29929                 asm:            ppc64.AMOVH,
29930                 reg: regInfo{
29931                         inputs: []inputInfo{
29932                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29933                         },
29934                         outputs: []outputInfo{
29935                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29936                         },
29937                 },
29938         },
29939         {
29940                 name:           "MOVHZload",
29941                 auxType:        auxSymOff,
29942                 argLen:         2,
29943                 faultOnNilArg0: true,
29944                 symEffect:      SymRead,
29945                 asm:            ppc64.AMOVHZ,
29946                 reg: regInfo{
29947                         inputs: []inputInfo{
29948                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29949                         },
29950                         outputs: []outputInfo{
29951                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29952                         },
29953                 },
29954         },
29955         {
29956                 name:           "MOVWload",
29957                 auxType:        auxSymOff,
29958                 argLen:         2,
29959                 faultOnNilArg0: true,
29960                 symEffect:      SymRead,
29961                 asm:            ppc64.AMOVW,
29962                 reg: regInfo{
29963                         inputs: []inputInfo{
29964                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29965                         },
29966                         outputs: []outputInfo{
29967                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29968                         },
29969                 },
29970         },
29971         {
29972                 name:           "MOVWZload",
29973                 auxType:        auxSymOff,
29974                 argLen:         2,
29975                 faultOnNilArg0: true,
29976                 symEffect:      SymRead,
29977                 asm:            ppc64.AMOVWZ,
29978                 reg: regInfo{
29979                         inputs: []inputInfo{
29980                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29981                         },
29982                         outputs: []outputInfo{
29983                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29984                         },
29985                 },
29986         },
29987         {
29988                 name:           "MOVDload",
29989                 auxType:        auxSymOff,
29990                 argLen:         2,
29991                 faultOnNilArg0: true,
29992                 symEffect:      SymRead,
29993                 asm:            ppc64.AMOVD,
29994                 reg: regInfo{
29995                         inputs: []inputInfo{
29996                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
29997                         },
29998                         outputs: []outputInfo{
29999                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30000                         },
30001                 },
30002         },
30003         {
30004                 name:           "MOVDBRload",
30005                 argLen:         2,
30006                 faultOnNilArg0: true,
30007                 asm:            ppc64.AMOVDBR,
30008                 reg: regInfo{
30009                         inputs: []inputInfo{
30010                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30011                         },
30012                         outputs: []outputInfo{
30013                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30014                         },
30015                 },
30016         },
30017         {
30018                 name:           "MOVWBRload",
30019                 argLen:         2,
30020                 faultOnNilArg0: true,
30021                 asm:            ppc64.AMOVWBR,
30022                 reg: regInfo{
30023                         inputs: []inputInfo{
30024                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30025                         },
30026                         outputs: []outputInfo{
30027                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30028                         },
30029                 },
30030         },
30031         {
30032                 name:           "MOVHBRload",
30033                 argLen:         2,
30034                 faultOnNilArg0: true,
30035                 asm:            ppc64.AMOVHBR,
30036                 reg: regInfo{
30037                         inputs: []inputInfo{
30038                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30039                         },
30040                         outputs: []outputInfo{
30041                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30042                         },
30043                 },
30044         },
30045         {
30046                 name:   "MOVBZloadidx",
30047                 argLen: 3,
30048                 asm:    ppc64.AMOVBZ,
30049                 reg: regInfo{
30050                         inputs: []inputInfo{
30051                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30052                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30053                         },
30054                         outputs: []outputInfo{
30055                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30056                         },
30057                 },
30058         },
30059         {
30060                 name:   "MOVHloadidx",
30061                 argLen: 3,
30062                 asm:    ppc64.AMOVH,
30063                 reg: regInfo{
30064                         inputs: []inputInfo{
30065                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30066                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30067                         },
30068                         outputs: []outputInfo{
30069                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30070                         },
30071                 },
30072         },
30073         {
30074                 name:   "MOVHZloadidx",
30075                 argLen: 3,
30076                 asm:    ppc64.AMOVHZ,
30077                 reg: regInfo{
30078                         inputs: []inputInfo{
30079                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30080                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30081                         },
30082                         outputs: []outputInfo{
30083                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30084                         },
30085                 },
30086         },
30087         {
30088                 name:   "MOVWloadidx",
30089                 argLen: 3,
30090                 asm:    ppc64.AMOVW,
30091                 reg: regInfo{
30092                         inputs: []inputInfo{
30093                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30094                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30095                         },
30096                         outputs: []outputInfo{
30097                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30098                         },
30099                 },
30100         },
30101         {
30102                 name:   "MOVWZloadidx",
30103                 argLen: 3,
30104                 asm:    ppc64.AMOVWZ,
30105                 reg: regInfo{
30106                         inputs: []inputInfo{
30107                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30108                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30109                         },
30110                         outputs: []outputInfo{
30111                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30112                         },
30113                 },
30114         },
30115         {
30116                 name:   "MOVDloadidx",
30117                 argLen: 3,
30118                 asm:    ppc64.AMOVD,
30119                 reg: regInfo{
30120                         inputs: []inputInfo{
30121                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30122                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30123                         },
30124                         outputs: []outputInfo{
30125                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30126                         },
30127                 },
30128         },
30129         {
30130                 name:   "MOVHBRloadidx",
30131                 argLen: 3,
30132                 asm:    ppc64.AMOVHBR,
30133                 reg: regInfo{
30134                         inputs: []inputInfo{
30135                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30136                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30137                         },
30138                         outputs: []outputInfo{
30139                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30140                         },
30141                 },
30142         },
30143         {
30144                 name:   "MOVWBRloadidx",
30145                 argLen: 3,
30146                 asm:    ppc64.AMOVWBR,
30147                 reg: regInfo{
30148                         inputs: []inputInfo{
30149                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30150                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30151                         },
30152                         outputs: []outputInfo{
30153                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30154                         },
30155                 },
30156         },
30157         {
30158                 name:   "MOVDBRloadidx",
30159                 argLen: 3,
30160                 asm:    ppc64.AMOVDBR,
30161                 reg: regInfo{
30162                         inputs: []inputInfo{
30163                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30164                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30165                         },
30166                         outputs: []outputInfo{
30167                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30168                         },
30169                 },
30170         },
30171         {
30172                 name:   "FMOVDloadidx",
30173                 argLen: 3,
30174                 asm:    ppc64.AFMOVD,
30175                 reg: regInfo{
30176                         inputs: []inputInfo{
30177                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30178                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30179                         },
30180                         outputs: []outputInfo{
30181                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30182                         },
30183                 },
30184         },
30185         {
30186                 name:   "FMOVSloadidx",
30187                 argLen: 3,
30188                 asm:    ppc64.AFMOVS,
30189                 reg: regInfo{
30190                         inputs: []inputInfo{
30191                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30192                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30193                         },
30194                         outputs: []outputInfo{
30195                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30196                         },
30197                 },
30198         },
30199         {
30200                 name:           "DCBT",
30201                 auxType:        auxInt64,
30202                 argLen:         2,
30203                 hasSideEffects: true,
30204                 asm:            ppc64.ADCBT,
30205                 reg: regInfo{
30206                         inputs: []inputInfo{
30207                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30208                         },
30209                 },
30210         },
30211         {
30212                 name:           "MOVDBRstore",
30213                 argLen:         3,
30214                 faultOnNilArg0: true,
30215                 asm:            ppc64.AMOVDBR,
30216                 reg: regInfo{
30217                         inputs: []inputInfo{
30218                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30219                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30220                         },
30221                 },
30222         },
30223         {
30224                 name:           "MOVWBRstore",
30225                 argLen:         3,
30226                 faultOnNilArg0: true,
30227                 asm:            ppc64.AMOVWBR,
30228                 reg: regInfo{
30229                         inputs: []inputInfo{
30230                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30231                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30232                         },
30233                 },
30234         },
30235         {
30236                 name:           "MOVHBRstore",
30237                 argLen:         3,
30238                 faultOnNilArg0: true,
30239                 asm:            ppc64.AMOVHBR,
30240                 reg: regInfo{
30241                         inputs: []inputInfo{
30242                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30243                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30244                         },
30245                 },
30246         },
30247         {
30248                 name:           "FMOVDload",
30249                 auxType:        auxSymOff,
30250                 argLen:         2,
30251                 faultOnNilArg0: true,
30252                 symEffect:      SymRead,
30253                 asm:            ppc64.AFMOVD,
30254                 reg: regInfo{
30255                         inputs: []inputInfo{
30256                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30257                         },
30258                         outputs: []outputInfo{
30259                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30260                         },
30261                 },
30262         },
30263         {
30264                 name:           "FMOVSload",
30265                 auxType:        auxSymOff,
30266                 argLen:         2,
30267                 faultOnNilArg0: true,
30268                 symEffect:      SymRead,
30269                 asm:            ppc64.AFMOVS,
30270                 reg: regInfo{
30271                         inputs: []inputInfo{
30272                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30273                         },
30274                         outputs: []outputInfo{
30275                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30276                         },
30277                 },
30278         },
30279         {
30280                 name:           "MOVBstore",
30281                 auxType:        auxSymOff,
30282                 argLen:         3,
30283                 faultOnNilArg0: true,
30284                 symEffect:      SymWrite,
30285                 asm:            ppc64.AMOVB,
30286                 reg: regInfo{
30287                         inputs: []inputInfo{
30288                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30289                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30290                         },
30291                 },
30292         },
30293         {
30294                 name:           "MOVHstore",
30295                 auxType:        auxSymOff,
30296                 argLen:         3,
30297                 faultOnNilArg0: true,
30298                 symEffect:      SymWrite,
30299                 asm:            ppc64.AMOVH,
30300                 reg: regInfo{
30301                         inputs: []inputInfo{
30302                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30303                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30304                         },
30305                 },
30306         },
30307         {
30308                 name:           "MOVWstore",
30309                 auxType:        auxSymOff,
30310                 argLen:         3,
30311                 faultOnNilArg0: true,
30312                 symEffect:      SymWrite,
30313                 asm:            ppc64.AMOVW,
30314                 reg: regInfo{
30315                         inputs: []inputInfo{
30316                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30317                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30318                         },
30319                 },
30320         },
30321         {
30322                 name:           "MOVDstore",
30323                 auxType:        auxSymOff,
30324                 argLen:         3,
30325                 faultOnNilArg0: true,
30326                 symEffect:      SymWrite,
30327                 asm:            ppc64.AMOVD,
30328                 reg: regInfo{
30329                         inputs: []inputInfo{
30330                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30331                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30332                         },
30333                 },
30334         },
30335         {
30336                 name:           "FMOVDstore",
30337                 auxType:        auxSymOff,
30338                 argLen:         3,
30339                 faultOnNilArg0: true,
30340                 symEffect:      SymWrite,
30341                 asm:            ppc64.AFMOVD,
30342                 reg: regInfo{
30343                         inputs: []inputInfo{
30344                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30345                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30346                         },
30347                 },
30348         },
30349         {
30350                 name:           "FMOVSstore",
30351                 auxType:        auxSymOff,
30352                 argLen:         3,
30353                 faultOnNilArg0: true,
30354                 symEffect:      SymWrite,
30355                 asm:            ppc64.AFMOVS,
30356                 reg: regInfo{
30357                         inputs: []inputInfo{
30358                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30359                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30360                         },
30361                 },
30362         },
30363         {
30364                 name:   "MOVBstoreidx",
30365                 argLen: 4,
30366                 asm:    ppc64.AMOVB,
30367                 reg: regInfo{
30368                         inputs: []inputInfo{
30369                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30370                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30371                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30372                         },
30373                 },
30374         },
30375         {
30376                 name:   "MOVHstoreidx",
30377                 argLen: 4,
30378                 asm:    ppc64.AMOVH,
30379                 reg: regInfo{
30380                         inputs: []inputInfo{
30381                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30382                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30383                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30384                         },
30385                 },
30386         },
30387         {
30388                 name:   "MOVWstoreidx",
30389                 argLen: 4,
30390                 asm:    ppc64.AMOVW,
30391                 reg: regInfo{
30392                         inputs: []inputInfo{
30393                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30394                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30395                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30396                         },
30397                 },
30398         },
30399         {
30400                 name:   "MOVDstoreidx",
30401                 argLen: 4,
30402                 asm:    ppc64.AMOVD,
30403                 reg: regInfo{
30404                         inputs: []inputInfo{
30405                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30406                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30407                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30408                         },
30409                 },
30410         },
30411         {
30412                 name:   "FMOVDstoreidx",
30413                 argLen: 4,
30414                 asm:    ppc64.AFMOVD,
30415                 reg: regInfo{
30416                         inputs: []inputInfo{
30417                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30418                                 {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30419                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30420                         },
30421                 },
30422         },
30423         {
30424                 name:   "FMOVSstoreidx",
30425                 argLen: 4,
30426                 asm:    ppc64.AFMOVS,
30427                 reg: regInfo{
30428                         inputs: []inputInfo{
30429                                 {0, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30430                                 {1, 1073733630},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30431                                 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30432                         },
30433                 },
30434         },
30435         {
30436                 name:   "MOVHBRstoreidx",
30437                 argLen: 4,
30438                 asm:    ppc64.AMOVHBR,
30439                 reg: regInfo{
30440                         inputs: []inputInfo{
30441                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30442                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30443                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30444                         },
30445                 },
30446         },
30447         {
30448                 name:   "MOVWBRstoreidx",
30449                 argLen: 4,
30450                 asm:    ppc64.AMOVWBR,
30451                 reg: regInfo{
30452                         inputs: []inputInfo{
30453                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30454                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30455                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30456                         },
30457                 },
30458         },
30459         {
30460                 name:   "MOVDBRstoreidx",
30461                 argLen: 4,
30462                 asm:    ppc64.AMOVDBR,
30463                 reg: regInfo{
30464                         inputs: []inputInfo{
30465                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30466                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30467                                 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30468                         },
30469                 },
30470         },
30471         {
30472                 name:           "MOVBstorezero",
30473                 auxType:        auxSymOff,
30474                 argLen:         2,
30475                 faultOnNilArg0: true,
30476                 symEffect:      SymWrite,
30477                 asm:            ppc64.AMOVB,
30478                 reg: regInfo{
30479                         inputs: []inputInfo{
30480                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30481                         },
30482                 },
30483         },
30484         {
30485                 name:           "MOVHstorezero",
30486                 auxType:        auxSymOff,
30487                 argLen:         2,
30488                 faultOnNilArg0: true,
30489                 symEffect:      SymWrite,
30490                 asm:            ppc64.AMOVH,
30491                 reg: regInfo{
30492                         inputs: []inputInfo{
30493                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30494                         },
30495                 },
30496         },
30497         {
30498                 name:           "MOVWstorezero",
30499                 auxType:        auxSymOff,
30500                 argLen:         2,
30501                 faultOnNilArg0: true,
30502                 symEffect:      SymWrite,
30503                 asm:            ppc64.AMOVW,
30504                 reg: regInfo{
30505                         inputs: []inputInfo{
30506                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30507                         },
30508                 },
30509         },
30510         {
30511                 name:           "MOVDstorezero",
30512                 auxType:        auxSymOff,
30513                 argLen:         2,
30514                 faultOnNilArg0: true,
30515                 symEffect:      SymWrite,
30516                 asm:            ppc64.AMOVD,
30517                 reg: regInfo{
30518                         inputs: []inputInfo{
30519                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30520                         },
30521                 },
30522         },
30523         {
30524                 name:              "MOVDaddr",
30525                 auxType:           auxSymOff,
30526                 argLen:            1,
30527                 rematerializeable: true,
30528                 symEffect:         SymAddr,
30529                 asm:               ppc64.AMOVD,
30530                 reg: regInfo{
30531                         inputs: []inputInfo{
30532                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30533                         },
30534                         outputs: []outputInfo{
30535                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30536                         },
30537                 },
30538         },
30539         {
30540                 name:              "MOVDconst",
30541                 auxType:           auxInt64,
30542                 argLen:            0,
30543                 rematerializeable: true,
30544                 asm:               ppc64.AMOVD,
30545                 reg: regInfo{
30546                         outputs: []outputInfo{
30547                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30548                         },
30549                 },
30550         },
30551         {
30552                 name:              "FMOVDconst",
30553                 auxType:           auxFloat64,
30554                 argLen:            0,
30555                 rematerializeable: true,
30556                 asm:               ppc64.AFMOVD,
30557                 reg: regInfo{
30558                         outputs: []outputInfo{
30559                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30560                         },
30561                 },
30562         },
30563         {
30564                 name:              "FMOVSconst",
30565                 auxType:           auxFloat32,
30566                 argLen:            0,
30567                 rematerializeable: true,
30568                 asm:               ppc64.AFMOVS,
30569                 reg: regInfo{
30570                         outputs: []outputInfo{
30571                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30572                         },
30573                 },
30574         },
30575         {
30576                 name:   "FCMPU",
30577                 argLen: 2,
30578                 asm:    ppc64.AFCMPU,
30579                 reg: regInfo{
30580                         inputs: []inputInfo{
30581                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30582                                 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30583                         },
30584                 },
30585         },
30586         {
30587                 name:   "CMP",
30588                 argLen: 2,
30589                 asm:    ppc64.ACMP,
30590                 reg: regInfo{
30591                         inputs: []inputInfo{
30592                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30593                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30594                         },
30595                 },
30596         },
30597         {
30598                 name:   "CMPU",
30599                 argLen: 2,
30600                 asm:    ppc64.ACMPU,
30601                 reg: regInfo{
30602                         inputs: []inputInfo{
30603                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30604                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30605                         },
30606                 },
30607         },
30608         {
30609                 name:   "CMPW",
30610                 argLen: 2,
30611                 asm:    ppc64.ACMPW,
30612                 reg: regInfo{
30613                         inputs: []inputInfo{
30614                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30615                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30616                         },
30617                 },
30618         },
30619         {
30620                 name:   "CMPWU",
30621                 argLen: 2,
30622                 asm:    ppc64.ACMPWU,
30623                 reg: regInfo{
30624                         inputs: []inputInfo{
30625                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30626                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30627                         },
30628                 },
30629         },
30630         {
30631                 name:    "CMPconst",
30632                 auxType: auxInt64,
30633                 argLen:  1,
30634                 asm:     ppc64.ACMP,
30635                 reg: regInfo{
30636                         inputs: []inputInfo{
30637                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30638                         },
30639                 },
30640         },
30641         {
30642                 name:    "CMPUconst",
30643                 auxType: auxInt64,
30644                 argLen:  1,
30645                 asm:     ppc64.ACMPU,
30646                 reg: regInfo{
30647                         inputs: []inputInfo{
30648                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30649                         },
30650                 },
30651         },
30652         {
30653                 name:    "CMPWconst",
30654                 auxType: auxInt32,
30655                 argLen:  1,
30656                 asm:     ppc64.ACMPW,
30657                 reg: regInfo{
30658                         inputs: []inputInfo{
30659                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30660                         },
30661                 },
30662         },
30663         {
30664                 name:    "CMPWUconst",
30665                 auxType: auxInt32,
30666                 argLen:  1,
30667                 asm:     ppc64.ACMPWU,
30668                 reg: regInfo{
30669                         inputs: []inputInfo{
30670                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30671                         },
30672                 },
30673         },
30674         {
30675                 name:    "ISEL",
30676                 auxType: auxInt32,
30677                 argLen:  3,
30678                 asm:     ppc64.AISEL,
30679                 reg: regInfo{
30680                         inputs: []inputInfo{
30681                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30682                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30683                         },
30684                         outputs: []outputInfo{
30685                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30686                         },
30687                 },
30688         },
30689         {
30690                 name:    "ISELZ",
30691                 auxType: auxInt32,
30692                 argLen:  2,
30693                 asm:     ppc64.AISEL,
30694                 reg: regInfo{
30695                         inputs: []inputInfo{
30696                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30697                         },
30698                         outputs: []outputInfo{
30699                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30700                         },
30701                 },
30702         },
30703         {
30704                 name:    "SETBC",
30705                 auxType: auxInt32,
30706                 argLen:  1,
30707                 asm:     ppc64.ASETBC,
30708                 reg: regInfo{
30709                         outputs: []outputInfo{
30710                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30711                         },
30712                 },
30713         },
30714         {
30715                 name:    "SETBCR",
30716                 auxType: auxInt32,
30717                 argLen:  1,
30718                 asm:     ppc64.ASETBCR,
30719                 reg: regInfo{
30720                         outputs: []outputInfo{
30721                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30722                         },
30723                 },
30724         },
30725         {
30726                 name:   "Equal",
30727                 argLen: 1,
30728                 reg: regInfo{
30729                         outputs: []outputInfo{
30730                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30731                         },
30732                 },
30733         },
30734         {
30735                 name:   "NotEqual",
30736                 argLen: 1,
30737                 reg: regInfo{
30738                         outputs: []outputInfo{
30739                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30740                         },
30741                 },
30742         },
30743         {
30744                 name:   "LessThan",
30745                 argLen: 1,
30746                 reg: regInfo{
30747                         outputs: []outputInfo{
30748                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30749                         },
30750                 },
30751         },
30752         {
30753                 name:   "FLessThan",
30754                 argLen: 1,
30755                 reg: regInfo{
30756                         outputs: []outputInfo{
30757                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30758                         },
30759                 },
30760         },
30761         {
30762                 name:   "LessEqual",
30763                 argLen: 1,
30764                 reg: regInfo{
30765                         outputs: []outputInfo{
30766                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30767                         },
30768                 },
30769         },
30770         {
30771                 name:   "FLessEqual",
30772                 argLen: 1,
30773                 reg: regInfo{
30774                         outputs: []outputInfo{
30775                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30776                         },
30777                 },
30778         },
30779         {
30780                 name:   "GreaterThan",
30781                 argLen: 1,
30782                 reg: regInfo{
30783                         outputs: []outputInfo{
30784                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30785                         },
30786                 },
30787         },
30788         {
30789                 name:   "FGreaterThan",
30790                 argLen: 1,
30791                 reg: regInfo{
30792                         outputs: []outputInfo{
30793                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30794                         },
30795                 },
30796         },
30797         {
30798                 name:   "GreaterEqual",
30799                 argLen: 1,
30800                 reg: regInfo{
30801                         outputs: []outputInfo{
30802                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30803                         },
30804                 },
30805         },
30806         {
30807                 name:   "FGreaterEqual",
30808                 argLen: 1,
30809                 reg: regInfo{
30810                         outputs: []outputInfo{
30811                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30812                         },
30813                 },
30814         },
30815         {
30816                 name:      "LoweredGetClosurePtr",
30817                 argLen:    0,
30818                 zeroWidth: true,
30819                 reg: regInfo{
30820                         outputs: []outputInfo{
30821                                 {0, 2048}, // R11
30822                         },
30823                 },
30824         },
30825         {
30826                 name:              "LoweredGetCallerSP",
30827                 argLen:            1,
30828                 rematerializeable: true,
30829                 reg: regInfo{
30830                         outputs: []outputInfo{
30831                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30832                         },
30833                 },
30834         },
30835         {
30836                 name:              "LoweredGetCallerPC",
30837                 argLen:            0,
30838                 rematerializeable: true,
30839                 reg: regInfo{
30840                         outputs: []outputInfo{
30841                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30842                         },
30843                 },
30844         },
30845         {
30846                 name:           "LoweredNilCheck",
30847                 argLen:         2,
30848                 clobberFlags:   true,
30849                 nilCheck:       true,
30850                 faultOnNilArg0: true,
30851                 reg: regInfo{
30852                         inputs: []inputInfo{
30853                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30854                         },
30855                         clobbers: 2147483648, // R31
30856                 },
30857         },
30858         {
30859                 name:         "LoweredRound32F",
30860                 argLen:       1,
30861                 resultInArg0: true,
30862                 zeroWidth:    true,
30863                 reg: regInfo{
30864                         inputs: []inputInfo{
30865                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30866                         },
30867                         outputs: []outputInfo{
30868                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30869                         },
30870                 },
30871         },
30872         {
30873                 name:         "LoweredRound64F",
30874                 argLen:       1,
30875                 resultInArg0: true,
30876                 zeroWidth:    true,
30877                 reg: regInfo{
30878                         inputs: []inputInfo{
30879                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30880                         },
30881                         outputs: []outputInfo{
30882                                 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
30883                         },
30884                 },
30885         },
30886         {
30887                 name:         "CALLstatic",
30888                 auxType:      auxCallOff,
30889                 argLen:       -1,
30890                 clobberFlags: true,
30891                 call:         true,
30892                 reg: regInfo{
30893                         clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
30894                 },
30895         },
30896         {
30897                 name:         "CALLtail",
30898                 auxType:      auxCallOff,
30899                 argLen:       -1,
30900                 clobberFlags: true,
30901                 call:         true,
30902                 tailCall:     true,
30903                 reg: regInfo{
30904                         clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
30905                 },
30906         },
30907         {
30908                 name:         "CALLclosure",
30909                 auxType:      auxCallOff,
30910                 argLen:       -1,
30911                 clobberFlags: true,
30912                 call:         true,
30913                 reg: regInfo{
30914                         inputs: []inputInfo{
30915                                 {0, 4096}, // R12
30916                                 {1, 2048}, // R11
30917                         },
30918                         clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
30919                 },
30920         },
30921         {
30922                 name:         "CALLinter",
30923                 auxType:      auxCallOff,
30924                 argLen:       -1,
30925                 clobberFlags: true,
30926                 call:         true,
30927                 reg: regInfo{
30928                         inputs: []inputInfo{
30929                                 {0, 4096}, // R12
30930                         },
30931                         clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
30932                 },
30933         },
30934         {
30935                 name:           "LoweredZero",
30936                 auxType:        auxInt64,
30937                 argLen:         2,
30938                 clobberFlags:   true,
30939                 faultOnNilArg0: true,
30940                 unsafePoint:    true,
30941                 reg: regInfo{
30942                         inputs: []inputInfo{
30943                                 {0, 1048576}, // R20
30944                         },
30945                         clobbers: 1048576, // R20
30946                 },
30947         },
30948         {
30949                 name:           "LoweredZeroShort",
30950                 auxType:        auxInt64,
30951                 argLen:         2,
30952                 faultOnNilArg0: true,
30953                 unsafePoint:    true,
30954                 reg: regInfo{
30955                         inputs: []inputInfo{
30956                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30957                         },
30958                 },
30959         },
30960         {
30961                 name:           "LoweredQuadZeroShort",
30962                 auxType:        auxInt64,
30963                 argLen:         2,
30964                 faultOnNilArg0: true,
30965                 unsafePoint:    true,
30966                 reg: regInfo{
30967                         inputs: []inputInfo{
30968                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
30969                         },
30970                 },
30971         },
30972         {
30973                 name:           "LoweredQuadZero",
30974                 auxType:        auxInt64,
30975                 argLen:         2,
30976                 clobberFlags:   true,
30977                 faultOnNilArg0: true,
30978                 unsafePoint:    true,
30979                 reg: regInfo{
30980                         inputs: []inputInfo{
30981                                 {0, 1048576}, // R20
30982                         },
30983                         clobbers: 1048576, // R20
30984                 },
30985         },
30986         {
30987                 name:           "LoweredMove",
30988                 auxType:        auxInt64,
30989                 argLen:         3,
30990                 clobberFlags:   true,
30991                 faultOnNilArg0: true,
30992                 faultOnNilArg1: true,
30993                 unsafePoint:    true,
30994                 reg: regInfo{
30995                         inputs: []inputInfo{
30996                                 {0, 1048576}, // R20
30997                                 {1, 2097152}, // R21
30998                         },
30999                         clobbers: 3145728, // R20 R21
31000                 },
31001         },
31002         {
31003                 name:           "LoweredMoveShort",
31004                 auxType:        auxInt64,
31005                 argLen:         3,
31006                 faultOnNilArg0: true,
31007                 faultOnNilArg1: true,
31008                 unsafePoint:    true,
31009                 reg: regInfo{
31010                         inputs: []inputInfo{
31011                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31012                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31013                         },
31014                 },
31015         },
31016         {
31017                 name:           "LoweredQuadMove",
31018                 auxType:        auxInt64,
31019                 argLen:         3,
31020                 clobberFlags:   true,
31021                 faultOnNilArg0: true,
31022                 faultOnNilArg1: true,
31023                 unsafePoint:    true,
31024                 reg: regInfo{
31025                         inputs: []inputInfo{
31026                                 {0, 1048576}, // R20
31027                                 {1, 2097152}, // R21
31028                         },
31029                         clobbers: 3145728, // R20 R21
31030                 },
31031         },
31032         {
31033                 name:           "LoweredQuadMoveShort",
31034                 auxType:        auxInt64,
31035                 argLen:         3,
31036                 faultOnNilArg0: true,
31037                 faultOnNilArg1: true,
31038                 unsafePoint:    true,
31039                 reg: regInfo{
31040                         inputs: []inputInfo{
31041                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31042                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31043                         },
31044                 },
31045         },
31046         {
31047                 name:           "LoweredAtomicStore8",
31048                 auxType:        auxInt64,
31049                 argLen:         3,
31050                 faultOnNilArg0: true,
31051                 hasSideEffects: true,
31052                 reg: regInfo{
31053                         inputs: []inputInfo{
31054                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31055                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31056                         },
31057                 },
31058         },
31059         {
31060                 name:           "LoweredAtomicStore32",
31061                 auxType:        auxInt64,
31062                 argLen:         3,
31063                 faultOnNilArg0: true,
31064                 hasSideEffects: true,
31065                 reg: regInfo{
31066                         inputs: []inputInfo{
31067                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31068                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31069                         },
31070                 },
31071         },
31072         {
31073                 name:           "LoweredAtomicStore64",
31074                 auxType:        auxInt64,
31075                 argLen:         3,
31076                 faultOnNilArg0: true,
31077                 hasSideEffects: true,
31078                 reg: regInfo{
31079                         inputs: []inputInfo{
31080                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31081                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31082                         },
31083                 },
31084         },
31085         {
31086                 name:           "LoweredAtomicLoad8",
31087                 auxType:        auxInt64,
31088                 argLen:         2,
31089                 clobberFlags:   true,
31090                 faultOnNilArg0: true,
31091                 reg: regInfo{
31092                         inputs: []inputInfo{
31093                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31094                         },
31095                         outputs: []outputInfo{
31096                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31097                         },
31098                 },
31099         },
31100         {
31101                 name:           "LoweredAtomicLoad32",
31102                 auxType:        auxInt64,
31103                 argLen:         2,
31104                 clobberFlags:   true,
31105                 faultOnNilArg0: true,
31106                 reg: regInfo{
31107                         inputs: []inputInfo{
31108                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31109                         },
31110                         outputs: []outputInfo{
31111                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31112                         },
31113                 },
31114         },
31115         {
31116                 name:           "LoweredAtomicLoad64",
31117                 auxType:        auxInt64,
31118                 argLen:         2,
31119                 clobberFlags:   true,
31120                 faultOnNilArg0: true,
31121                 reg: regInfo{
31122                         inputs: []inputInfo{
31123                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31124                         },
31125                         outputs: []outputInfo{
31126                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31127                         },
31128                 },
31129         },
31130         {
31131                 name:           "LoweredAtomicLoadPtr",
31132                 auxType:        auxInt64,
31133                 argLen:         2,
31134                 clobberFlags:   true,
31135                 faultOnNilArg0: true,
31136                 reg: regInfo{
31137                         inputs: []inputInfo{
31138                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31139                         },
31140                         outputs: []outputInfo{
31141                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31142                         },
31143                 },
31144         },
31145         {
31146                 name:            "LoweredAtomicAdd32",
31147                 argLen:          3,
31148                 resultNotInArgs: true,
31149                 clobberFlags:    true,
31150                 faultOnNilArg0:  true,
31151                 hasSideEffects:  true,
31152                 reg: regInfo{
31153                         inputs: []inputInfo{
31154                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31155                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31156                         },
31157                         outputs: []outputInfo{
31158                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31159                         },
31160                 },
31161         },
31162         {
31163                 name:            "LoweredAtomicAdd64",
31164                 argLen:          3,
31165                 resultNotInArgs: true,
31166                 clobberFlags:    true,
31167                 faultOnNilArg0:  true,
31168                 hasSideEffects:  true,
31169                 reg: regInfo{
31170                         inputs: []inputInfo{
31171                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31172                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31173                         },
31174                         outputs: []outputInfo{
31175                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31176                         },
31177                 },
31178         },
31179         {
31180                 name:            "LoweredAtomicExchange32",
31181                 argLen:          3,
31182                 resultNotInArgs: true,
31183                 clobberFlags:    true,
31184                 faultOnNilArg0:  true,
31185                 hasSideEffects:  true,
31186                 reg: regInfo{
31187                         inputs: []inputInfo{
31188                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31189                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31190                         },
31191                         outputs: []outputInfo{
31192                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31193                         },
31194                 },
31195         },
31196         {
31197                 name:            "LoweredAtomicExchange64",
31198                 argLen:          3,
31199                 resultNotInArgs: true,
31200                 clobberFlags:    true,
31201                 faultOnNilArg0:  true,
31202                 hasSideEffects:  true,
31203                 reg: regInfo{
31204                         inputs: []inputInfo{
31205                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31206                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31207                         },
31208                         outputs: []outputInfo{
31209                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31210                         },
31211                 },
31212         },
31213         {
31214                 name:            "LoweredAtomicCas64",
31215                 auxType:         auxInt64,
31216                 argLen:          4,
31217                 resultNotInArgs: true,
31218                 clobberFlags:    true,
31219                 faultOnNilArg0:  true,
31220                 hasSideEffects:  true,
31221                 reg: regInfo{
31222                         inputs: []inputInfo{
31223                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31224                                 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31225                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31226                         },
31227                         outputs: []outputInfo{
31228                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31229                         },
31230                 },
31231         },
31232         {
31233                 name:            "LoweredAtomicCas32",
31234                 auxType:         auxInt64,
31235                 argLen:          4,
31236                 resultNotInArgs: true,
31237                 clobberFlags:    true,
31238                 faultOnNilArg0:  true,
31239                 hasSideEffects:  true,
31240                 reg: regInfo{
31241                         inputs: []inputInfo{
31242                                 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31243                                 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31244                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31245                         },
31246                         outputs: []outputInfo{
31247                                 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31248                         },
31249                 },
31250         },
31251         {
31252                 name:           "LoweredAtomicAnd8",
31253                 argLen:         3,
31254                 faultOnNilArg0: true,
31255                 hasSideEffects: true,
31256                 asm:            ppc64.AAND,
31257                 reg: regInfo{
31258                         inputs: []inputInfo{
31259                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31260                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31261                         },
31262                 },
31263         },
31264         {
31265                 name:           "LoweredAtomicAnd32",
31266                 argLen:         3,
31267                 faultOnNilArg0: true,
31268                 hasSideEffects: true,
31269                 asm:            ppc64.AAND,
31270                 reg: regInfo{
31271                         inputs: []inputInfo{
31272                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31273                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31274                         },
31275                 },
31276         },
31277         {
31278                 name:           "LoweredAtomicOr8",
31279                 argLen:         3,
31280                 faultOnNilArg0: true,
31281                 hasSideEffects: true,
31282                 asm:            ppc64.AOR,
31283                 reg: regInfo{
31284                         inputs: []inputInfo{
31285                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31286                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31287                         },
31288                 },
31289         },
31290         {
31291                 name:           "LoweredAtomicOr32",
31292                 argLen:         3,
31293                 faultOnNilArg0: true,
31294                 hasSideEffects: true,
31295                 asm:            ppc64.AOR,
31296                 reg: regInfo{
31297                         inputs: []inputInfo{
31298                                 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31299                                 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
31300                         },
31301                 },
31302         },
31303         {
31304                 name:         "LoweredWB",
31305                 auxType:      auxInt64,
31306                 argLen:       1,
31307                 clobberFlags: true,
31308                 reg: regInfo{
31309                         clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
31310                         outputs: []outputInfo{
31311                                 {0, 536870912}, // R29
31312                         },
31313                 },
31314         },
31315         {
31316                 name:           "LoweredPubBarrier",
31317                 argLen:         1,
31318                 hasSideEffects: true,
31319                 asm:            ppc64.ALWSYNC,
31320                 reg:            regInfo{},
31321         },
31322         {
31323                 name:    "LoweredPanicBoundsA",
31324                 auxType: auxInt64,
31325                 argLen:  3,
31326                 call:    true,
31327                 reg: regInfo{
31328                         inputs: []inputInfo{
31329                                 {0, 32}, // R5
31330                                 {1, 64}, // R6
31331                         },
31332                 },
31333         },
31334         {
31335                 name:    "LoweredPanicBoundsB",
31336                 auxType: auxInt64,
31337                 argLen:  3,
31338                 call:    true,
31339                 reg: regInfo{
31340                         inputs: []inputInfo{
31341                                 {0, 16}, // R4
31342                                 {1, 32}, // R5
31343                         },
31344                 },
31345         },
31346         {
31347                 name:    "LoweredPanicBoundsC",
31348                 auxType: auxInt64,
31349                 argLen:  3,
31350                 call:    true,
31351                 reg: regInfo{
31352                         inputs: []inputInfo{
31353                                 {0, 8},  // R3
31354                                 {1, 16}, // R4
31355                         },
31356                 },
31357         },
31358         {
31359                 name:   "InvertFlags",
31360                 argLen: 1,
31361                 reg:    regInfo{},
31362         },
31363         {
31364                 name:   "FlagEQ",
31365                 argLen: 0,
31366                 reg:    regInfo{},
31367         },
31368         {
31369                 name:   "FlagLT",
31370                 argLen: 0,
31371                 reg:    regInfo{},
31372         },
31373         {
31374                 name:   "FlagGT",
31375                 argLen: 0,
31376                 reg:    regInfo{},
31377         },
31378
31379         {
31380                 name:        "ADD",
31381                 argLen:      2,
31382                 commutative: true,
31383                 asm:         riscv.AADD,
31384                 reg: regInfo{
31385                         inputs: []inputInfo{
31386                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31387                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31388                         },
31389                         outputs: []outputInfo{
31390                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31391                         },
31392                 },
31393         },
31394         {
31395                 name:    "ADDI",
31396                 auxType: auxInt64,
31397                 argLen:  1,
31398                 asm:     riscv.AADDI,
31399                 reg: regInfo{
31400                         inputs: []inputInfo{
31401                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31402                         },
31403                         outputs: []outputInfo{
31404                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31405                         },
31406                 },
31407         },
31408         {
31409                 name:    "ADDIW",
31410                 auxType: auxInt64,
31411                 argLen:  1,
31412                 asm:     riscv.AADDIW,
31413                 reg: regInfo{
31414                         inputs: []inputInfo{
31415                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31416                         },
31417                         outputs: []outputInfo{
31418                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31419                         },
31420                 },
31421         },
31422         {
31423                 name:   "NEG",
31424                 argLen: 1,
31425                 asm:    riscv.ANEG,
31426                 reg: regInfo{
31427                         inputs: []inputInfo{
31428                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31429                         },
31430                         outputs: []outputInfo{
31431                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31432                         },
31433                 },
31434         },
31435         {
31436                 name:   "NEGW",
31437                 argLen: 1,
31438                 asm:    riscv.ANEGW,
31439                 reg: regInfo{
31440                         inputs: []inputInfo{
31441                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31442                         },
31443                         outputs: []outputInfo{
31444                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31445                         },
31446                 },
31447         },
31448         {
31449                 name:   "SUB",
31450                 argLen: 2,
31451                 asm:    riscv.ASUB,
31452                 reg: regInfo{
31453                         inputs: []inputInfo{
31454                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31455                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31456                         },
31457                         outputs: []outputInfo{
31458                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31459                         },
31460                 },
31461         },
31462         {
31463                 name:   "SUBW",
31464                 argLen: 2,
31465                 asm:    riscv.ASUBW,
31466                 reg: regInfo{
31467                         inputs: []inputInfo{
31468                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31469                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31470                         },
31471                         outputs: []outputInfo{
31472                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31473                         },
31474                 },
31475         },
31476         {
31477                 name:        "MUL",
31478                 argLen:      2,
31479                 commutative: true,
31480                 asm:         riscv.AMUL,
31481                 reg: regInfo{
31482                         inputs: []inputInfo{
31483                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31484                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31485                         },
31486                         outputs: []outputInfo{
31487                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31488                         },
31489                 },
31490         },
31491         {
31492                 name:        "MULW",
31493                 argLen:      2,
31494                 commutative: true,
31495                 asm:         riscv.AMULW,
31496                 reg: regInfo{
31497                         inputs: []inputInfo{
31498                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31499                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31500                         },
31501                         outputs: []outputInfo{
31502                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31503                         },
31504                 },
31505         },
31506         {
31507                 name:        "MULH",
31508                 argLen:      2,
31509                 commutative: true,
31510                 asm:         riscv.AMULH,
31511                 reg: regInfo{
31512                         inputs: []inputInfo{
31513                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31514                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31515                         },
31516                         outputs: []outputInfo{
31517                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31518                         },
31519                 },
31520         },
31521         {
31522                 name:        "MULHU",
31523                 argLen:      2,
31524                 commutative: true,
31525                 asm:         riscv.AMULHU,
31526                 reg: regInfo{
31527                         inputs: []inputInfo{
31528                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31529                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31530                         },
31531                         outputs: []outputInfo{
31532                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31533                         },
31534                 },
31535         },
31536         {
31537                 name:            "LoweredMuluhilo",
31538                 argLen:          2,
31539                 resultNotInArgs: true,
31540                 reg: regInfo{
31541                         inputs: []inputInfo{
31542                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31543                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31544                         },
31545                         outputs: []outputInfo{
31546                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31547                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31548                         },
31549                 },
31550         },
31551         {
31552                 name:            "LoweredMuluover",
31553                 argLen:          2,
31554                 resultNotInArgs: true,
31555                 reg: regInfo{
31556                         inputs: []inputInfo{
31557                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31558                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31559                         },
31560                         outputs: []outputInfo{
31561                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31562                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31563                         },
31564                 },
31565         },
31566         {
31567                 name:   "DIV",
31568                 argLen: 2,
31569                 asm:    riscv.ADIV,
31570                 reg: regInfo{
31571                         inputs: []inputInfo{
31572                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31573                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31574                         },
31575                         outputs: []outputInfo{
31576                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31577                         },
31578                 },
31579         },
31580         {
31581                 name:   "DIVU",
31582                 argLen: 2,
31583                 asm:    riscv.ADIVU,
31584                 reg: regInfo{
31585                         inputs: []inputInfo{
31586                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31587                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31588                         },
31589                         outputs: []outputInfo{
31590                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31591                         },
31592                 },
31593         },
31594         {
31595                 name:   "DIVW",
31596                 argLen: 2,
31597                 asm:    riscv.ADIVW,
31598                 reg: regInfo{
31599                         inputs: []inputInfo{
31600                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31601                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31602                         },
31603                         outputs: []outputInfo{
31604                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31605                         },
31606                 },
31607         },
31608         {
31609                 name:   "DIVUW",
31610                 argLen: 2,
31611                 asm:    riscv.ADIVUW,
31612                 reg: regInfo{
31613                         inputs: []inputInfo{
31614                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31615                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31616                         },
31617                         outputs: []outputInfo{
31618                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31619                         },
31620                 },
31621         },
31622         {
31623                 name:   "REM",
31624                 argLen: 2,
31625                 asm:    riscv.AREM,
31626                 reg: regInfo{
31627                         inputs: []inputInfo{
31628                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31629                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31630                         },
31631                         outputs: []outputInfo{
31632                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31633                         },
31634                 },
31635         },
31636         {
31637                 name:   "REMU",
31638                 argLen: 2,
31639                 asm:    riscv.AREMU,
31640                 reg: regInfo{
31641                         inputs: []inputInfo{
31642                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31643                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31644                         },
31645                         outputs: []outputInfo{
31646                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31647                         },
31648                 },
31649         },
31650         {
31651                 name:   "REMW",
31652                 argLen: 2,
31653                 asm:    riscv.AREMW,
31654                 reg: regInfo{
31655                         inputs: []inputInfo{
31656                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31657                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31658                         },
31659                         outputs: []outputInfo{
31660                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31661                         },
31662                 },
31663         },
31664         {
31665                 name:   "REMUW",
31666                 argLen: 2,
31667                 asm:    riscv.AREMUW,
31668                 reg: regInfo{
31669                         inputs: []inputInfo{
31670                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31671                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31672                         },
31673                         outputs: []outputInfo{
31674                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31675                         },
31676                 },
31677         },
31678         {
31679                 name:              "MOVaddr",
31680                 auxType:           auxSymOff,
31681                 argLen:            1,
31682                 rematerializeable: true,
31683                 symEffect:         SymAddr,
31684                 asm:               riscv.AMOV,
31685                 reg: regInfo{
31686                         inputs: []inputInfo{
31687                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31688                         },
31689                         outputs: []outputInfo{
31690                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31691                         },
31692                 },
31693         },
31694         {
31695                 name:              "MOVDconst",
31696                 auxType:           auxInt64,
31697                 argLen:            0,
31698                 rematerializeable: true,
31699                 asm:               riscv.AMOV,
31700                 reg: regInfo{
31701                         outputs: []outputInfo{
31702                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31703                         },
31704                 },
31705         },
31706         {
31707                 name:           "MOVBload",
31708                 auxType:        auxSymOff,
31709                 argLen:         2,
31710                 faultOnNilArg0: true,
31711                 symEffect:      SymRead,
31712                 asm:            riscv.AMOVB,
31713                 reg: regInfo{
31714                         inputs: []inputInfo{
31715                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31716                         },
31717                         outputs: []outputInfo{
31718                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31719                         },
31720                 },
31721         },
31722         {
31723                 name:           "MOVHload",
31724                 auxType:        auxSymOff,
31725                 argLen:         2,
31726                 faultOnNilArg0: true,
31727                 symEffect:      SymRead,
31728                 asm:            riscv.AMOVH,
31729                 reg: regInfo{
31730                         inputs: []inputInfo{
31731                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31732                         },
31733                         outputs: []outputInfo{
31734                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31735                         },
31736                 },
31737         },
31738         {
31739                 name:           "MOVWload",
31740                 auxType:        auxSymOff,
31741                 argLen:         2,
31742                 faultOnNilArg0: true,
31743                 symEffect:      SymRead,
31744                 asm:            riscv.AMOVW,
31745                 reg: regInfo{
31746                         inputs: []inputInfo{
31747                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31748                         },
31749                         outputs: []outputInfo{
31750                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31751                         },
31752                 },
31753         },
31754         {
31755                 name:           "MOVDload",
31756                 auxType:        auxSymOff,
31757                 argLen:         2,
31758                 faultOnNilArg0: true,
31759                 symEffect:      SymRead,
31760                 asm:            riscv.AMOV,
31761                 reg: regInfo{
31762                         inputs: []inputInfo{
31763                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31764                         },
31765                         outputs: []outputInfo{
31766                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31767                         },
31768                 },
31769         },
31770         {
31771                 name:           "MOVBUload",
31772                 auxType:        auxSymOff,
31773                 argLen:         2,
31774                 faultOnNilArg0: true,
31775                 symEffect:      SymRead,
31776                 asm:            riscv.AMOVBU,
31777                 reg: regInfo{
31778                         inputs: []inputInfo{
31779                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31780                         },
31781                         outputs: []outputInfo{
31782                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31783                         },
31784                 },
31785         },
31786         {
31787                 name:           "MOVHUload",
31788                 auxType:        auxSymOff,
31789                 argLen:         2,
31790                 faultOnNilArg0: true,
31791                 symEffect:      SymRead,
31792                 asm:            riscv.AMOVHU,
31793                 reg: regInfo{
31794                         inputs: []inputInfo{
31795                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31796                         },
31797                         outputs: []outputInfo{
31798                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31799                         },
31800                 },
31801         },
31802         {
31803                 name:           "MOVWUload",
31804                 auxType:        auxSymOff,
31805                 argLen:         2,
31806                 faultOnNilArg0: true,
31807                 symEffect:      SymRead,
31808                 asm:            riscv.AMOVWU,
31809                 reg: regInfo{
31810                         inputs: []inputInfo{
31811                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31812                         },
31813                         outputs: []outputInfo{
31814                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31815                         },
31816                 },
31817         },
31818         {
31819                 name:           "MOVBstore",
31820                 auxType:        auxSymOff,
31821                 argLen:         3,
31822                 faultOnNilArg0: true,
31823                 symEffect:      SymWrite,
31824                 asm:            riscv.AMOVB,
31825                 reg: regInfo{
31826                         inputs: []inputInfo{
31827                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31828                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31829                         },
31830                 },
31831         },
31832         {
31833                 name:           "MOVHstore",
31834                 auxType:        auxSymOff,
31835                 argLen:         3,
31836                 faultOnNilArg0: true,
31837                 symEffect:      SymWrite,
31838                 asm:            riscv.AMOVH,
31839                 reg: regInfo{
31840                         inputs: []inputInfo{
31841                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31842                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31843                         },
31844                 },
31845         },
31846         {
31847                 name:           "MOVWstore",
31848                 auxType:        auxSymOff,
31849                 argLen:         3,
31850                 faultOnNilArg0: true,
31851                 symEffect:      SymWrite,
31852                 asm:            riscv.AMOVW,
31853                 reg: regInfo{
31854                         inputs: []inputInfo{
31855                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31856                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31857                         },
31858                 },
31859         },
31860         {
31861                 name:           "MOVDstore",
31862                 auxType:        auxSymOff,
31863                 argLen:         3,
31864                 faultOnNilArg0: true,
31865                 symEffect:      SymWrite,
31866                 asm:            riscv.AMOV,
31867                 reg: regInfo{
31868                         inputs: []inputInfo{
31869                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31870                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31871                         },
31872                 },
31873         },
31874         {
31875                 name:           "MOVBstorezero",
31876                 auxType:        auxSymOff,
31877                 argLen:         2,
31878                 faultOnNilArg0: true,
31879                 symEffect:      SymWrite,
31880                 asm:            riscv.AMOVB,
31881                 reg: regInfo{
31882                         inputs: []inputInfo{
31883                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31884                         },
31885                 },
31886         },
31887         {
31888                 name:           "MOVHstorezero",
31889                 auxType:        auxSymOff,
31890                 argLen:         2,
31891                 faultOnNilArg0: true,
31892                 symEffect:      SymWrite,
31893                 asm:            riscv.AMOVH,
31894                 reg: regInfo{
31895                         inputs: []inputInfo{
31896                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31897                         },
31898                 },
31899         },
31900         {
31901                 name:           "MOVWstorezero",
31902                 auxType:        auxSymOff,
31903                 argLen:         2,
31904                 faultOnNilArg0: true,
31905                 symEffect:      SymWrite,
31906                 asm:            riscv.AMOVW,
31907                 reg: regInfo{
31908                         inputs: []inputInfo{
31909                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31910                         },
31911                 },
31912         },
31913         {
31914                 name:           "MOVDstorezero",
31915                 auxType:        auxSymOff,
31916                 argLen:         2,
31917                 faultOnNilArg0: true,
31918                 symEffect:      SymWrite,
31919                 asm:            riscv.AMOV,
31920                 reg: regInfo{
31921                         inputs: []inputInfo{
31922                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
31923                         },
31924                 },
31925         },
31926         {
31927                 name:   "MOVBreg",
31928                 argLen: 1,
31929                 asm:    riscv.AMOVB,
31930                 reg: regInfo{
31931                         inputs: []inputInfo{
31932                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31933                         },
31934                         outputs: []outputInfo{
31935                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31936                         },
31937                 },
31938         },
31939         {
31940                 name:   "MOVHreg",
31941                 argLen: 1,
31942                 asm:    riscv.AMOVH,
31943                 reg: regInfo{
31944                         inputs: []inputInfo{
31945                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31946                         },
31947                         outputs: []outputInfo{
31948                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31949                         },
31950                 },
31951         },
31952         {
31953                 name:   "MOVWreg",
31954                 argLen: 1,
31955                 asm:    riscv.AMOVW,
31956                 reg: regInfo{
31957                         inputs: []inputInfo{
31958                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31959                         },
31960                         outputs: []outputInfo{
31961                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31962                         },
31963                 },
31964         },
31965         {
31966                 name:   "MOVDreg",
31967                 argLen: 1,
31968                 asm:    riscv.AMOV,
31969                 reg: regInfo{
31970                         inputs: []inputInfo{
31971                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31972                         },
31973                         outputs: []outputInfo{
31974                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31975                         },
31976                 },
31977         },
31978         {
31979                 name:   "MOVBUreg",
31980                 argLen: 1,
31981                 asm:    riscv.AMOVBU,
31982                 reg: regInfo{
31983                         inputs: []inputInfo{
31984                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31985                         },
31986                         outputs: []outputInfo{
31987                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31988                         },
31989                 },
31990         },
31991         {
31992                 name:   "MOVHUreg",
31993                 argLen: 1,
31994                 asm:    riscv.AMOVHU,
31995                 reg: regInfo{
31996                         inputs: []inputInfo{
31997                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
31998                         },
31999                         outputs: []outputInfo{
32000                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32001                         },
32002                 },
32003         },
32004         {
32005                 name:   "MOVWUreg",
32006                 argLen: 1,
32007                 asm:    riscv.AMOVWU,
32008                 reg: regInfo{
32009                         inputs: []inputInfo{
32010                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32011                         },
32012                         outputs: []outputInfo{
32013                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32014                         },
32015                 },
32016         },
32017         {
32018                 name:         "MOVDnop",
32019                 argLen:       1,
32020                 resultInArg0: true,
32021                 reg: regInfo{
32022                         inputs: []inputInfo{
32023                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32024                         },
32025                         outputs: []outputInfo{
32026                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32027                         },
32028                 },
32029         },
32030         {
32031                 name:   "SLL",
32032                 argLen: 2,
32033                 asm:    riscv.ASLL,
32034                 reg: regInfo{
32035                         inputs: []inputInfo{
32036                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32037                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32038                         },
32039                         outputs: []outputInfo{
32040                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32041                         },
32042                 },
32043         },
32044         {
32045                 name:   "SRA",
32046                 argLen: 2,
32047                 asm:    riscv.ASRA,
32048                 reg: regInfo{
32049                         inputs: []inputInfo{
32050                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32051                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32052                         },
32053                         outputs: []outputInfo{
32054                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32055                         },
32056                 },
32057         },
32058         {
32059                 name:   "SRAW",
32060                 argLen: 2,
32061                 asm:    riscv.ASRAW,
32062                 reg: regInfo{
32063                         inputs: []inputInfo{
32064                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32065                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32066                         },
32067                         outputs: []outputInfo{
32068                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32069                         },
32070                 },
32071         },
32072         {
32073                 name:   "SRL",
32074                 argLen: 2,
32075                 asm:    riscv.ASRL,
32076                 reg: regInfo{
32077                         inputs: []inputInfo{
32078                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32079                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32080                         },
32081                         outputs: []outputInfo{
32082                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32083                         },
32084                 },
32085         },
32086         {
32087                 name:   "SRLW",
32088                 argLen: 2,
32089                 asm:    riscv.ASRLW,
32090                 reg: regInfo{
32091                         inputs: []inputInfo{
32092                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32093                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32094                         },
32095                         outputs: []outputInfo{
32096                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32097                         },
32098                 },
32099         },
32100         {
32101                 name:    "SLLI",
32102                 auxType: auxInt64,
32103                 argLen:  1,
32104                 asm:     riscv.ASLLI,
32105                 reg: regInfo{
32106                         inputs: []inputInfo{
32107                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32108                         },
32109                         outputs: []outputInfo{
32110                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32111                         },
32112                 },
32113         },
32114         {
32115                 name:    "SRAI",
32116                 auxType: auxInt64,
32117                 argLen:  1,
32118                 asm:     riscv.ASRAI,
32119                 reg: regInfo{
32120                         inputs: []inputInfo{
32121                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32122                         },
32123                         outputs: []outputInfo{
32124                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32125                         },
32126                 },
32127         },
32128         {
32129                 name:    "SRAIW",
32130                 auxType: auxInt64,
32131                 argLen:  1,
32132                 asm:     riscv.ASRAIW,
32133                 reg: regInfo{
32134                         inputs: []inputInfo{
32135                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32136                         },
32137                         outputs: []outputInfo{
32138                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32139                         },
32140                 },
32141         },
32142         {
32143                 name:    "SRLI",
32144                 auxType: auxInt64,
32145                 argLen:  1,
32146                 asm:     riscv.ASRLI,
32147                 reg: regInfo{
32148                         inputs: []inputInfo{
32149                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32150                         },
32151                         outputs: []outputInfo{
32152                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32153                         },
32154                 },
32155         },
32156         {
32157                 name:    "SRLIW",
32158                 auxType: auxInt64,
32159                 argLen:  1,
32160                 asm:     riscv.ASRLIW,
32161                 reg: regInfo{
32162                         inputs: []inputInfo{
32163                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32164                         },
32165                         outputs: []outputInfo{
32166                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32167                         },
32168                 },
32169         },
32170         {
32171                 name:        "XOR",
32172                 argLen:      2,
32173                 commutative: true,
32174                 asm:         riscv.AXOR,
32175                 reg: regInfo{
32176                         inputs: []inputInfo{
32177                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32178                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32179                         },
32180                         outputs: []outputInfo{
32181                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32182                         },
32183                 },
32184         },
32185         {
32186                 name:    "XORI",
32187                 auxType: auxInt64,
32188                 argLen:  1,
32189                 asm:     riscv.AXORI,
32190                 reg: regInfo{
32191                         inputs: []inputInfo{
32192                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32193                         },
32194                         outputs: []outputInfo{
32195                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32196                         },
32197                 },
32198         },
32199         {
32200                 name:        "OR",
32201                 argLen:      2,
32202                 commutative: true,
32203                 asm:         riscv.AOR,
32204                 reg: regInfo{
32205                         inputs: []inputInfo{
32206                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32207                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32208                         },
32209                         outputs: []outputInfo{
32210                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32211                         },
32212                 },
32213         },
32214         {
32215                 name:    "ORI",
32216                 auxType: auxInt64,
32217                 argLen:  1,
32218                 asm:     riscv.AORI,
32219                 reg: regInfo{
32220                         inputs: []inputInfo{
32221                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32222                         },
32223                         outputs: []outputInfo{
32224                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32225                         },
32226                 },
32227         },
32228         {
32229                 name:        "AND",
32230                 argLen:      2,
32231                 commutative: true,
32232                 asm:         riscv.AAND,
32233                 reg: regInfo{
32234                         inputs: []inputInfo{
32235                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32236                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32237                         },
32238                         outputs: []outputInfo{
32239                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32240                         },
32241                 },
32242         },
32243         {
32244                 name:    "ANDI",
32245                 auxType: auxInt64,
32246                 argLen:  1,
32247                 asm:     riscv.AANDI,
32248                 reg: regInfo{
32249                         inputs: []inputInfo{
32250                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32251                         },
32252                         outputs: []outputInfo{
32253                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32254                         },
32255                 },
32256         },
32257         {
32258                 name:   "NOT",
32259                 argLen: 1,
32260                 asm:    riscv.ANOT,
32261                 reg: regInfo{
32262                         inputs: []inputInfo{
32263                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32264                         },
32265                         outputs: []outputInfo{
32266                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32267                         },
32268                 },
32269         },
32270         {
32271                 name:   "SEQZ",
32272                 argLen: 1,
32273                 asm:    riscv.ASEQZ,
32274                 reg: regInfo{
32275                         inputs: []inputInfo{
32276                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32277                         },
32278                         outputs: []outputInfo{
32279                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32280                         },
32281                 },
32282         },
32283         {
32284                 name:   "SNEZ",
32285                 argLen: 1,
32286                 asm:    riscv.ASNEZ,
32287                 reg: regInfo{
32288                         inputs: []inputInfo{
32289                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32290                         },
32291                         outputs: []outputInfo{
32292                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32293                         },
32294                 },
32295         },
32296         {
32297                 name:   "SLT",
32298                 argLen: 2,
32299                 asm:    riscv.ASLT,
32300                 reg: regInfo{
32301                         inputs: []inputInfo{
32302                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32303                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32304                         },
32305                         outputs: []outputInfo{
32306                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32307                         },
32308                 },
32309         },
32310         {
32311                 name:    "SLTI",
32312                 auxType: auxInt64,
32313                 argLen:  1,
32314                 asm:     riscv.ASLTI,
32315                 reg: regInfo{
32316                         inputs: []inputInfo{
32317                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32318                         },
32319                         outputs: []outputInfo{
32320                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32321                         },
32322                 },
32323         },
32324         {
32325                 name:   "SLTU",
32326                 argLen: 2,
32327                 asm:    riscv.ASLTU,
32328                 reg: regInfo{
32329                         inputs: []inputInfo{
32330                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32331                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32332                         },
32333                         outputs: []outputInfo{
32334                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32335                         },
32336                 },
32337         },
32338         {
32339                 name:    "SLTIU",
32340                 auxType: auxInt64,
32341                 argLen:  1,
32342                 asm:     riscv.ASLTIU,
32343                 reg: regInfo{
32344                         inputs: []inputInfo{
32345                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32346                         },
32347                         outputs: []outputInfo{
32348                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32349                         },
32350                 },
32351         },
32352         {
32353                 name:         "LoweredRound32F",
32354                 argLen:       1,
32355                 resultInArg0: true,
32356                 reg: regInfo{
32357                         inputs: []inputInfo{
32358                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32359                         },
32360                         outputs: []outputInfo{
32361                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32362                         },
32363                 },
32364         },
32365         {
32366                 name:         "LoweredRound64F",
32367                 argLen:       1,
32368                 resultInArg0: true,
32369                 reg: regInfo{
32370                         inputs: []inputInfo{
32371                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32372                         },
32373                         outputs: []outputInfo{
32374                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32375                         },
32376                 },
32377         },
32378         {
32379                 name:    "CALLstatic",
32380                 auxType: auxCallOff,
32381                 argLen:  -1,
32382                 call:    true,
32383                 reg: regInfo{
32384                         clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32385                 },
32386         },
32387         {
32388                 name:     "CALLtail",
32389                 auxType:  auxCallOff,
32390                 argLen:   -1,
32391                 call:     true,
32392                 tailCall: true,
32393                 reg: regInfo{
32394                         clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32395                 },
32396         },
32397         {
32398                 name:    "CALLclosure",
32399                 auxType: auxCallOff,
32400                 argLen:  -1,
32401                 call:    true,
32402                 reg: regInfo{
32403                         inputs: []inputInfo{
32404                                 {1, 33554432},   // X26
32405                                 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32406                         },
32407                         clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32408                 },
32409         },
32410         {
32411                 name:    "CALLinter",
32412                 auxType: auxCallOff,
32413                 argLen:  -1,
32414                 call:    true,
32415                 reg: regInfo{
32416                         inputs: []inputInfo{
32417                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32418                         },
32419                         clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32420                 },
32421         },
32422         {
32423                 name:           "DUFFZERO",
32424                 auxType:        auxInt64,
32425                 argLen:         2,
32426                 faultOnNilArg0: true,
32427                 reg: regInfo{
32428                         inputs: []inputInfo{
32429                                 {0, 16777216}, // X25
32430                         },
32431                         clobbers: 16777216, // X25
32432                 },
32433         },
32434         {
32435                 name:           "DUFFCOPY",
32436                 auxType:        auxInt64,
32437                 argLen:         3,
32438                 faultOnNilArg0: true,
32439                 faultOnNilArg1: true,
32440                 reg: regInfo{
32441                         inputs: []inputInfo{
32442                                 {0, 16777216}, // X25
32443                                 {1, 8388608},  // X24
32444                         },
32445                         clobbers: 25165824, // X24 X25
32446                 },
32447         },
32448         {
32449                 name:           "LoweredZero",
32450                 auxType:        auxInt64,
32451                 argLen:         3,
32452                 faultOnNilArg0: true,
32453                 reg: regInfo{
32454                         inputs: []inputInfo{
32455                                 {0, 16},         // X5
32456                                 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32457                         },
32458                         clobbers: 16, // X5
32459                 },
32460         },
32461         {
32462                 name:           "LoweredMove",
32463                 auxType:        auxInt64,
32464                 argLen:         4,
32465                 faultOnNilArg0: true,
32466                 faultOnNilArg1: true,
32467                 reg: regInfo{
32468                         inputs: []inputInfo{
32469                                 {0, 16},         // X5
32470                                 {1, 32},         // X6
32471                                 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32472                         },
32473                         clobbers: 112, // X5 X6 X7
32474                 },
32475         },
32476         {
32477                 name:           "LoweredAtomicLoad8",
32478                 argLen:         2,
32479                 faultOnNilArg0: true,
32480                 reg: regInfo{
32481                         inputs: []inputInfo{
32482                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32483                         },
32484                         outputs: []outputInfo{
32485                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32486                         },
32487                 },
32488         },
32489         {
32490                 name:           "LoweredAtomicLoad32",
32491                 argLen:         2,
32492                 faultOnNilArg0: true,
32493                 reg: regInfo{
32494                         inputs: []inputInfo{
32495                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32496                         },
32497                         outputs: []outputInfo{
32498                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32499                         },
32500                 },
32501         },
32502         {
32503                 name:           "LoweredAtomicLoad64",
32504                 argLen:         2,
32505                 faultOnNilArg0: true,
32506                 reg: regInfo{
32507                         inputs: []inputInfo{
32508                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32509                         },
32510                         outputs: []outputInfo{
32511                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32512                         },
32513                 },
32514         },
32515         {
32516                 name:           "LoweredAtomicStore8",
32517                 argLen:         3,
32518                 faultOnNilArg0: true,
32519                 hasSideEffects: true,
32520                 reg: regInfo{
32521                         inputs: []inputInfo{
32522                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32523                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32524                         },
32525                 },
32526         },
32527         {
32528                 name:           "LoweredAtomicStore32",
32529                 argLen:         3,
32530                 faultOnNilArg0: true,
32531                 hasSideEffects: true,
32532                 reg: regInfo{
32533                         inputs: []inputInfo{
32534                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32535                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32536                         },
32537                 },
32538         },
32539         {
32540                 name:           "LoweredAtomicStore64",
32541                 argLen:         3,
32542                 faultOnNilArg0: true,
32543                 hasSideEffects: true,
32544                 reg: regInfo{
32545                         inputs: []inputInfo{
32546                                 {1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32547                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32548                         },
32549                 },
32550         },
32551         {
32552                 name:            "LoweredAtomicExchange32",
32553                 argLen:          3,
32554                 resultNotInArgs: true,
32555                 faultOnNilArg0:  true,
32556                 hasSideEffects:  true,
32557                 reg: regInfo{
32558                         inputs: []inputInfo{
32559                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32560                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32561                         },
32562                         outputs: []outputInfo{
32563                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32564                         },
32565                 },
32566         },
32567         {
32568                 name:            "LoweredAtomicExchange64",
32569                 argLen:          3,
32570                 resultNotInArgs: true,
32571                 faultOnNilArg0:  true,
32572                 hasSideEffects:  true,
32573                 reg: regInfo{
32574                         inputs: []inputInfo{
32575                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32576                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32577                         },
32578                         outputs: []outputInfo{
32579                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32580                         },
32581                 },
32582         },
32583         {
32584                 name:            "LoweredAtomicAdd32",
32585                 argLen:          3,
32586                 resultNotInArgs: true,
32587                 faultOnNilArg0:  true,
32588                 hasSideEffects:  true,
32589                 unsafePoint:     true,
32590                 reg: regInfo{
32591                         inputs: []inputInfo{
32592                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32593                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32594                         },
32595                         outputs: []outputInfo{
32596                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32597                         },
32598                 },
32599         },
32600         {
32601                 name:            "LoweredAtomicAdd64",
32602                 argLen:          3,
32603                 resultNotInArgs: true,
32604                 faultOnNilArg0:  true,
32605                 hasSideEffects:  true,
32606                 unsafePoint:     true,
32607                 reg: regInfo{
32608                         inputs: []inputInfo{
32609                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32610                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32611                         },
32612                         outputs: []outputInfo{
32613                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32614                         },
32615                 },
32616         },
32617         {
32618                 name:            "LoweredAtomicCas32",
32619                 argLen:          4,
32620                 resultNotInArgs: true,
32621                 faultOnNilArg0:  true,
32622                 hasSideEffects:  true,
32623                 unsafePoint:     true,
32624                 reg: regInfo{
32625                         inputs: []inputInfo{
32626                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32627                                 {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32628                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32629                         },
32630                         outputs: []outputInfo{
32631                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32632                         },
32633                 },
32634         },
32635         {
32636                 name:            "LoweredAtomicCas64",
32637                 argLen:          4,
32638                 resultNotInArgs: true,
32639                 faultOnNilArg0:  true,
32640                 hasSideEffects:  true,
32641                 unsafePoint:     true,
32642                 reg: regInfo{
32643                         inputs: []inputInfo{
32644                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32645                                 {2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32646                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32647                         },
32648                         outputs: []outputInfo{
32649                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32650                         },
32651                 },
32652         },
32653         {
32654                 name:           "LoweredAtomicAnd32",
32655                 argLen:         3,
32656                 faultOnNilArg0: true,
32657                 hasSideEffects: true,
32658                 asm:            riscv.AAMOANDW,
32659                 reg: regInfo{
32660                         inputs: []inputInfo{
32661                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32662                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32663                         },
32664                 },
32665         },
32666         {
32667                 name:           "LoweredAtomicOr32",
32668                 argLen:         3,
32669                 faultOnNilArg0: true,
32670                 hasSideEffects: true,
32671                 asm:            riscv.AAMOORW,
32672                 reg: regInfo{
32673                         inputs: []inputInfo{
32674                                 {1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
32675                                 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
32676                         },
32677                 },
32678         },
32679         {
32680                 name:           "LoweredNilCheck",
32681                 argLen:         2,
32682                 nilCheck:       true,
32683                 faultOnNilArg0: true,
32684                 reg: regInfo{
32685                         inputs: []inputInfo{
32686                                 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32687                         },
32688                 },
32689         },
32690         {
32691                 name:   "LoweredGetClosurePtr",
32692                 argLen: 0,
32693                 reg: regInfo{
32694                         outputs: []outputInfo{
32695                                 {0, 33554432}, // X26
32696                         },
32697                 },
32698         },
32699         {
32700                 name:              "LoweredGetCallerSP",
32701                 argLen:            1,
32702                 rematerializeable: true,
32703                 reg: regInfo{
32704                         outputs: []outputInfo{
32705                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32706                         },
32707                 },
32708         },
32709         {
32710                 name:              "LoweredGetCallerPC",
32711                 argLen:            0,
32712                 rematerializeable: true,
32713                 reg: regInfo{
32714                         outputs: []outputInfo{
32715                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32716                         },
32717                 },
32718         },
32719         {
32720                 name:         "LoweredWB",
32721                 auxType:      auxInt64,
32722                 argLen:       1,
32723                 clobberFlags: true,
32724                 reg: regInfo{
32725                         clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32726                         outputs: []outputInfo{
32727                                 {0, 8388608}, // X24
32728                         },
32729                 },
32730         },
32731         {
32732                 name:           "LoweredPubBarrier",
32733                 argLen:         1,
32734                 hasSideEffects: true,
32735                 asm:            riscv.AFENCE,
32736                 reg:            regInfo{},
32737         },
32738         {
32739                 name:    "LoweredPanicBoundsA",
32740                 auxType: auxInt64,
32741                 argLen:  3,
32742                 call:    true,
32743                 reg: regInfo{
32744                         inputs: []inputInfo{
32745                                 {0, 64},        // X7
32746                                 {1, 134217728}, // X28
32747                         },
32748                 },
32749         },
32750         {
32751                 name:    "LoweredPanicBoundsB",
32752                 auxType: auxInt64,
32753                 argLen:  3,
32754                 call:    true,
32755                 reg: regInfo{
32756                         inputs: []inputInfo{
32757                                 {0, 32}, // X6
32758                                 {1, 64}, // X7
32759                         },
32760                 },
32761         },
32762         {
32763                 name:    "LoweredPanicBoundsC",
32764                 auxType: auxInt64,
32765                 argLen:  3,
32766                 call:    true,
32767                 reg: regInfo{
32768                         inputs: []inputInfo{
32769                                 {0, 16}, // X5
32770                                 {1, 32}, // X6
32771                         },
32772                 },
32773         },
32774         {
32775                 name:        "FADDS",
32776                 argLen:      2,
32777                 commutative: true,
32778                 asm:         riscv.AFADDS,
32779                 reg: regInfo{
32780                         inputs: []inputInfo{
32781                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32782                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32783                         },
32784                         outputs: []outputInfo{
32785                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32786                         },
32787                 },
32788         },
32789         {
32790                 name:   "FSUBS",
32791                 argLen: 2,
32792                 asm:    riscv.AFSUBS,
32793                 reg: regInfo{
32794                         inputs: []inputInfo{
32795                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32796                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32797                         },
32798                         outputs: []outputInfo{
32799                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32800                         },
32801                 },
32802         },
32803         {
32804                 name:        "FMULS",
32805                 argLen:      2,
32806                 commutative: true,
32807                 asm:         riscv.AFMULS,
32808                 reg: regInfo{
32809                         inputs: []inputInfo{
32810                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32811                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32812                         },
32813                         outputs: []outputInfo{
32814                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32815                         },
32816                 },
32817         },
32818         {
32819                 name:   "FDIVS",
32820                 argLen: 2,
32821                 asm:    riscv.AFDIVS,
32822                 reg: regInfo{
32823                         inputs: []inputInfo{
32824                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32825                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32826                         },
32827                         outputs: []outputInfo{
32828                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32829                         },
32830                 },
32831         },
32832         {
32833                 name:        "FMADDS",
32834                 argLen:      3,
32835                 commutative: true,
32836                 asm:         riscv.AFMADDS,
32837                 reg: regInfo{
32838                         inputs: []inputInfo{
32839                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32840                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32841                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32842                         },
32843                         outputs: []outputInfo{
32844                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32845                         },
32846                 },
32847         },
32848         {
32849                 name:        "FMSUBS",
32850                 argLen:      3,
32851                 commutative: true,
32852                 asm:         riscv.AFMSUBS,
32853                 reg: regInfo{
32854                         inputs: []inputInfo{
32855                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32856                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32857                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32858                         },
32859                         outputs: []outputInfo{
32860                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32861                         },
32862                 },
32863         },
32864         {
32865                 name:        "FNMADDS",
32866                 argLen:      3,
32867                 commutative: true,
32868                 asm:         riscv.AFNMADDS,
32869                 reg: regInfo{
32870                         inputs: []inputInfo{
32871                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32872                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32873                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32874                         },
32875                         outputs: []outputInfo{
32876                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32877                         },
32878                 },
32879         },
32880         {
32881                 name:        "FNMSUBS",
32882                 argLen:      3,
32883                 commutative: true,
32884                 asm:         riscv.AFNMSUBS,
32885                 reg: regInfo{
32886                         inputs: []inputInfo{
32887                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32888                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32889                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32890                         },
32891                         outputs: []outputInfo{
32892                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32893                         },
32894                 },
32895         },
32896         {
32897                 name:   "FSQRTS",
32898                 argLen: 1,
32899                 asm:    riscv.AFSQRTS,
32900                 reg: regInfo{
32901                         inputs: []inputInfo{
32902                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32903                         },
32904                         outputs: []outputInfo{
32905                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32906                         },
32907                 },
32908         },
32909         {
32910                 name:   "FNEGS",
32911                 argLen: 1,
32912                 asm:    riscv.AFNEGS,
32913                 reg: regInfo{
32914                         inputs: []inputInfo{
32915                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32916                         },
32917                         outputs: []outputInfo{
32918                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32919                         },
32920                 },
32921         },
32922         {
32923                 name:   "FMVSX",
32924                 argLen: 1,
32925                 asm:    riscv.AFMVSX,
32926                 reg: regInfo{
32927                         inputs: []inputInfo{
32928                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32929                         },
32930                         outputs: []outputInfo{
32931                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32932                         },
32933                 },
32934         },
32935         {
32936                 name:   "FCVTSW",
32937                 argLen: 1,
32938                 asm:    riscv.AFCVTSW,
32939                 reg: regInfo{
32940                         inputs: []inputInfo{
32941                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32942                         },
32943                         outputs: []outputInfo{
32944                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32945                         },
32946                 },
32947         },
32948         {
32949                 name:   "FCVTSL",
32950                 argLen: 1,
32951                 asm:    riscv.AFCVTSL,
32952                 reg: regInfo{
32953                         inputs: []inputInfo{
32954                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32955                         },
32956                         outputs: []outputInfo{
32957                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32958                         },
32959                 },
32960         },
32961         {
32962                 name:   "FCVTWS",
32963                 argLen: 1,
32964                 asm:    riscv.AFCVTWS,
32965                 reg: regInfo{
32966                         inputs: []inputInfo{
32967                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32968                         },
32969                         outputs: []outputInfo{
32970                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32971                         },
32972                 },
32973         },
32974         {
32975                 name:   "FCVTLS",
32976                 argLen: 1,
32977                 asm:    riscv.AFCVTLS,
32978                 reg: regInfo{
32979                         inputs: []inputInfo{
32980                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
32981                         },
32982                         outputs: []outputInfo{
32983                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
32984                         },
32985                 },
32986         },
32987         {
32988                 name:           "FMOVWload",
32989                 auxType:        auxSymOff,
32990                 argLen:         2,
32991                 faultOnNilArg0: true,
32992                 symEffect:      SymRead,
32993                 asm:            riscv.AMOVF,
32994                 reg: regInfo{
32995                         inputs: []inputInfo{
32996                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
32997                         },
32998                         outputs: []outputInfo{
32999                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33000                         },
33001                 },
33002         },
33003         {
33004                 name:           "FMOVWstore",
33005                 auxType:        auxSymOff,
33006                 argLen:         3,
33007                 faultOnNilArg0: true,
33008                 symEffect:      SymWrite,
33009                 asm:            riscv.AMOVF,
33010                 reg: regInfo{
33011                         inputs: []inputInfo{
33012                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
33013                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33014                         },
33015                 },
33016         },
33017         {
33018                 name:        "FEQS",
33019                 argLen:      2,
33020                 commutative: true,
33021                 asm:         riscv.AFEQS,
33022                 reg: regInfo{
33023                         inputs: []inputInfo{
33024                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33025                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33026                         },
33027                         outputs: []outputInfo{
33028                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33029                         },
33030                 },
33031         },
33032         {
33033                 name:        "FNES",
33034                 argLen:      2,
33035                 commutative: true,
33036                 asm:         riscv.AFNES,
33037                 reg: regInfo{
33038                         inputs: []inputInfo{
33039                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33040                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33041                         },
33042                         outputs: []outputInfo{
33043                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33044                         },
33045                 },
33046         },
33047         {
33048                 name:   "FLTS",
33049                 argLen: 2,
33050                 asm:    riscv.AFLTS,
33051                 reg: regInfo{
33052                         inputs: []inputInfo{
33053                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33054                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33055                         },
33056                         outputs: []outputInfo{
33057                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33058                         },
33059                 },
33060         },
33061         {
33062                 name:   "FLES",
33063                 argLen: 2,
33064                 asm:    riscv.AFLES,
33065                 reg: regInfo{
33066                         inputs: []inputInfo{
33067                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33068                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33069                         },
33070                         outputs: []outputInfo{
33071                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33072                         },
33073                 },
33074         },
33075         {
33076                 name:        "FADDD",
33077                 argLen:      2,
33078                 commutative: true,
33079                 asm:         riscv.AFADDD,
33080                 reg: regInfo{
33081                         inputs: []inputInfo{
33082                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33083                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33084                         },
33085                         outputs: []outputInfo{
33086                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33087                         },
33088                 },
33089         },
33090         {
33091                 name:   "FSUBD",
33092                 argLen: 2,
33093                 asm:    riscv.AFSUBD,
33094                 reg: regInfo{
33095                         inputs: []inputInfo{
33096                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33097                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33098                         },
33099                         outputs: []outputInfo{
33100                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33101                         },
33102                 },
33103         },
33104         {
33105                 name:        "FMULD",
33106                 argLen:      2,
33107                 commutative: true,
33108                 asm:         riscv.AFMULD,
33109                 reg: regInfo{
33110                         inputs: []inputInfo{
33111                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33112                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33113                         },
33114                         outputs: []outputInfo{
33115                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33116                         },
33117                 },
33118         },
33119         {
33120                 name:   "FDIVD",
33121                 argLen: 2,
33122                 asm:    riscv.AFDIVD,
33123                 reg: regInfo{
33124                         inputs: []inputInfo{
33125                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33126                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33127                         },
33128                         outputs: []outputInfo{
33129                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33130                         },
33131                 },
33132         },
33133         {
33134                 name:        "FMADDD",
33135                 argLen:      3,
33136                 commutative: true,
33137                 asm:         riscv.AFMADDD,
33138                 reg: regInfo{
33139                         inputs: []inputInfo{
33140                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33141                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33142                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33143                         },
33144                         outputs: []outputInfo{
33145                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33146                         },
33147                 },
33148         },
33149         {
33150                 name:        "FMSUBD",
33151                 argLen:      3,
33152                 commutative: true,
33153                 asm:         riscv.AFMSUBD,
33154                 reg: regInfo{
33155                         inputs: []inputInfo{
33156                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33157                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33158                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33159                         },
33160                         outputs: []outputInfo{
33161                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33162                         },
33163                 },
33164         },
33165         {
33166                 name:        "FNMADDD",
33167                 argLen:      3,
33168                 commutative: true,
33169                 asm:         riscv.AFNMADDD,
33170                 reg: regInfo{
33171                         inputs: []inputInfo{
33172                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33173                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33174                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33175                         },
33176                         outputs: []outputInfo{
33177                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33178                         },
33179                 },
33180         },
33181         {
33182                 name:        "FNMSUBD",
33183                 argLen:      3,
33184                 commutative: true,
33185                 asm:         riscv.AFNMSUBD,
33186                 reg: regInfo{
33187                         inputs: []inputInfo{
33188                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33189                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33190                                 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33191                         },
33192                         outputs: []outputInfo{
33193                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33194                         },
33195                 },
33196         },
33197         {
33198                 name:   "FSQRTD",
33199                 argLen: 1,
33200                 asm:    riscv.AFSQRTD,
33201                 reg: regInfo{
33202                         inputs: []inputInfo{
33203                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33204                         },
33205                         outputs: []outputInfo{
33206                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33207                         },
33208                 },
33209         },
33210         {
33211                 name:   "FNEGD",
33212                 argLen: 1,
33213                 asm:    riscv.AFNEGD,
33214                 reg: regInfo{
33215                         inputs: []inputInfo{
33216                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33217                         },
33218                         outputs: []outputInfo{
33219                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33220                         },
33221                 },
33222         },
33223         {
33224                 name:   "FABSD",
33225                 argLen: 1,
33226                 asm:    riscv.AFABSD,
33227                 reg: regInfo{
33228                         inputs: []inputInfo{
33229                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33230                         },
33231                         outputs: []outputInfo{
33232                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33233                         },
33234                 },
33235         },
33236         {
33237                 name:   "FSGNJD",
33238                 argLen: 2,
33239                 asm:    riscv.AFSGNJD,
33240                 reg: regInfo{
33241                         inputs: []inputInfo{
33242                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33243                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33244                         },
33245                         outputs: []outputInfo{
33246                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33247                         },
33248                 },
33249         },
33250         {
33251                 name:   "FMVDX",
33252                 argLen: 1,
33253                 asm:    riscv.AFMVDX,
33254                 reg: regInfo{
33255                         inputs: []inputInfo{
33256                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33257                         },
33258                         outputs: []outputInfo{
33259                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33260                         },
33261                 },
33262         },
33263         {
33264                 name:   "FCVTDW",
33265                 argLen: 1,
33266                 asm:    riscv.AFCVTDW,
33267                 reg: regInfo{
33268                         inputs: []inputInfo{
33269                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33270                         },
33271                         outputs: []outputInfo{
33272                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33273                         },
33274                 },
33275         },
33276         {
33277                 name:   "FCVTDL",
33278                 argLen: 1,
33279                 asm:    riscv.AFCVTDL,
33280                 reg: regInfo{
33281                         inputs: []inputInfo{
33282                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33283                         },
33284                         outputs: []outputInfo{
33285                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33286                         },
33287                 },
33288         },
33289         {
33290                 name:   "FCVTWD",
33291                 argLen: 1,
33292                 asm:    riscv.AFCVTWD,
33293                 reg: regInfo{
33294                         inputs: []inputInfo{
33295                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33296                         },
33297                         outputs: []outputInfo{
33298                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33299                         },
33300                 },
33301         },
33302         {
33303                 name:   "FCVTLD",
33304                 argLen: 1,
33305                 asm:    riscv.AFCVTLD,
33306                 reg: regInfo{
33307                         inputs: []inputInfo{
33308                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33309                         },
33310                         outputs: []outputInfo{
33311                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33312                         },
33313                 },
33314         },
33315         {
33316                 name:   "FCVTDS",
33317                 argLen: 1,
33318                 asm:    riscv.AFCVTDS,
33319                 reg: regInfo{
33320                         inputs: []inputInfo{
33321                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33322                         },
33323                         outputs: []outputInfo{
33324                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33325                         },
33326                 },
33327         },
33328         {
33329                 name:   "FCVTSD",
33330                 argLen: 1,
33331                 asm:    riscv.AFCVTSD,
33332                 reg: regInfo{
33333                         inputs: []inputInfo{
33334                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33335                         },
33336                         outputs: []outputInfo{
33337                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33338                         },
33339                 },
33340         },
33341         {
33342                 name:           "FMOVDload",
33343                 auxType:        auxSymOff,
33344                 argLen:         2,
33345                 faultOnNilArg0: true,
33346                 symEffect:      SymRead,
33347                 asm:            riscv.AMOVD,
33348                 reg: regInfo{
33349                         inputs: []inputInfo{
33350                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
33351                         },
33352                         outputs: []outputInfo{
33353                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33354                         },
33355                 },
33356         },
33357         {
33358                 name:           "FMOVDstore",
33359                 auxType:        auxSymOff,
33360                 argLen:         3,
33361                 faultOnNilArg0: true,
33362                 symEffect:      SymWrite,
33363                 asm:            riscv.AMOVD,
33364                 reg: regInfo{
33365                         inputs: []inputInfo{
33366                                 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
33367                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33368                         },
33369                 },
33370         },
33371         {
33372                 name:        "FEQD",
33373                 argLen:      2,
33374                 commutative: true,
33375                 asm:         riscv.AFEQD,
33376                 reg: regInfo{
33377                         inputs: []inputInfo{
33378                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33379                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33380                         },
33381                         outputs: []outputInfo{
33382                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33383                         },
33384                 },
33385         },
33386         {
33387                 name:        "FNED",
33388                 argLen:      2,
33389                 commutative: true,
33390                 asm:         riscv.AFNED,
33391                 reg: regInfo{
33392                         inputs: []inputInfo{
33393                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33394                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33395                         },
33396                         outputs: []outputInfo{
33397                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33398                         },
33399                 },
33400         },
33401         {
33402                 name:   "FLTD",
33403                 argLen: 2,
33404                 asm:    riscv.AFLTD,
33405                 reg: regInfo{
33406                         inputs: []inputInfo{
33407                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33408                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33409                         },
33410                         outputs: []outputInfo{
33411                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33412                         },
33413                 },
33414         },
33415         {
33416                 name:   "FLED",
33417                 argLen: 2,
33418                 asm:    riscv.AFLED,
33419                 reg: regInfo{
33420                         inputs: []inputInfo{
33421                                 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33422                                 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33423                         },
33424                         outputs: []outputInfo{
33425                                 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
33426                         },
33427                 },
33428         },
33429
33430         {
33431                 name:         "FADDS",
33432                 argLen:       2,
33433                 commutative:  true,
33434                 resultInArg0: true,
33435                 asm:          s390x.AFADDS,
33436                 reg: regInfo{
33437                         inputs: []inputInfo{
33438                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33439                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33440                         },
33441                         outputs: []outputInfo{
33442                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33443                         },
33444                 },
33445         },
33446         {
33447                 name:         "FADD",
33448                 argLen:       2,
33449                 commutative:  true,
33450                 resultInArg0: true,
33451                 asm:          s390x.AFADD,
33452                 reg: regInfo{
33453                         inputs: []inputInfo{
33454                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33455                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33456                         },
33457                         outputs: []outputInfo{
33458                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33459                         },
33460                 },
33461         },
33462         {
33463                 name:         "FSUBS",
33464                 argLen:       2,
33465                 resultInArg0: true,
33466                 asm:          s390x.AFSUBS,
33467                 reg: regInfo{
33468                         inputs: []inputInfo{
33469                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33470                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33471                         },
33472                         outputs: []outputInfo{
33473                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33474                         },
33475                 },
33476         },
33477         {
33478                 name:         "FSUB",
33479                 argLen:       2,
33480                 resultInArg0: true,
33481                 asm:          s390x.AFSUB,
33482                 reg: regInfo{
33483                         inputs: []inputInfo{
33484                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33485                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33486                         },
33487                         outputs: []outputInfo{
33488                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33489                         },
33490                 },
33491         },
33492         {
33493                 name:         "FMULS",
33494                 argLen:       2,
33495                 commutative:  true,
33496                 resultInArg0: true,
33497                 asm:          s390x.AFMULS,
33498                 reg: regInfo{
33499                         inputs: []inputInfo{
33500                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33501                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33502                         },
33503                         outputs: []outputInfo{
33504                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33505                         },
33506                 },
33507         },
33508         {
33509                 name:         "FMUL",
33510                 argLen:       2,
33511                 commutative:  true,
33512                 resultInArg0: true,
33513                 asm:          s390x.AFMUL,
33514                 reg: regInfo{
33515                         inputs: []inputInfo{
33516                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33517                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33518                         },
33519                         outputs: []outputInfo{
33520                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33521                         },
33522                 },
33523         },
33524         {
33525                 name:         "FDIVS",
33526                 argLen:       2,
33527                 resultInArg0: true,
33528                 asm:          s390x.AFDIVS,
33529                 reg: regInfo{
33530                         inputs: []inputInfo{
33531                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33532                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33533                         },
33534                         outputs: []outputInfo{
33535                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33536                         },
33537                 },
33538         },
33539         {
33540                 name:         "FDIV",
33541                 argLen:       2,
33542                 resultInArg0: true,
33543                 asm:          s390x.AFDIV,
33544                 reg: regInfo{
33545                         inputs: []inputInfo{
33546                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33547                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33548                         },
33549                         outputs: []outputInfo{
33550                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33551                         },
33552                 },
33553         },
33554         {
33555                 name:         "FNEGS",
33556                 argLen:       1,
33557                 clobberFlags: true,
33558                 asm:          s390x.AFNEGS,
33559                 reg: regInfo{
33560                         inputs: []inputInfo{
33561                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33562                         },
33563                         outputs: []outputInfo{
33564                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33565                         },
33566                 },
33567         },
33568         {
33569                 name:         "FNEG",
33570                 argLen:       1,
33571                 clobberFlags: true,
33572                 asm:          s390x.AFNEG,
33573                 reg: regInfo{
33574                         inputs: []inputInfo{
33575                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33576                         },
33577                         outputs: []outputInfo{
33578                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33579                         },
33580                 },
33581         },
33582         {
33583                 name:         "FMADDS",
33584                 argLen:       3,
33585                 resultInArg0: true,
33586                 asm:          s390x.AFMADDS,
33587                 reg: regInfo{
33588                         inputs: []inputInfo{
33589                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33590                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33591                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33592                         },
33593                         outputs: []outputInfo{
33594                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33595                         },
33596                 },
33597         },
33598         {
33599                 name:         "FMADD",
33600                 argLen:       3,
33601                 resultInArg0: true,
33602                 asm:          s390x.AFMADD,
33603                 reg: regInfo{
33604                         inputs: []inputInfo{
33605                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33606                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33607                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33608                         },
33609                         outputs: []outputInfo{
33610                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33611                         },
33612                 },
33613         },
33614         {
33615                 name:         "FMSUBS",
33616                 argLen:       3,
33617                 resultInArg0: true,
33618                 asm:          s390x.AFMSUBS,
33619                 reg: regInfo{
33620                         inputs: []inputInfo{
33621                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33622                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33623                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33624                         },
33625                         outputs: []outputInfo{
33626                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33627                         },
33628                 },
33629         },
33630         {
33631                 name:         "FMSUB",
33632                 argLen:       3,
33633                 resultInArg0: true,
33634                 asm:          s390x.AFMSUB,
33635                 reg: regInfo{
33636                         inputs: []inputInfo{
33637                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33638                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33639                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33640                         },
33641                         outputs: []outputInfo{
33642                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33643                         },
33644                 },
33645         },
33646         {
33647                 name:   "LPDFR",
33648                 argLen: 1,
33649                 asm:    s390x.ALPDFR,
33650                 reg: regInfo{
33651                         inputs: []inputInfo{
33652                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33653                         },
33654                         outputs: []outputInfo{
33655                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33656                         },
33657                 },
33658         },
33659         {
33660                 name:   "LNDFR",
33661                 argLen: 1,
33662                 asm:    s390x.ALNDFR,
33663                 reg: regInfo{
33664                         inputs: []inputInfo{
33665                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33666                         },
33667                         outputs: []outputInfo{
33668                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33669                         },
33670                 },
33671         },
33672         {
33673                 name:   "CPSDR",
33674                 argLen: 2,
33675                 asm:    s390x.ACPSDR,
33676                 reg: regInfo{
33677                         inputs: []inputInfo{
33678                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33679                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33680                         },
33681                         outputs: []outputInfo{
33682                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33683                         },
33684                 },
33685         },
33686         {
33687                 name:    "FIDBR",
33688                 auxType: auxInt8,
33689                 argLen:  1,
33690                 asm:     s390x.AFIDBR,
33691                 reg: regInfo{
33692                         inputs: []inputInfo{
33693                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33694                         },
33695                         outputs: []outputInfo{
33696                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33697                         },
33698                 },
33699         },
33700         {
33701                 name:           "FMOVSload",
33702                 auxType:        auxSymOff,
33703                 argLen:         2,
33704                 faultOnNilArg0: true,
33705                 symEffect:      SymRead,
33706                 asm:            s390x.AFMOVS,
33707                 reg: regInfo{
33708                         inputs: []inputInfo{
33709                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33710                         },
33711                         outputs: []outputInfo{
33712                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33713                         },
33714                 },
33715         },
33716         {
33717                 name:           "FMOVDload",
33718                 auxType:        auxSymOff,
33719                 argLen:         2,
33720                 faultOnNilArg0: true,
33721                 symEffect:      SymRead,
33722                 asm:            s390x.AFMOVD,
33723                 reg: regInfo{
33724                         inputs: []inputInfo{
33725                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33726                         },
33727                         outputs: []outputInfo{
33728                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33729                         },
33730                 },
33731         },
33732         {
33733                 name:              "FMOVSconst",
33734                 auxType:           auxFloat32,
33735                 argLen:            0,
33736                 rematerializeable: true,
33737                 asm:               s390x.AFMOVS,
33738                 reg: regInfo{
33739                         outputs: []outputInfo{
33740                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33741                         },
33742                 },
33743         },
33744         {
33745                 name:              "FMOVDconst",
33746                 auxType:           auxFloat64,
33747                 argLen:            0,
33748                 rematerializeable: true,
33749                 asm:               s390x.AFMOVD,
33750                 reg: regInfo{
33751                         outputs: []outputInfo{
33752                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33753                         },
33754                 },
33755         },
33756         {
33757                 name:      "FMOVSloadidx",
33758                 auxType:   auxSymOff,
33759                 argLen:    3,
33760                 symEffect: SymRead,
33761                 asm:       s390x.AFMOVS,
33762                 reg: regInfo{
33763                         inputs: []inputInfo{
33764                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33765                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33766                         },
33767                         outputs: []outputInfo{
33768                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33769                         },
33770                 },
33771         },
33772         {
33773                 name:      "FMOVDloadidx",
33774                 auxType:   auxSymOff,
33775                 argLen:    3,
33776                 symEffect: SymRead,
33777                 asm:       s390x.AFMOVD,
33778                 reg: regInfo{
33779                         inputs: []inputInfo{
33780                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33781                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33782                         },
33783                         outputs: []outputInfo{
33784                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33785                         },
33786                 },
33787         },
33788         {
33789                 name:           "FMOVSstore",
33790                 auxType:        auxSymOff,
33791                 argLen:         3,
33792                 faultOnNilArg0: true,
33793                 symEffect:      SymWrite,
33794                 asm:            s390x.AFMOVS,
33795                 reg: regInfo{
33796                         inputs: []inputInfo{
33797                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33798                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33799                         },
33800                 },
33801         },
33802         {
33803                 name:           "FMOVDstore",
33804                 auxType:        auxSymOff,
33805                 argLen:         3,
33806                 faultOnNilArg0: true,
33807                 symEffect:      SymWrite,
33808                 asm:            s390x.AFMOVD,
33809                 reg: regInfo{
33810                         inputs: []inputInfo{
33811                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33812                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33813                         },
33814                 },
33815         },
33816         {
33817                 name:      "FMOVSstoreidx",
33818                 auxType:   auxSymOff,
33819                 argLen:    4,
33820                 symEffect: SymWrite,
33821                 asm:       s390x.AFMOVS,
33822                 reg: regInfo{
33823                         inputs: []inputInfo{
33824                                 {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33825                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33826                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33827                         },
33828                 },
33829         },
33830         {
33831                 name:      "FMOVDstoreidx",
33832                 auxType:   auxSymOff,
33833                 argLen:    4,
33834                 symEffect: SymWrite,
33835                 asm:       s390x.AFMOVD,
33836                 reg: regInfo{
33837                         inputs: []inputInfo{
33838                                 {0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33839                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33840                                 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33841                         },
33842                 },
33843         },
33844         {
33845                 name:         "ADD",
33846                 argLen:       2,
33847                 commutative:  true,
33848                 clobberFlags: true,
33849                 asm:          s390x.AADD,
33850                 reg: regInfo{
33851                         inputs: []inputInfo{
33852                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33853                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33854                         },
33855                         outputs: []outputInfo{
33856                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33857                         },
33858                 },
33859         },
33860         {
33861                 name:         "ADDW",
33862                 argLen:       2,
33863                 commutative:  true,
33864                 clobberFlags: true,
33865                 asm:          s390x.AADDW,
33866                 reg: regInfo{
33867                         inputs: []inputInfo{
33868                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33869                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33870                         },
33871                         outputs: []outputInfo{
33872                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33873                         },
33874                 },
33875         },
33876         {
33877                 name:         "ADDconst",
33878                 auxType:      auxInt32,
33879                 argLen:       1,
33880                 clobberFlags: true,
33881                 asm:          s390x.AADD,
33882                 reg: regInfo{
33883                         inputs: []inputInfo{
33884                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33885                         },
33886                         outputs: []outputInfo{
33887                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33888                         },
33889                 },
33890         },
33891         {
33892                 name:         "ADDWconst",
33893                 auxType:      auxInt32,
33894                 argLen:       1,
33895                 clobberFlags: true,
33896                 asm:          s390x.AADDW,
33897                 reg: regInfo{
33898                         inputs: []inputInfo{
33899                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33900                         },
33901                         outputs: []outputInfo{
33902                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33903                         },
33904                 },
33905         },
33906         {
33907                 name:           "ADDload",
33908                 auxType:        auxSymOff,
33909                 argLen:         3,
33910                 resultInArg0:   true,
33911                 clobberFlags:   true,
33912                 faultOnNilArg1: true,
33913                 symEffect:      SymRead,
33914                 asm:            s390x.AADD,
33915                 reg: regInfo{
33916                         inputs: []inputInfo{
33917                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33918                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33919                         },
33920                         outputs: []outputInfo{
33921                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33922                         },
33923                 },
33924         },
33925         {
33926                 name:           "ADDWload",
33927                 auxType:        auxSymOff,
33928                 argLen:         3,
33929                 resultInArg0:   true,
33930                 clobberFlags:   true,
33931                 faultOnNilArg1: true,
33932                 symEffect:      SymRead,
33933                 asm:            s390x.AADDW,
33934                 reg: regInfo{
33935                         inputs: []inputInfo{
33936                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33937                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33938                         },
33939                         outputs: []outputInfo{
33940                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33941                         },
33942                 },
33943         },
33944         {
33945                 name:         "SUB",
33946                 argLen:       2,
33947                 clobberFlags: true,
33948                 asm:          s390x.ASUB,
33949                 reg: regInfo{
33950                         inputs: []inputInfo{
33951                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33952                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33953                         },
33954                         outputs: []outputInfo{
33955                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33956                         },
33957                 },
33958         },
33959         {
33960                 name:         "SUBW",
33961                 argLen:       2,
33962                 clobberFlags: true,
33963                 asm:          s390x.ASUBW,
33964                 reg: regInfo{
33965                         inputs: []inputInfo{
33966                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33967                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33968                         },
33969                         outputs: []outputInfo{
33970                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33971                         },
33972                 },
33973         },
33974         {
33975                 name:         "SUBconst",
33976                 auxType:      auxInt32,
33977                 argLen:       1,
33978                 resultInArg0: true,
33979                 clobberFlags: true,
33980                 asm:          s390x.ASUB,
33981                 reg: regInfo{
33982                         inputs: []inputInfo{
33983                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33984                         },
33985                         outputs: []outputInfo{
33986                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33987                         },
33988                 },
33989         },
33990         {
33991                 name:         "SUBWconst",
33992                 auxType:      auxInt32,
33993                 argLen:       1,
33994                 resultInArg0: true,
33995                 clobberFlags: true,
33996                 asm:          s390x.ASUBW,
33997                 reg: regInfo{
33998                         inputs: []inputInfo{
33999                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34000                         },
34001                         outputs: []outputInfo{
34002                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34003                         },
34004                 },
34005         },
34006         {
34007                 name:           "SUBload",
34008                 auxType:        auxSymOff,
34009                 argLen:         3,
34010                 resultInArg0:   true,
34011                 clobberFlags:   true,
34012                 faultOnNilArg1: true,
34013                 symEffect:      SymRead,
34014                 asm:            s390x.ASUB,
34015                 reg: regInfo{
34016                         inputs: []inputInfo{
34017                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34018                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34019                         },
34020                         outputs: []outputInfo{
34021                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34022                         },
34023                 },
34024         },
34025         {
34026                 name:           "SUBWload",
34027                 auxType:        auxSymOff,
34028                 argLen:         3,
34029                 resultInArg0:   true,
34030                 clobberFlags:   true,
34031                 faultOnNilArg1: true,
34032                 symEffect:      SymRead,
34033                 asm:            s390x.ASUBW,
34034                 reg: regInfo{
34035                         inputs: []inputInfo{
34036                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34037                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34038                         },
34039                         outputs: []outputInfo{
34040                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34041                         },
34042                 },
34043         },
34044         {
34045                 name:         "MULLD",
34046                 argLen:       2,
34047                 commutative:  true,
34048                 resultInArg0: true,
34049                 clobberFlags: true,
34050                 asm:          s390x.AMULLD,
34051                 reg: regInfo{
34052                         inputs: []inputInfo{
34053                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34054                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34055                         },
34056                         outputs: []outputInfo{
34057                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34058                         },
34059                 },
34060         },
34061         {
34062                 name:         "MULLW",
34063                 argLen:       2,
34064                 commutative:  true,
34065                 resultInArg0: true,
34066                 clobberFlags: true,
34067                 asm:          s390x.AMULLW,
34068                 reg: regInfo{
34069                         inputs: []inputInfo{
34070                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34071                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34072                         },
34073                         outputs: []outputInfo{
34074                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34075                         },
34076                 },
34077         },
34078         {
34079                 name:         "MULLDconst",
34080                 auxType:      auxInt32,
34081                 argLen:       1,
34082                 resultInArg0: true,
34083                 clobberFlags: true,
34084                 asm:          s390x.AMULLD,
34085                 reg: regInfo{
34086                         inputs: []inputInfo{
34087                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34088                         },
34089                         outputs: []outputInfo{
34090                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34091                         },
34092                 },
34093         },
34094         {
34095                 name:         "MULLWconst",
34096                 auxType:      auxInt32,
34097                 argLen:       1,
34098                 resultInArg0: true,
34099                 clobberFlags: true,
34100                 asm:          s390x.AMULLW,
34101                 reg: regInfo{
34102                         inputs: []inputInfo{
34103                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34104                         },
34105                         outputs: []outputInfo{
34106                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34107                         },
34108                 },
34109         },
34110         {
34111                 name:           "MULLDload",
34112                 auxType:        auxSymOff,
34113                 argLen:         3,
34114                 resultInArg0:   true,
34115                 clobberFlags:   true,
34116                 faultOnNilArg1: true,
34117                 symEffect:      SymRead,
34118                 asm:            s390x.AMULLD,
34119                 reg: regInfo{
34120                         inputs: []inputInfo{
34121                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34122                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34123                         },
34124                         outputs: []outputInfo{
34125                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34126                         },
34127                 },
34128         },
34129         {
34130                 name:           "MULLWload",
34131                 auxType:        auxSymOff,
34132                 argLen:         3,
34133                 resultInArg0:   true,
34134                 clobberFlags:   true,
34135                 faultOnNilArg1: true,
34136                 symEffect:      SymRead,
34137                 asm:            s390x.AMULLW,
34138                 reg: regInfo{
34139                         inputs: []inputInfo{
34140                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34141                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34142                         },
34143                         outputs: []outputInfo{
34144                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34145                         },
34146                 },
34147         },
34148         {
34149                 name:         "MULHD",
34150                 argLen:       2,
34151                 commutative:  true,
34152                 resultInArg0: true,
34153                 clobberFlags: true,
34154                 asm:          s390x.AMULHD,
34155                 reg: regInfo{
34156                         inputs: []inputInfo{
34157                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34158                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34159                         },
34160                         clobbers: 2048, // R11
34161                         outputs: []outputInfo{
34162                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34163                         },
34164                 },
34165         },
34166         {
34167                 name:         "MULHDU",
34168                 argLen:       2,
34169                 commutative:  true,
34170                 resultInArg0: true,
34171                 clobberFlags: true,
34172                 asm:          s390x.AMULHDU,
34173                 reg: regInfo{
34174                         inputs: []inputInfo{
34175                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34176                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34177                         },
34178                         clobbers: 2048, // R11
34179                         outputs: []outputInfo{
34180                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34181                         },
34182                 },
34183         },
34184         {
34185                 name:         "DIVD",
34186                 argLen:       2,
34187                 resultInArg0: true,
34188                 clobberFlags: true,
34189                 asm:          s390x.ADIVD,
34190                 reg: regInfo{
34191                         inputs: []inputInfo{
34192                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34193                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34194                         },
34195                         clobbers: 2048, // R11
34196                         outputs: []outputInfo{
34197                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34198                         },
34199                 },
34200         },
34201         {
34202                 name:         "DIVW",
34203                 argLen:       2,
34204                 resultInArg0: true,
34205                 clobberFlags: true,
34206                 asm:          s390x.ADIVW,
34207                 reg: regInfo{
34208                         inputs: []inputInfo{
34209                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34210                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34211                         },
34212                         clobbers: 2048, // R11
34213                         outputs: []outputInfo{
34214                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34215                         },
34216                 },
34217         },
34218         {
34219                 name:         "DIVDU",
34220                 argLen:       2,
34221                 resultInArg0: true,
34222                 clobberFlags: true,
34223                 asm:          s390x.ADIVDU,
34224                 reg: regInfo{
34225                         inputs: []inputInfo{
34226                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34227                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34228                         },
34229                         clobbers: 2048, // R11
34230                         outputs: []outputInfo{
34231                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34232                         },
34233                 },
34234         },
34235         {
34236                 name:         "DIVWU",
34237                 argLen:       2,
34238                 resultInArg0: true,
34239                 clobberFlags: true,
34240                 asm:          s390x.ADIVWU,
34241                 reg: regInfo{
34242                         inputs: []inputInfo{
34243                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34244                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34245                         },
34246                         clobbers: 2048, // R11
34247                         outputs: []outputInfo{
34248                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34249                         },
34250                 },
34251         },
34252         {
34253                 name:         "MODD",
34254                 argLen:       2,
34255                 resultInArg0: true,
34256                 clobberFlags: true,
34257                 asm:          s390x.AMODD,
34258                 reg: regInfo{
34259                         inputs: []inputInfo{
34260                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34261                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34262                         },
34263                         clobbers: 2048, // R11
34264                         outputs: []outputInfo{
34265                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34266                         },
34267                 },
34268         },
34269         {
34270                 name:         "MODW",
34271                 argLen:       2,
34272                 resultInArg0: true,
34273                 clobberFlags: true,
34274                 asm:          s390x.AMODW,
34275                 reg: regInfo{
34276                         inputs: []inputInfo{
34277                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34278                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34279                         },
34280                         clobbers: 2048, // R11
34281                         outputs: []outputInfo{
34282                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34283                         },
34284                 },
34285         },
34286         {
34287                 name:         "MODDU",
34288                 argLen:       2,
34289                 resultInArg0: true,
34290                 clobberFlags: true,
34291                 asm:          s390x.AMODDU,
34292                 reg: regInfo{
34293                         inputs: []inputInfo{
34294                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34295                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34296                         },
34297                         clobbers: 2048, // R11
34298                         outputs: []outputInfo{
34299                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34300                         },
34301                 },
34302         },
34303         {
34304                 name:         "MODWU",
34305                 argLen:       2,
34306                 resultInArg0: true,
34307                 clobberFlags: true,
34308                 asm:          s390x.AMODWU,
34309                 reg: regInfo{
34310                         inputs: []inputInfo{
34311                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34312                                 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34313                         },
34314                         clobbers: 2048, // R11
34315                         outputs: []outputInfo{
34316                                 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
34317                         },
34318                 },
34319         },
34320         {
34321                 name:         "AND",
34322                 argLen:       2,
34323                 commutative:  true,
34324                 clobberFlags: true,
34325                 asm:          s390x.AAND,
34326                 reg: regInfo{
34327                         inputs: []inputInfo{
34328                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34329                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34330                         },
34331                         outputs: []outputInfo{
34332                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34333                         },
34334                 },
34335         },
34336         {
34337                 name:         "ANDW",
34338                 argLen:       2,
34339                 commutative:  true,
34340                 clobberFlags: true,
34341                 asm:          s390x.AANDW,
34342                 reg: regInfo{
34343                         inputs: []inputInfo{
34344                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34345                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34346                         },
34347                         outputs: []outputInfo{
34348                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34349                         },
34350                 },
34351         },
34352         {
34353                 name:         "ANDconst",
34354                 auxType:      auxInt64,
34355                 argLen:       1,
34356                 resultInArg0: true,
34357                 clobberFlags: true,
34358                 asm:          s390x.AAND,
34359                 reg: regInfo{
34360                         inputs: []inputInfo{
34361                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34362                         },
34363                         outputs: []outputInfo{
34364                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34365                         },
34366                 },
34367         },
34368         {
34369                 name:         "ANDWconst",
34370                 auxType:      auxInt32,
34371                 argLen:       1,
34372                 resultInArg0: true,
34373                 clobberFlags: true,
34374                 asm:          s390x.AANDW,
34375                 reg: regInfo{
34376                         inputs: []inputInfo{
34377                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34378                         },
34379                         outputs: []outputInfo{
34380                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34381                         },
34382                 },
34383         },
34384         {
34385                 name:           "ANDload",
34386                 auxType:        auxSymOff,
34387                 argLen:         3,
34388                 resultInArg0:   true,
34389                 clobberFlags:   true,
34390                 faultOnNilArg1: true,
34391                 symEffect:      SymRead,
34392                 asm:            s390x.AAND,
34393                 reg: regInfo{
34394                         inputs: []inputInfo{
34395                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34396                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34397                         },
34398                         outputs: []outputInfo{
34399                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34400                         },
34401                 },
34402         },
34403         {
34404                 name:           "ANDWload",
34405                 auxType:        auxSymOff,
34406                 argLen:         3,
34407                 resultInArg0:   true,
34408                 clobberFlags:   true,
34409                 faultOnNilArg1: true,
34410                 symEffect:      SymRead,
34411                 asm:            s390x.AANDW,
34412                 reg: regInfo{
34413                         inputs: []inputInfo{
34414                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34415                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34416                         },
34417                         outputs: []outputInfo{
34418                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34419                         },
34420                 },
34421         },
34422         {
34423                 name:         "OR",
34424                 argLen:       2,
34425                 commutative:  true,
34426                 clobberFlags: true,
34427                 asm:          s390x.AOR,
34428                 reg: regInfo{
34429                         inputs: []inputInfo{
34430                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34431                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34432                         },
34433                         outputs: []outputInfo{
34434                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34435                         },
34436                 },
34437         },
34438         {
34439                 name:         "ORW",
34440                 argLen:       2,
34441                 commutative:  true,
34442                 clobberFlags: true,
34443                 asm:          s390x.AORW,
34444                 reg: regInfo{
34445                         inputs: []inputInfo{
34446                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34447                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34448                         },
34449                         outputs: []outputInfo{
34450                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34451                         },
34452                 },
34453         },
34454         {
34455                 name:         "ORconst",
34456                 auxType:      auxInt64,
34457                 argLen:       1,
34458                 resultInArg0: true,
34459                 clobberFlags: true,
34460                 asm:          s390x.AOR,
34461                 reg: regInfo{
34462                         inputs: []inputInfo{
34463                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34464                         },
34465                         outputs: []outputInfo{
34466                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34467                         },
34468                 },
34469         },
34470         {
34471                 name:         "ORWconst",
34472                 auxType:      auxInt32,
34473                 argLen:       1,
34474                 resultInArg0: true,
34475                 clobberFlags: true,
34476                 asm:          s390x.AORW,
34477                 reg: regInfo{
34478                         inputs: []inputInfo{
34479                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34480                         },
34481                         outputs: []outputInfo{
34482                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34483                         },
34484                 },
34485         },
34486         {
34487                 name:           "ORload",
34488                 auxType:        auxSymOff,
34489                 argLen:         3,
34490                 resultInArg0:   true,
34491                 clobberFlags:   true,
34492                 faultOnNilArg1: true,
34493                 symEffect:      SymRead,
34494                 asm:            s390x.AOR,
34495                 reg: regInfo{
34496                         inputs: []inputInfo{
34497                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34498                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34499                         },
34500                         outputs: []outputInfo{
34501                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34502                         },
34503                 },
34504         },
34505         {
34506                 name:           "ORWload",
34507                 auxType:        auxSymOff,
34508                 argLen:         3,
34509                 resultInArg0:   true,
34510                 clobberFlags:   true,
34511                 faultOnNilArg1: true,
34512                 symEffect:      SymRead,
34513                 asm:            s390x.AORW,
34514                 reg: regInfo{
34515                         inputs: []inputInfo{
34516                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34517                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34518                         },
34519                         outputs: []outputInfo{
34520                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34521                         },
34522                 },
34523         },
34524         {
34525                 name:         "XOR",
34526                 argLen:       2,
34527                 commutative:  true,
34528                 clobberFlags: true,
34529                 asm:          s390x.AXOR,
34530                 reg: regInfo{
34531                         inputs: []inputInfo{
34532                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34533                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34534                         },
34535                         outputs: []outputInfo{
34536                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34537                         },
34538                 },
34539         },
34540         {
34541                 name:         "XORW",
34542                 argLen:       2,
34543                 commutative:  true,
34544                 clobberFlags: true,
34545                 asm:          s390x.AXORW,
34546                 reg: regInfo{
34547                         inputs: []inputInfo{
34548                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34549                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34550                         },
34551                         outputs: []outputInfo{
34552                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34553                         },
34554                 },
34555         },
34556         {
34557                 name:         "XORconst",
34558                 auxType:      auxInt64,
34559                 argLen:       1,
34560                 resultInArg0: true,
34561                 clobberFlags: true,
34562                 asm:          s390x.AXOR,
34563                 reg: regInfo{
34564                         inputs: []inputInfo{
34565                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34566                         },
34567                         outputs: []outputInfo{
34568                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34569                         },
34570                 },
34571         },
34572         {
34573                 name:         "XORWconst",
34574                 auxType:      auxInt32,
34575                 argLen:       1,
34576                 resultInArg0: true,
34577                 clobberFlags: true,
34578                 asm:          s390x.AXORW,
34579                 reg: regInfo{
34580                         inputs: []inputInfo{
34581                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34582                         },
34583                         outputs: []outputInfo{
34584                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34585                         },
34586                 },
34587         },
34588         {
34589                 name:           "XORload",
34590                 auxType:        auxSymOff,
34591                 argLen:         3,
34592                 resultInArg0:   true,
34593                 clobberFlags:   true,
34594                 faultOnNilArg1: true,
34595                 symEffect:      SymRead,
34596                 asm:            s390x.AXOR,
34597                 reg: regInfo{
34598                         inputs: []inputInfo{
34599                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34600                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34601                         },
34602                         outputs: []outputInfo{
34603                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34604                         },
34605                 },
34606         },
34607         {
34608                 name:           "XORWload",
34609                 auxType:        auxSymOff,
34610                 argLen:         3,
34611                 resultInArg0:   true,
34612                 clobberFlags:   true,
34613                 faultOnNilArg1: true,
34614                 symEffect:      SymRead,
34615                 asm:            s390x.AXORW,
34616                 reg: regInfo{
34617                         inputs: []inputInfo{
34618                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34619                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34620                         },
34621                         outputs: []outputInfo{
34622                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34623                         },
34624                 },
34625         },
34626         {
34627                 name:        "ADDC",
34628                 argLen:      2,
34629                 commutative: true,
34630                 asm:         s390x.AADDC,
34631                 reg: regInfo{
34632                         inputs: []inputInfo{
34633                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34634                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34635                         },
34636                         outputs: []outputInfo{
34637                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34638                         },
34639                 },
34640         },
34641         {
34642                 name:    "ADDCconst",
34643                 auxType: auxInt16,
34644                 argLen:  1,
34645                 asm:     s390x.AADDC,
34646                 reg: regInfo{
34647                         inputs: []inputInfo{
34648                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34649                         },
34650                         outputs: []outputInfo{
34651                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34652                         },
34653                 },
34654         },
34655         {
34656                 name:         "ADDE",
34657                 argLen:       3,
34658                 commutative:  true,
34659                 resultInArg0: true,
34660                 asm:          s390x.AADDE,
34661                 reg: regInfo{
34662                         inputs: []inputInfo{
34663                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34664                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34665                         },
34666                         outputs: []outputInfo{
34667                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34668                         },
34669                 },
34670         },
34671         {
34672                 name:   "SUBC",
34673                 argLen: 2,
34674                 asm:    s390x.ASUBC,
34675                 reg: regInfo{
34676                         inputs: []inputInfo{
34677                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34678                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34679                         },
34680                         outputs: []outputInfo{
34681                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34682                         },
34683                 },
34684         },
34685         {
34686                 name:         "SUBE",
34687                 argLen:       3,
34688                 resultInArg0: true,
34689                 asm:          s390x.ASUBE,
34690                 reg: regInfo{
34691                         inputs: []inputInfo{
34692                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34693                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34694                         },
34695                         outputs: []outputInfo{
34696                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34697                         },
34698                 },
34699         },
34700         {
34701                 name:   "CMP",
34702                 argLen: 2,
34703                 asm:    s390x.ACMP,
34704                 reg: regInfo{
34705                         inputs: []inputInfo{
34706                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34707                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34708                         },
34709                 },
34710         },
34711         {
34712                 name:   "CMPW",
34713                 argLen: 2,
34714                 asm:    s390x.ACMPW,
34715                 reg: regInfo{
34716                         inputs: []inputInfo{
34717                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34718                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34719                         },
34720                 },
34721         },
34722         {
34723                 name:   "CMPU",
34724                 argLen: 2,
34725                 asm:    s390x.ACMPU,
34726                 reg: regInfo{
34727                         inputs: []inputInfo{
34728                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34729                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34730                         },
34731                 },
34732         },
34733         {
34734                 name:   "CMPWU",
34735                 argLen: 2,
34736                 asm:    s390x.ACMPWU,
34737                 reg: regInfo{
34738                         inputs: []inputInfo{
34739                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34740                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34741                         },
34742                 },
34743         },
34744         {
34745                 name:    "CMPconst",
34746                 auxType: auxInt32,
34747                 argLen:  1,
34748                 asm:     s390x.ACMP,
34749                 reg: regInfo{
34750                         inputs: []inputInfo{
34751                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34752                         },
34753                 },
34754         },
34755         {
34756                 name:    "CMPWconst",
34757                 auxType: auxInt32,
34758                 argLen:  1,
34759                 asm:     s390x.ACMPW,
34760                 reg: regInfo{
34761                         inputs: []inputInfo{
34762                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34763                         },
34764                 },
34765         },
34766         {
34767                 name:    "CMPUconst",
34768                 auxType: auxInt32,
34769                 argLen:  1,
34770                 asm:     s390x.ACMPU,
34771                 reg: regInfo{
34772                         inputs: []inputInfo{
34773                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34774                         },
34775                 },
34776         },
34777         {
34778                 name:    "CMPWUconst",
34779                 auxType: auxInt32,
34780                 argLen:  1,
34781                 asm:     s390x.ACMPWU,
34782                 reg: regInfo{
34783                         inputs: []inputInfo{
34784                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
34785                         },
34786                 },
34787         },
34788         {
34789                 name:   "FCMPS",
34790                 argLen: 2,
34791                 asm:    s390x.ACEBR,
34792                 reg: regInfo{
34793                         inputs: []inputInfo{
34794                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34795                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34796                         },
34797                 },
34798         },
34799         {
34800                 name:   "FCMP",
34801                 argLen: 2,
34802                 asm:    s390x.AFCMPU,
34803                 reg: regInfo{
34804                         inputs: []inputInfo{
34805                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34806                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34807                         },
34808                 },
34809         },
34810         {
34811                 name:   "LTDBR",
34812                 argLen: 1,
34813                 asm:    s390x.ALTDBR,
34814                 reg: regInfo{
34815                         inputs: []inputInfo{
34816                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34817                         },
34818                 },
34819         },
34820         {
34821                 name:   "LTEBR",
34822                 argLen: 1,
34823                 asm:    s390x.ALTEBR,
34824                 reg: regInfo{
34825                         inputs: []inputInfo{
34826                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34827                         },
34828                 },
34829         },
34830         {
34831                 name:   "SLD",
34832                 argLen: 2,
34833                 asm:    s390x.ASLD,
34834                 reg: regInfo{
34835                         inputs: []inputInfo{
34836                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34837                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34838                         },
34839                         outputs: []outputInfo{
34840                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34841                         },
34842                 },
34843         },
34844         {
34845                 name:   "SLW",
34846                 argLen: 2,
34847                 asm:    s390x.ASLW,
34848                 reg: regInfo{
34849                         inputs: []inputInfo{
34850                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34851                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34852                         },
34853                         outputs: []outputInfo{
34854                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34855                         },
34856                 },
34857         },
34858         {
34859                 name:    "SLDconst",
34860                 auxType: auxUInt8,
34861                 argLen:  1,
34862                 asm:     s390x.ASLD,
34863                 reg: regInfo{
34864                         inputs: []inputInfo{
34865                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34866                         },
34867                         outputs: []outputInfo{
34868                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34869                         },
34870                 },
34871         },
34872         {
34873                 name:    "SLWconst",
34874                 auxType: auxUInt8,
34875                 argLen:  1,
34876                 asm:     s390x.ASLW,
34877                 reg: regInfo{
34878                         inputs: []inputInfo{
34879                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34880                         },
34881                         outputs: []outputInfo{
34882                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34883                         },
34884                 },
34885         },
34886         {
34887                 name:   "SRD",
34888                 argLen: 2,
34889                 asm:    s390x.ASRD,
34890                 reg: regInfo{
34891                         inputs: []inputInfo{
34892                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34893                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34894                         },
34895                         outputs: []outputInfo{
34896                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34897                         },
34898                 },
34899         },
34900         {
34901                 name:   "SRW",
34902                 argLen: 2,
34903                 asm:    s390x.ASRW,
34904                 reg: regInfo{
34905                         inputs: []inputInfo{
34906                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34907                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34908                         },
34909                         outputs: []outputInfo{
34910                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34911                         },
34912                 },
34913         },
34914         {
34915                 name:    "SRDconst",
34916                 auxType: auxUInt8,
34917                 argLen:  1,
34918                 asm:     s390x.ASRD,
34919                 reg: regInfo{
34920                         inputs: []inputInfo{
34921                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34922                         },
34923                         outputs: []outputInfo{
34924                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34925                         },
34926                 },
34927         },
34928         {
34929                 name:    "SRWconst",
34930                 auxType: auxUInt8,
34931                 argLen:  1,
34932                 asm:     s390x.ASRW,
34933                 reg: regInfo{
34934                         inputs: []inputInfo{
34935                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34936                         },
34937                         outputs: []outputInfo{
34938                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34939                         },
34940                 },
34941         },
34942         {
34943                 name:         "SRAD",
34944                 argLen:       2,
34945                 clobberFlags: true,
34946                 asm:          s390x.ASRAD,
34947                 reg: regInfo{
34948                         inputs: []inputInfo{
34949                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34950                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34951                         },
34952                         outputs: []outputInfo{
34953                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34954                         },
34955                 },
34956         },
34957         {
34958                 name:         "SRAW",
34959                 argLen:       2,
34960                 clobberFlags: true,
34961                 asm:          s390x.ASRAW,
34962                 reg: regInfo{
34963                         inputs: []inputInfo{
34964                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34965                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34966                         },
34967                         outputs: []outputInfo{
34968                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34969                         },
34970                 },
34971         },
34972         {
34973                 name:         "SRADconst",
34974                 auxType:      auxUInt8,
34975                 argLen:       1,
34976                 clobberFlags: true,
34977                 asm:          s390x.ASRAD,
34978                 reg: regInfo{
34979                         inputs: []inputInfo{
34980                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34981                         },
34982                         outputs: []outputInfo{
34983                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34984                         },
34985                 },
34986         },
34987         {
34988                 name:         "SRAWconst",
34989                 auxType:      auxUInt8,
34990                 argLen:       1,
34991                 clobberFlags: true,
34992                 asm:          s390x.ASRAW,
34993                 reg: regInfo{
34994                         inputs: []inputInfo{
34995                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34996                         },
34997                         outputs: []outputInfo{
34998                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
34999                         },
35000                 },
35001         },
35002         {
35003                 name:   "RLLG",
35004                 argLen: 2,
35005                 asm:    s390x.ARLLG,
35006                 reg: regInfo{
35007                         inputs: []inputInfo{
35008                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35009                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35010                         },
35011                         outputs: []outputInfo{
35012                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35013                         },
35014                 },
35015         },
35016         {
35017                 name:   "RLL",
35018                 argLen: 2,
35019                 asm:    s390x.ARLL,
35020                 reg: regInfo{
35021                         inputs: []inputInfo{
35022                                 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35023                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35024                         },
35025                         outputs: []outputInfo{
35026                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35027                         },
35028                 },
35029         },
35030         {
35031                 name:    "RLLconst",
35032                 auxType: auxUInt8,
35033                 argLen:  1,
35034                 asm:     s390x.ARLL,
35035                 reg: regInfo{
35036                         inputs: []inputInfo{
35037                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35038                         },
35039                         outputs: []outputInfo{
35040                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35041                         },
35042                 },
35043         },
35044         {
35045                 name:         "RXSBG",
35046                 auxType:      auxS390XRotateParams,
35047                 argLen:       2,
35048                 resultInArg0: true,
35049                 clobberFlags: true,
35050                 asm:          s390x.ARXSBG,
35051                 reg: regInfo{
35052                         inputs: []inputInfo{
35053                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35054                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35055                         },
35056                         outputs: []outputInfo{
35057                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35058                         },
35059                 },
35060         },
35061         {
35062                 name:         "RISBGZ",
35063                 auxType:      auxS390XRotateParams,
35064                 argLen:       1,
35065                 clobberFlags: true,
35066                 asm:          s390x.ARISBGZ,
35067                 reg: regInfo{
35068                         inputs: []inputInfo{
35069                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35070                         },
35071                         outputs: []outputInfo{
35072                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35073                         },
35074                 },
35075         },
35076         {
35077                 name:         "NEG",
35078                 argLen:       1,
35079                 clobberFlags: true,
35080                 asm:          s390x.ANEG,
35081                 reg: regInfo{
35082                         inputs: []inputInfo{
35083                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35084                         },
35085                         outputs: []outputInfo{
35086                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35087                         },
35088                 },
35089         },
35090         {
35091                 name:         "NEGW",
35092                 argLen:       1,
35093                 clobberFlags: true,
35094                 asm:          s390x.ANEGW,
35095                 reg: regInfo{
35096                         inputs: []inputInfo{
35097                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35098                         },
35099                         outputs: []outputInfo{
35100                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35101                         },
35102                 },
35103         },
35104         {
35105                 name:         "NOT",
35106                 argLen:       1,
35107                 resultInArg0: true,
35108                 clobberFlags: true,
35109                 reg: regInfo{
35110                         inputs: []inputInfo{
35111                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35112                         },
35113                         outputs: []outputInfo{
35114                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35115                         },
35116                 },
35117         },
35118         {
35119                 name:         "NOTW",
35120                 argLen:       1,
35121                 resultInArg0: true,
35122                 clobberFlags: true,
35123                 reg: regInfo{
35124                         inputs: []inputInfo{
35125                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35126                         },
35127                         outputs: []outputInfo{
35128                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35129                         },
35130                 },
35131         },
35132         {
35133                 name:   "FSQRT",
35134                 argLen: 1,
35135                 asm:    s390x.AFSQRT,
35136                 reg: regInfo{
35137                         inputs: []inputInfo{
35138                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35139                         },
35140                         outputs: []outputInfo{
35141                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35142                         },
35143                 },
35144         },
35145         {
35146                 name:   "FSQRTS",
35147                 argLen: 1,
35148                 asm:    s390x.AFSQRTS,
35149                 reg: regInfo{
35150                         inputs: []inputInfo{
35151                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35152                         },
35153                         outputs: []outputInfo{
35154                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35155                         },
35156                 },
35157         },
35158         {
35159                 name:         "LOCGR",
35160                 auxType:      auxS390XCCMask,
35161                 argLen:       3,
35162                 resultInArg0: true,
35163                 asm:          s390x.ALOCGR,
35164                 reg: regInfo{
35165                         inputs: []inputInfo{
35166                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35167                                 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35168                         },
35169                         outputs: []outputInfo{
35170                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35171                         },
35172                 },
35173         },
35174         {
35175                 name:   "MOVBreg",
35176                 argLen: 1,
35177                 asm:    s390x.AMOVB,
35178                 reg: regInfo{
35179                         inputs: []inputInfo{
35180                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35181                         },
35182                         outputs: []outputInfo{
35183                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35184                         },
35185                 },
35186         },
35187         {
35188                 name:   "MOVBZreg",
35189                 argLen: 1,
35190                 asm:    s390x.AMOVBZ,
35191                 reg: regInfo{
35192                         inputs: []inputInfo{
35193                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35194                         },
35195                         outputs: []outputInfo{
35196                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35197                         },
35198                 },
35199         },
35200         {
35201                 name:   "MOVHreg",
35202                 argLen: 1,
35203                 asm:    s390x.AMOVH,
35204                 reg: regInfo{
35205                         inputs: []inputInfo{
35206                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35207                         },
35208                         outputs: []outputInfo{
35209                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35210                         },
35211                 },
35212         },
35213         {
35214                 name:   "MOVHZreg",
35215                 argLen: 1,
35216                 asm:    s390x.AMOVHZ,
35217                 reg: regInfo{
35218                         inputs: []inputInfo{
35219                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35220                         },
35221                         outputs: []outputInfo{
35222                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35223                         },
35224                 },
35225         },
35226         {
35227                 name:   "MOVWreg",
35228                 argLen: 1,
35229                 asm:    s390x.AMOVW,
35230                 reg: regInfo{
35231                         inputs: []inputInfo{
35232                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35233                         },
35234                         outputs: []outputInfo{
35235                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35236                         },
35237                 },
35238         },
35239         {
35240                 name:   "MOVWZreg",
35241                 argLen: 1,
35242                 asm:    s390x.AMOVWZ,
35243                 reg: regInfo{
35244                         inputs: []inputInfo{
35245                                 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35246                         },
35247                         outputs: []outputInfo{
35248                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35249                         },
35250                 },
35251         },
35252         {
35253                 name:              "MOVDconst",
35254                 auxType:           auxInt64,
35255                 argLen:            0,
35256                 rematerializeable: true,
35257                 asm:               s390x.AMOVD,
35258                 reg: regInfo{
35259                         outputs: []outputInfo{
35260                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35261                         },
35262                 },
35263         },
35264         {
35265                 name:   "LDGR",
35266                 argLen: 1,
35267                 asm:    s390x.ALDGR,
35268                 reg: regInfo{
35269                         inputs: []inputInfo{
35270                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35271                         },
35272                         outputs: []outputInfo{
35273                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35274                         },
35275                 },
35276         },
35277         {
35278                 name:   "LGDR",
35279                 argLen: 1,
35280                 asm:    s390x.ALGDR,
35281                 reg: regInfo{
35282                         inputs: []inputInfo{
35283                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35284                         },
35285                         outputs: []outputInfo{
35286                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35287                         },
35288                 },
35289         },
35290         {
35291                 name:         "CFDBRA",
35292                 argLen:       1,
35293                 clobberFlags: true,
35294                 asm:          s390x.ACFDBRA,
35295                 reg: regInfo{
35296                         inputs: []inputInfo{
35297                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35298                         },
35299                         outputs: []outputInfo{
35300                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35301                         },
35302                 },
35303         },
35304         {
35305                 name:         "CGDBRA",
35306                 argLen:       1,
35307                 clobberFlags: true,
35308                 asm:          s390x.ACGDBRA,
35309                 reg: regInfo{
35310                         inputs: []inputInfo{
35311                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35312                         },
35313                         outputs: []outputInfo{
35314                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35315                         },
35316                 },
35317         },
35318         {
35319                 name:         "CFEBRA",
35320                 argLen:       1,
35321                 clobberFlags: true,
35322                 asm:          s390x.ACFEBRA,
35323                 reg: regInfo{
35324                         inputs: []inputInfo{
35325                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35326                         },
35327                         outputs: []outputInfo{
35328                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35329                         },
35330                 },
35331         },
35332         {
35333                 name:         "CGEBRA",
35334                 argLen:       1,
35335                 clobberFlags: true,
35336                 asm:          s390x.ACGEBRA,
35337                 reg: regInfo{
35338                         inputs: []inputInfo{
35339                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35340                         },
35341                         outputs: []outputInfo{
35342                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35343                         },
35344                 },
35345         },
35346         {
35347                 name:         "CEFBRA",
35348                 argLen:       1,
35349                 clobberFlags: true,
35350                 asm:          s390x.ACEFBRA,
35351                 reg: regInfo{
35352                         inputs: []inputInfo{
35353                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35354                         },
35355                         outputs: []outputInfo{
35356                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35357                         },
35358                 },
35359         },
35360         {
35361                 name:         "CDFBRA",
35362                 argLen:       1,
35363                 clobberFlags: true,
35364                 asm:          s390x.ACDFBRA,
35365                 reg: regInfo{
35366                         inputs: []inputInfo{
35367                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35368                         },
35369                         outputs: []outputInfo{
35370                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35371                         },
35372                 },
35373         },
35374         {
35375                 name:         "CEGBRA",
35376                 argLen:       1,
35377                 clobberFlags: true,
35378                 asm:          s390x.ACEGBRA,
35379                 reg: regInfo{
35380                         inputs: []inputInfo{
35381                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35382                         },
35383                         outputs: []outputInfo{
35384                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35385                         },
35386                 },
35387         },
35388         {
35389                 name:         "CDGBRA",
35390                 argLen:       1,
35391                 clobberFlags: true,
35392                 asm:          s390x.ACDGBRA,
35393                 reg: regInfo{
35394                         inputs: []inputInfo{
35395                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35396                         },
35397                         outputs: []outputInfo{
35398                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35399                         },
35400                 },
35401         },
35402         {
35403                 name:         "CLFEBR",
35404                 argLen:       1,
35405                 clobberFlags: true,
35406                 asm:          s390x.ACLFEBR,
35407                 reg: regInfo{
35408                         inputs: []inputInfo{
35409                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35410                         },
35411                         outputs: []outputInfo{
35412                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35413                         },
35414                 },
35415         },
35416         {
35417                 name:         "CLFDBR",
35418                 argLen:       1,
35419                 clobberFlags: true,
35420                 asm:          s390x.ACLFDBR,
35421                 reg: regInfo{
35422                         inputs: []inputInfo{
35423                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35424                         },
35425                         outputs: []outputInfo{
35426                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35427                         },
35428                 },
35429         },
35430         {
35431                 name:         "CLGEBR",
35432                 argLen:       1,
35433                 clobberFlags: true,
35434                 asm:          s390x.ACLGEBR,
35435                 reg: regInfo{
35436                         inputs: []inputInfo{
35437                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35438                         },
35439                         outputs: []outputInfo{
35440                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35441                         },
35442                 },
35443         },
35444         {
35445                 name:         "CLGDBR",
35446                 argLen:       1,
35447                 clobberFlags: true,
35448                 asm:          s390x.ACLGDBR,
35449                 reg: regInfo{
35450                         inputs: []inputInfo{
35451                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35452                         },
35453                         outputs: []outputInfo{
35454                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35455                         },
35456                 },
35457         },
35458         {
35459                 name:         "CELFBR",
35460                 argLen:       1,
35461                 clobberFlags: true,
35462                 asm:          s390x.ACELFBR,
35463                 reg: regInfo{
35464                         inputs: []inputInfo{
35465                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35466                         },
35467                         outputs: []outputInfo{
35468                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35469                         },
35470                 },
35471         },
35472         {
35473                 name:         "CDLFBR",
35474                 argLen:       1,
35475                 clobberFlags: true,
35476                 asm:          s390x.ACDLFBR,
35477                 reg: regInfo{
35478                         inputs: []inputInfo{
35479                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35480                         },
35481                         outputs: []outputInfo{
35482                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35483                         },
35484                 },
35485         },
35486         {
35487                 name:         "CELGBR",
35488                 argLen:       1,
35489                 clobberFlags: true,
35490                 asm:          s390x.ACELGBR,
35491                 reg: regInfo{
35492                         inputs: []inputInfo{
35493                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35494                         },
35495                         outputs: []outputInfo{
35496                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35497                         },
35498                 },
35499         },
35500         {
35501                 name:         "CDLGBR",
35502                 argLen:       1,
35503                 clobberFlags: true,
35504                 asm:          s390x.ACDLGBR,
35505                 reg: regInfo{
35506                         inputs: []inputInfo{
35507                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35508                         },
35509                         outputs: []outputInfo{
35510                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35511                         },
35512                 },
35513         },
35514         {
35515                 name:   "LEDBR",
35516                 argLen: 1,
35517                 asm:    s390x.ALEDBR,
35518                 reg: regInfo{
35519                         inputs: []inputInfo{
35520                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35521                         },
35522                         outputs: []outputInfo{
35523                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35524                         },
35525                 },
35526         },
35527         {
35528                 name:   "LDEBR",
35529                 argLen: 1,
35530                 asm:    s390x.ALDEBR,
35531                 reg: regInfo{
35532                         inputs: []inputInfo{
35533                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35534                         },
35535                         outputs: []outputInfo{
35536                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
35537                         },
35538                 },
35539         },
35540         {
35541                 name:              "MOVDaddr",
35542                 auxType:           auxSymOff,
35543                 argLen:            1,
35544                 rematerializeable: true,
35545                 symEffect:         SymAddr,
35546                 reg: regInfo{
35547                         inputs: []inputInfo{
35548                                 {0, 4295000064}, // SP SB
35549                         },
35550                         outputs: []outputInfo{
35551                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35552                         },
35553                 },
35554         },
35555         {
35556                 name:      "MOVDaddridx",
35557                 auxType:   auxSymOff,
35558                 argLen:    2,
35559                 symEffect: SymAddr,
35560                 reg: regInfo{
35561                         inputs: []inputInfo{
35562                                 {0, 4295000064}, // SP SB
35563                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35564                         },
35565                         outputs: []outputInfo{
35566                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35567                         },
35568                 },
35569         },
35570         {
35571                 name:           "MOVBZload",
35572                 auxType:        auxSymOff,
35573                 argLen:         2,
35574                 faultOnNilArg0: true,
35575                 symEffect:      SymRead,
35576                 asm:            s390x.AMOVBZ,
35577                 reg: regInfo{
35578                         inputs: []inputInfo{
35579                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35580                         },
35581                         outputs: []outputInfo{
35582                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35583                         },
35584                 },
35585         },
35586         {
35587                 name:           "MOVBload",
35588                 auxType:        auxSymOff,
35589                 argLen:         2,
35590                 faultOnNilArg0: true,
35591                 symEffect:      SymRead,
35592                 asm:            s390x.AMOVB,
35593                 reg: regInfo{
35594                         inputs: []inputInfo{
35595                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35596                         },
35597                         outputs: []outputInfo{
35598                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35599                         },
35600                 },
35601         },
35602         {
35603                 name:           "MOVHZload",
35604                 auxType:        auxSymOff,
35605                 argLen:         2,
35606                 faultOnNilArg0: true,
35607                 symEffect:      SymRead,
35608                 asm:            s390x.AMOVHZ,
35609                 reg: regInfo{
35610                         inputs: []inputInfo{
35611                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35612                         },
35613                         outputs: []outputInfo{
35614                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35615                         },
35616                 },
35617         },
35618         {
35619                 name:           "MOVHload",
35620                 auxType:        auxSymOff,
35621                 argLen:         2,
35622                 faultOnNilArg0: true,
35623                 symEffect:      SymRead,
35624                 asm:            s390x.AMOVH,
35625                 reg: regInfo{
35626                         inputs: []inputInfo{
35627                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35628                         },
35629                         outputs: []outputInfo{
35630                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35631                         },
35632                 },
35633         },
35634         {
35635                 name:           "MOVWZload",
35636                 auxType:        auxSymOff,
35637                 argLen:         2,
35638                 faultOnNilArg0: true,
35639                 symEffect:      SymRead,
35640                 asm:            s390x.AMOVWZ,
35641                 reg: regInfo{
35642                         inputs: []inputInfo{
35643                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35644                         },
35645                         outputs: []outputInfo{
35646                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35647                         },
35648                 },
35649         },
35650         {
35651                 name:           "MOVWload",
35652                 auxType:        auxSymOff,
35653                 argLen:         2,
35654                 faultOnNilArg0: true,
35655                 symEffect:      SymRead,
35656                 asm:            s390x.AMOVW,
35657                 reg: regInfo{
35658                         inputs: []inputInfo{
35659                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35660                         },
35661                         outputs: []outputInfo{
35662                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35663                         },
35664                 },
35665         },
35666         {
35667                 name:           "MOVDload",
35668                 auxType:        auxSymOff,
35669                 argLen:         2,
35670                 faultOnNilArg0: true,
35671                 symEffect:      SymRead,
35672                 asm:            s390x.AMOVD,
35673                 reg: regInfo{
35674                         inputs: []inputInfo{
35675                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35676                         },
35677                         outputs: []outputInfo{
35678                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35679                         },
35680                 },
35681         },
35682         {
35683                 name:   "MOVWBR",
35684                 argLen: 1,
35685                 asm:    s390x.AMOVWBR,
35686                 reg: regInfo{
35687                         inputs: []inputInfo{
35688                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35689                         },
35690                         outputs: []outputInfo{
35691                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35692                         },
35693                 },
35694         },
35695         {
35696                 name:   "MOVDBR",
35697                 argLen: 1,
35698                 asm:    s390x.AMOVDBR,
35699                 reg: regInfo{
35700                         inputs: []inputInfo{
35701                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35702                         },
35703                         outputs: []outputInfo{
35704                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35705                         },
35706                 },
35707         },
35708         {
35709                 name:           "MOVHBRload",
35710                 auxType:        auxSymOff,
35711                 argLen:         2,
35712                 faultOnNilArg0: true,
35713                 symEffect:      SymRead,
35714                 asm:            s390x.AMOVHBR,
35715                 reg: regInfo{
35716                         inputs: []inputInfo{
35717                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35718                         },
35719                         outputs: []outputInfo{
35720                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35721                         },
35722                 },
35723         },
35724         {
35725                 name:           "MOVWBRload",
35726                 auxType:        auxSymOff,
35727                 argLen:         2,
35728                 faultOnNilArg0: true,
35729                 symEffect:      SymRead,
35730                 asm:            s390x.AMOVWBR,
35731                 reg: regInfo{
35732                         inputs: []inputInfo{
35733                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35734                         },
35735                         outputs: []outputInfo{
35736                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35737                         },
35738                 },
35739         },
35740         {
35741                 name:           "MOVDBRload",
35742                 auxType:        auxSymOff,
35743                 argLen:         2,
35744                 faultOnNilArg0: true,
35745                 symEffect:      SymRead,
35746                 asm:            s390x.AMOVDBR,
35747                 reg: regInfo{
35748                         inputs: []inputInfo{
35749                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35750                         },
35751                         outputs: []outputInfo{
35752                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35753                         },
35754                 },
35755         },
35756         {
35757                 name:           "MOVBstore",
35758                 auxType:        auxSymOff,
35759                 argLen:         3,
35760                 faultOnNilArg0: true,
35761                 symEffect:      SymWrite,
35762                 asm:            s390x.AMOVB,
35763                 reg: regInfo{
35764                         inputs: []inputInfo{
35765                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35766                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35767                         },
35768                 },
35769         },
35770         {
35771                 name:           "MOVHstore",
35772                 auxType:        auxSymOff,
35773                 argLen:         3,
35774                 faultOnNilArg0: true,
35775                 symEffect:      SymWrite,
35776                 asm:            s390x.AMOVH,
35777                 reg: regInfo{
35778                         inputs: []inputInfo{
35779                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35780                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35781                         },
35782                 },
35783         },
35784         {
35785                 name:           "MOVWstore",
35786                 auxType:        auxSymOff,
35787                 argLen:         3,
35788                 faultOnNilArg0: true,
35789                 symEffect:      SymWrite,
35790                 asm:            s390x.AMOVW,
35791                 reg: regInfo{
35792                         inputs: []inputInfo{
35793                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35794                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35795                         },
35796                 },
35797         },
35798         {
35799                 name:           "MOVDstore",
35800                 auxType:        auxSymOff,
35801                 argLen:         3,
35802                 faultOnNilArg0: true,
35803                 symEffect:      SymWrite,
35804                 asm:            s390x.AMOVD,
35805                 reg: regInfo{
35806                         inputs: []inputInfo{
35807                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35808                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35809                         },
35810                 },
35811         },
35812         {
35813                 name:           "MOVHBRstore",
35814                 auxType:        auxSymOff,
35815                 argLen:         3,
35816                 faultOnNilArg0: true,
35817                 symEffect:      SymWrite,
35818                 asm:            s390x.AMOVHBR,
35819                 reg: regInfo{
35820                         inputs: []inputInfo{
35821                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35822                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35823                         },
35824                 },
35825         },
35826         {
35827                 name:           "MOVWBRstore",
35828                 auxType:        auxSymOff,
35829                 argLen:         3,
35830                 faultOnNilArg0: true,
35831                 symEffect:      SymWrite,
35832                 asm:            s390x.AMOVWBR,
35833                 reg: regInfo{
35834                         inputs: []inputInfo{
35835                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35836                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35837                         },
35838                 },
35839         },
35840         {
35841                 name:           "MOVDBRstore",
35842                 auxType:        auxSymOff,
35843                 argLen:         3,
35844                 faultOnNilArg0: true,
35845                 symEffect:      SymWrite,
35846                 asm:            s390x.AMOVDBR,
35847                 reg: regInfo{
35848                         inputs: []inputInfo{
35849                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35850                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35851                         },
35852                 },
35853         },
35854         {
35855                 name:           "MVC",
35856                 auxType:        auxSymValAndOff,
35857                 argLen:         3,
35858                 clobberFlags:   true,
35859                 faultOnNilArg0: true,
35860                 faultOnNilArg1: true,
35861                 symEffect:      SymNone,
35862                 asm:            s390x.AMVC,
35863                 reg: regInfo{
35864                         inputs: []inputInfo{
35865                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35866                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35867                         },
35868                 },
35869         },
35870         {
35871                 name:        "MOVBZloadidx",
35872                 auxType:     auxSymOff,
35873                 argLen:      3,
35874                 commutative: true,
35875                 symEffect:   SymRead,
35876                 asm:         s390x.AMOVBZ,
35877                 reg: regInfo{
35878                         inputs: []inputInfo{
35879                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35880                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35881                         },
35882                         outputs: []outputInfo{
35883                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35884                         },
35885                 },
35886         },
35887         {
35888                 name:        "MOVBloadidx",
35889                 auxType:     auxSymOff,
35890                 argLen:      3,
35891                 commutative: true,
35892                 symEffect:   SymRead,
35893                 asm:         s390x.AMOVB,
35894                 reg: regInfo{
35895                         inputs: []inputInfo{
35896                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35897                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35898                         },
35899                         outputs: []outputInfo{
35900                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35901                         },
35902                 },
35903         },
35904         {
35905                 name:        "MOVHZloadidx",
35906                 auxType:     auxSymOff,
35907                 argLen:      3,
35908                 commutative: true,
35909                 symEffect:   SymRead,
35910                 asm:         s390x.AMOVHZ,
35911                 reg: regInfo{
35912                         inputs: []inputInfo{
35913                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35914                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35915                         },
35916                         outputs: []outputInfo{
35917                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35918                         },
35919                 },
35920         },
35921         {
35922                 name:        "MOVHloadidx",
35923                 auxType:     auxSymOff,
35924                 argLen:      3,
35925                 commutative: true,
35926                 symEffect:   SymRead,
35927                 asm:         s390x.AMOVH,
35928                 reg: regInfo{
35929                         inputs: []inputInfo{
35930                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35931                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35932                         },
35933                         outputs: []outputInfo{
35934                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35935                         },
35936                 },
35937         },
35938         {
35939                 name:        "MOVWZloadidx",
35940                 auxType:     auxSymOff,
35941                 argLen:      3,
35942                 commutative: true,
35943                 symEffect:   SymRead,
35944                 asm:         s390x.AMOVWZ,
35945                 reg: regInfo{
35946                         inputs: []inputInfo{
35947                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35948                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35949                         },
35950                         outputs: []outputInfo{
35951                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35952                         },
35953                 },
35954         },
35955         {
35956                 name:        "MOVWloadidx",
35957                 auxType:     auxSymOff,
35958                 argLen:      3,
35959                 commutative: true,
35960                 symEffect:   SymRead,
35961                 asm:         s390x.AMOVW,
35962                 reg: regInfo{
35963                         inputs: []inputInfo{
35964                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35965                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35966                         },
35967                         outputs: []outputInfo{
35968                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35969                         },
35970                 },
35971         },
35972         {
35973                 name:        "MOVDloadidx",
35974                 auxType:     auxSymOff,
35975                 argLen:      3,
35976                 commutative: true,
35977                 symEffect:   SymRead,
35978                 asm:         s390x.AMOVD,
35979                 reg: regInfo{
35980                         inputs: []inputInfo{
35981                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35982                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
35983                         },
35984                         outputs: []outputInfo{
35985                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
35986                         },
35987                 },
35988         },
35989         {
35990                 name:        "MOVHBRloadidx",
35991                 auxType:     auxSymOff,
35992                 argLen:      3,
35993                 commutative: true,
35994                 symEffect:   SymRead,
35995                 asm:         s390x.AMOVHBR,
35996                 reg: regInfo{
35997                         inputs: []inputInfo{
35998                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
35999                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36000                         },
36001                         outputs: []outputInfo{
36002                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36003                         },
36004                 },
36005         },
36006         {
36007                 name:        "MOVWBRloadidx",
36008                 auxType:     auxSymOff,
36009                 argLen:      3,
36010                 commutative: true,
36011                 symEffect:   SymRead,
36012                 asm:         s390x.AMOVWBR,
36013                 reg: regInfo{
36014                         inputs: []inputInfo{
36015                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36016                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36017                         },
36018                         outputs: []outputInfo{
36019                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36020                         },
36021                 },
36022         },
36023         {
36024                 name:        "MOVDBRloadidx",
36025                 auxType:     auxSymOff,
36026                 argLen:      3,
36027                 commutative: true,
36028                 symEffect:   SymRead,
36029                 asm:         s390x.AMOVDBR,
36030                 reg: regInfo{
36031                         inputs: []inputInfo{
36032                                 {1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36033                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36034                         },
36035                         outputs: []outputInfo{
36036                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36037                         },
36038                 },
36039         },
36040         {
36041                 name:        "MOVBstoreidx",
36042                 auxType:     auxSymOff,
36043                 argLen:      4,
36044                 commutative: true,
36045                 symEffect:   SymWrite,
36046                 asm:         s390x.AMOVB,
36047                 reg: regInfo{
36048                         inputs: []inputInfo{
36049                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36050                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36051                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36052                         },
36053                 },
36054         },
36055         {
36056                 name:        "MOVHstoreidx",
36057                 auxType:     auxSymOff,
36058                 argLen:      4,
36059                 commutative: true,
36060                 symEffect:   SymWrite,
36061                 asm:         s390x.AMOVH,
36062                 reg: regInfo{
36063                         inputs: []inputInfo{
36064                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36065                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36066                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36067                         },
36068                 },
36069         },
36070         {
36071                 name:        "MOVWstoreidx",
36072                 auxType:     auxSymOff,
36073                 argLen:      4,
36074                 commutative: true,
36075                 symEffect:   SymWrite,
36076                 asm:         s390x.AMOVW,
36077                 reg: regInfo{
36078                         inputs: []inputInfo{
36079                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36080                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36081                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36082                         },
36083                 },
36084         },
36085         {
36086                 name:        "MOVDstoreidx",
36087                 auxType:     auxSymOff,
36088                 argLen:      4,
36089                 commutative: true,
36090                 symEffect:   SymWrite,
36091                 asm:         s390x.AMOVD,
36092                 reg: regInfo{
36093                         inputs: []inputInfo{
36094                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36095                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36096                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36097                         },
36098                 },
36099         },
36100         {
36101                 name:        "MOVHBRstoreidx",
36102                 auxType:     auxSymOff,
36103                 argLen:      4,
36104                 commutative: true,
36105                 symEffect:   SymWrite,
36106                 asm:         s390x.AMOVHBR,
36107                 reg: regInfo{
36108                         inputs: []inputInfo{
36109                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36110                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36111                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36112                         },
36113                 },
36114         },
36115         {
36116                 name:        "MOVWBRstoreidx",
36117                 auxType:     auxSymOff,
36118                 argLen:      4,
36119                 commutative: true,
36120                 symEffect:   SymWrite,
36121                 asm:         s390x.AMOVWBR,
36122                 reg: regInfo{
36123                         inputs: []inputInfo{
36124                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36125                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36126                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36127                         },
36128                 },
36129         },
36130         {
36131                 name:        "MOVDBRstoreidx",
36132                 auxType:     auxSymOff,
36133                 argLen:      4,
36134                 commutative: true,
36135                 symEffect:   SymWrite,
36136                 asm:         s390x.AMOVDBR,
36137                 reg: regInfo{
36138                         inputs: []inputInfo{
36139                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36140                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36141                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36142                         },
36143                 },
36144         },
36145         {
36146                 name:           "MOVBstoreconst",
36147                 auxType:        auxSymValAndOff,
36148                 argLen:         2,
36149                 faultOnNilArg0: true,
36150                 symEffect:      SymWrite,
36151                 asm:            s390x.AMOVB,
36152                 reg: regInfo{
36153                         inputs: []inputInfo{
36154                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36155                         },
36156                 },
36157         },
36158         {
36159                 name:           "MOVHstoreconst",
36160                 auxType:        auxSymValAndOff,
36161                 argLen:         2,
36162                 faultOnNilArg0: true,
36163                 symEffect:      SymWrite,
36164                 asm:            s390x.AMOVH,
36165                 reg: regInfo{
36166                         inputs: []inputInfo{
36167                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36168                         },
36169                 },
36170         },
36171         {
36172                 name:           "MOVWstoreconst",
36173                 auxType:        auxSymValAndOff,
36174                 argLen:         2,
36175                 faultOnNilArg0: true,
36176                 symEffect:      SymWrite,
36177                 asm:            s390x.AMOVW,
36178                 reg: regInfo{
36179                         inputs: []inputInfo{
36180                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36181                         },
36182                 },
36183         },
36184         {
36185                 name:           "MOVDstoreconst",
36186                 auxType:        auxSymValAndOff,
36187                 argLen:         2,
36188                 faultOnNilArg0: true,
36189                 symEffect:      SymWrite,
36190                 asm:            s390x.AMOVD,
36191                 reg: regInfo{
36192                         inputs: []inputInfo{
36193                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36194                         },
36195                 },
36196         },
36197         {
36198                 name:           "CLEAR",
36199                 auxType:        auxSymValAndOff,
36200                 argLen:         2,
36201                 clobberFlags:   true,
36202                 faultOnNilArg0: true,
36203                 symEffect:      SymWrite,
36204                 asm:            s390x.ACLEAR,
36205                 reg: regInfo{
36206                         inputs: []inputInfo{
36207                                 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36208                         },
36209                 },
36210         },
36211         {
36212                 name:         "CALLstatic",
36213                 auxType:      auxCallOff,
36214                 argLen:       1,
36215                 clobberFlags: true,
36216                 call:         true,
36217                 reg: regInfo{
36218                         clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36219                 },
36220         },
36221         {
36222                 name:         "CALLtail",
36223                 auxType:      auxCallOff,
36224                 argLen:       1,
36225                 clobberFlags: true,
36226                 call:         true,
36227                 tailCall:     true,
36228                 reg: regInfo{
36229                         clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36230                 },
36231         },
36232         {
36233                 name:         "CALLclosure",
36234                 auxType:      auxCallOff,
36235                 argLen:       3,
36236                 clobberFlags: true,
36237                 call:         true,
36238                 reg: regInfo{
36239                         inputs: []inputInfo{
36240                                 {1, 4096},  // R12
36241                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36242                         },
36243                         clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36244                 },
36245         },
36246         {
36247                 name:         "CALLinter",
36248                 auxType:      auxCallOff,
36249                 argLen:       2,
36250                 clobberFlags: true,
36251                 call:         true,
36252                 reg: regInfo{
36253                         inputs: []inputInfo{
36254                                 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36255                         },
36256                         clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36257                 },
36258         },
36259         {
36260                 name:   "InvertFlags",
36261                 argLen: 1,
36262                 reg:    regInfo{},
36263         },
36264         {
36265                 name:   "LoweredGetG",
36266                 argLen: 1,
36267                 reg: regInfo{
36268                         outputs: []outputInfo{
36269                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36270                         },
36271                 },
36272         },
36273         {
36274                 name:      "LoweredGetClosurePtr",
36275                 argLen:    0,
36276                 zeroWidth: true,
36277                 reg: regInfo{
36278                         outputs: []outputInfo{
36279                                 {0, 4096}, // R12
36280                         },
36281                 },
36282         },
36283         {
36284                 name:              "LoweredGetCallerSP",
36285                 argLen:            1,
36286                 rematerializeable: true,
36287                 reg: regInfo{
36288                         outputs: []outputInfo{
36289                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36290                         },
36291                 },
36292         },
36293         {
36294                 name:              "LoweredGetCallerPC",
36295                 argLen:            0,
36296                 rematerializeable: true,
36297                 reg: regInfo{
36298                         outputs: []outputInfo{
36299                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36300                         },
36301                 },
36302         },
36303         {
36304                 name:           "LoweredNilCheck",
36305                 argLen:         2,
36306                 clobberFlags:   true,
36307                 nilCheck:       true,
36308                 faultOnNilArg0: true,
36309                 reg: regInfo{
36310                         inputs: []inputInfo{
36311                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36312                         },
36313                 },
36314         },
36315         {
36316                 name:         "LoweredRound32F",
36317                 argLen:       1,
36318                 resultInArg0: true,
36319                 zeroWidth:    true,
36320                 reg: regInfo{
36321                         inputs: []inputInfo{
36322                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36323                         },
36324                         outputs: []outputInfo{
36325                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36326                         },
36327                 },
36328         },
36329         {
36330                 name:         "LoweredRound64F",
36331                 argLen:       1,
36332                 resultInArg0: true,
36333                 zeroWidth:    true,
36334                 reg: regInfo{
36335                         inputs: []inputInfo{
36336                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36337                         },
36338                         outputs: []outputInfo{
36339                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36340                         },
36341                 },
36342         },
36343         {
36344                 name:         "LoweredWB",
36345                 auxType:      auxInt64,
36346                 argLen:       1,
36347                 clobberFlags: true,
36348                 reg: regInfo{
36349                         clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
36350                         outputs: []outputInfo{
36351                                 {0, 512}, // R9
36352                         },
36353                 },
36354         },
36355         {
36356                 name:    "LoweredPanicBoundsA",
36357                 auxType: auxInt64,
36358                 argLen:  3,
36359                 call:    true,
36360                 reg: regInfo{
36361                         inputs: []inputInfo{
36362                                 {0, 4}, // R2
36363                                 {1, 8}, // R3
36364                         },
36365                 },
36366         },
36367         {
36368                 name:    "LoweredPanicBoundsB",
36369                 auxType: auxInt64,
36370                 argLen:  3,
36371                 call:    true,
36372                 reg: regInfo{
36373                         inputs: []inputInfo{
36374                                 {0, 2}, // R1
36375                                 {1, 4}, // R2
36376                         },
36377                 },
36378         },
36379         {
36380                 name:    "LoweredPanicBoundsC",
36381                 auxType: auxInt64,
36382                 argLen:  3,
36383                 call:    true,
36384                 reg: regInfo{
36385                         inputs: []inputInfo{
36386                                 {0, 1}, // R0
36387                                 {1, 2}, // R1
36388                         },
36389                 },
36390         },
36391         {
36392                 name:   "FlagEQ",
36393                 argLen: 0,
36394                 reg:    regInfo{},
36395         },
36396         {
36397                 name:   "FlagLT",
36398                 argLen: 0,
36399                 reg:    regInfo{},
36400         },
36401         {
36402                 name:   "FlagGT",
36403                 argLen: 0,
36404                 reg:    regInfo{},
36405         },
36406         {
36407                 name:   "FlagOV",
36408                 argLen: 0,
36409                 reg:    regInfo{},
36410         },
36411         {
36412                 name:   "SYNC",
36413                 argLen: 1,
36414                 asm:    s390x.ASYNC,
36415                 reg:    regInfo{},
36416         },
36417         {
36418                 name:           "MOVBZatomicload",
36419                 auxType:        auxSymOff,
36420                 argLen:         2,
36421                 faultOnNilArg0: true,
36422                 symEffect:      SymRead,
36423                 asm:            s390x.AMOVBZ,
36424                 reg: regInfo{
36425                         inputs: []inputInfo{
36426                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36427                         },
36428                         outputs: []outputInfo{
36429                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36430                         },
36431                 },
36432         },
36433         {
36434                 name:           "MOVWZatomicload",
36435                 auxType:        auxSymOff,
36436                 argLen:         2,
36437                 faultOnNilArg0: true,
36438                 symEffect:      SymRead,
36439                 asm:            s390x.AMOVWZ,
36440                 reg: regInfo{
36441                         inputs: []inputInfo{
36442                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36443                         },
36444                         outputs: []outputInfo{
36445                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36446                         },
36447                 },
36448         },
36449         {
36450                 name:           "MOVDatomicload",
36451                 auxType:        auxSymOff,
36452                 argLen:         2,
36453                 faultOnNilArg0: true,
36454                 symEffect:      SymRead,
36455                 asm:            s390x.AMOVD,
36456                 reg: regInfo{
36457                         inputs: []inputInfo{
36458                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36459                         },
36460                         outputs: []outputInfo{
36461                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36462                         },
36463                 },
36464         },
36465         {
36466                 name:           "MOVBatomicstore",
36467                 auxType:        auxSymOff,
36468                 argLen:         3,
36469                 clobberFlags:   true,
36470                 faultOnNilArg0: true,
36471                 hasSideEffects: true,
36472                 symEffect:      SymWrite,
36473                 asm:            s390x.AMOVB,
36474                 reg: regInfo{
36475                         inputs: []inputInfo{
36476                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36477                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36478                         },
36479                 },
36480         },
36481         {
36482                 name:           "MOVWatomicstore",
36483                 auxType:        auxSymOff,
36484                 argLen:         3,
36485                 clobberFlags:   true,
36486                 faultOnNilArg0: true,
36487                 hasSideEffects: true,
36488                 symEffect:      SymWrite,
36489                 asm:            s390x.AMOVW,
36490                 reg: regInfo{
36491                         inputs: []inputInfo{
36492                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36493                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36494                         },
36495                 },
36496         },
36497         {
36498                 name:           "MOVDatomicstore",
36499                 auxType:        auxSymOff,
36500                 argLen:         3,
36501                 clobberFlags:   true,
36502                 faultOnNilArg0: true,
36503                 hasSideEffects: true,
36504                 symEffect:      SymWrite,
36505                 asm:            s390x.AMOVD,
36506                 reg: regInfo{
36507                         inputs: []inputInfo{
36508                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36509                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36510                         },
36511                 },
36512         },
36513         {
36514                 name:           "LAA",
36515                 auxType:        auxSymOff,
36516                 argLen:         3,
36517                 clobberFlags:   true,
36518                 faultOnNilArg0: true,
36519                 hasSideEffects: true,
36520                 symEffect:      SymRdWr,
36521                 asm:            s390x.ALAA,
36522                 reg: regInfo{
36523                         inputs: []inputInfo{
36524                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36525                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36526                         },
36527                         outputs: []outputInfo{
36528                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36529                         },
36530                 },
36531         },
36532         {
36533                 name:           "LAAG",
36534                 auxType:        auxSymOff,
36535                 argLen:         3,
36536                 clobberFlags:   true,
36537                 faultOnNilArg0: true,
36538                 hasSideEffects: true,
36539                 symEffect:      SymRdWr,
36540                 asm:            s390x.ALAAG,
36541                 reg: regInfo{
36542                         inputs: []inputInfo{
36543                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36544                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36545                         },
36546                         outputs: []outputInfo{
36547                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36548                         },
36549                 },
36550         },
36551         {
36552                 name:   "AddTupleFirst32",
36553                 argLen: 2,
36554                 reg:    regInfo{},
36555         },
36556         {
36557                 name:   "AddTupleFirst64",
36558                 argLen: 2,
36559                 reg:    regInfo{},
36560         },
36561         {
36562                 name:           "LAN",
36563                 argLen:         3,
36564                 clobberFlags:   true,
36565                 hasSideEffects: true,
36566                 asm:            s390x.ALAN,
36567                 reg: regInfo{
36568                         inputs: []inputInfo{
36569                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36570                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36571                         },
36572                 },
36573         },
36574         {
36575                 name:           "LANfloor",
36576                 argLen:         3,
36577                 clobberFlags:   true,
36578                 hasSideEffects: true,
36579                 asm:            s390x.ALAN,
36580                 reg: regInfo{
36581                         inputs: []inputInfo{
36582                                 {0, 2},     // R1
36583                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36584                         },
36585                         clobbers: 2, // R1
36586                 },
36587         },
36588         {
36589                 name:           "LAO",
36590                 argLen:         3,
36591                 clobberFlags:   true,
36592                 hasSideEffects: true,
36593                 asm:            s390x.ALAO,
36594                 reg: regInfo{
36595                         inputs: []inputInfo{
36596                                 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
36597                                 {1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36598                         },
36599                 },
36600         },
36601         {
36602                 name:           "LAOfloor",
36603                 argLen:         3,
36604                 clobberFlags:   true,
36605                 hasSideEffects: true,
36606                 asm:            s390x.ALAO,
36607                 reg: regInfo{
36608                         inputs: []inputInfo{
36609                                 {0, 2},     // R1
36610                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36611                         },
36612                         clobbers: 2, // R1
36613                 },
36614         },
36615         {
36616                 name:           "LoweredAtomicCas32",
36617                 auxType:        auxSymOff,
36618                 argLen:         4,
36619                 clobberFlags:   true,
36620                 faultOnNilArg0: true,
36621                 hasSideEffects: true,
36622                 symEffect:      SymRdWr,
36623                 asm:            s390x.ACS,
36624                 reg: regInfo{
36625                         inputs: []inputInfo{
36626                                 {1, 1},     // R0
36627                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36628                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36629                         },
36630                         clobbers: 1, // R0
36631                         outputs: []outputInfo{
36632                                 {1, 0},
36633                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36634                         },
36635                 },
36636         },
36637         {
36638                 name:           "LoweredAtomicCas64",
36639                 auxType:        auxSymOff,
36640                 argLen:         4,
36641                 clobberFlags:   true,
36642                 faultOnNilArg0: true,
36643                 hasSideEffects: true,
36644                 symEffect:      SymRdWr,
36645                 asm:            s390x.ACSG,
36646                 reg: regInfo{
36647                         inputs: []inputInfo{
36648                                 {1, 1},     // R0
36649                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36650                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36651                         },
36652                         clobbers: 1, // R0
36653                         outputs: []outputInfo{
36654                                 {1, 0},
36655                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36656                         },
36657                 },
36658         },
36659         {
36660                 name:           "LoweredAtomicExchange32",
36661                 auxType:        auxSymOff,
36662                 argLen:         3,
36663                 clobberFlags:   true,
36664                 faultOnNilArg0: true,
36665                 hasSideEffects: true,
36666                 symEffect:      SymRdWr,
36667                 asm:            s390x.ACS,
36668                 reg: regInfo{
36669                         inputs: []inputInfo{
36670                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36671                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36672                         },
36673                         outputs: []outputInfo{
36674                                 {1, 0},
36675                                 {0, 1}, // R0
36676                         },
36677                 },
36678         },
36679         {
36680                 name:           "LoweredAtomicExchange64",
36681                 auxType:        auxSymOff,
36682                 argLen:         3,
36683                 clobberFlags:   true,
36684                 faultOnNilArg0: true,
36685                 hasSideEffects: true,
36686                 symEffect:      SymRdWr,
36687                 asm:            s390x.ACSG,
36688                 reg: regInfo{
36689                         inputs: []inputInfo{
36690                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36691                                 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36692                         },
36693                         outputs: []outputInfo{
36694                                 {1, 0},
36695                                 {0, 1}, // R0
36696                         },
36697                 },
36698         },
36699         {
36700                 name:         "FLOGR",
36701                 argLen:       1,
36702                 clobberFlags: true,
36703                 asm:          s390x.AFLOGR,
36704                 reg: regInfo{
36705                         inputs: []inputInfo{
36706                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36707                         },
36708                         clobbers: 2, // R1
36709                         outputs: []outputInfo{
36710                                 {0, 1}, // R0
36711                         },
36712                 },
36713         },
36714         {
36715                 name:         "POPCNT",
36716                 argLen:       1,
36717                 clobberFlags: true,
36718                 asm:          s390x.APOPCNT,
36719                 reg: regInfo{
36720                         inputs: []inputInfo{
36721                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36722                         },
36723                         outputs: []outputInfo{
36724                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36725                         },
36726                 },
36727         },
36728         {
36729                 name:   "MLGR",
36730                 argLen: 2,
36731                 asm:    s390x.AMLGR,
36732                 reg: regInfo{
36733                         inputs: []inputInfo{
36734                                 {1, 8},     // R3
36735                                 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
36736                         },
36737                         outputs: []outputInfo{
36738                                 {0, 4}, // R2
36739                                 {1, 8}, // R3
36740                         },
36741                 },
36742         },
36743         {
36744                 name:   "SumBytes2",
36745                 argLen: 1,
36746                 reg:    regInfo{},
36747         },
36748         {
36749                 name:   "SumBytes4",
36750                 argLen: 1,
36751                 reg:    regInfo{},
36752         },
36753         {
36754                 name:   "SumBytes8",
36755                 argLen: 1,
36756                 reg:    regInfo{},
36757         },
36758         {
36759                 name:           "STMG2",
36760                 auxType:        auxSymOff,
36761                 argLen:         4,
36762                 clobberFlags:   true,
36763                 faultOnNilArg0: true,
36764                 symEffect:      SymWrite,
36765                 asm:            s390x.ASTMG,
36766                 reg: regInfo{
36767                         inputs: []inputInfo{
36768                                 {1, 2},     // R1
36769                                 {2, 4},     // R2
36770                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36771                         },
36772                 },
36773         },
36774         {
36775                 name:           "STMG3",
36776                 auxType:        auxSymOff,
36777                 argLen:         5,
36778                 clobberFlags:   true,
36779                 faultOnNilArg0: true,
36780                 symEffect:      SymWrite,
36781                 asm:            s390x.ASTMG,
36782                 reg: regInfo{
36783                         inputs: []inputInfo{
36784                                 {1, 2},     // R1
36785                                 {2, 4},     // R2
36786                                 {3, 8},     // R3
36787                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36788                         },
36789                 },
36790         },
36791         {
36792                 name:           "STMG4",
36793                 auxType:        auxSymOff,
36794                 argLen:         6,
36795                 clobberFlags:   true,
36796                 faultOnNilArg0: true,
36797                 symEffect:      SymWrite,
36798                 asm:            s390x.ASTMG,
36799                 reg: regInfo{
36800                         inputs: []inputInfo{
36801                                 {1, 2},     // R1
36802                                 {2, 4},     // R2
36803                                 {3, 8},     // R3
36804                                 {4, 16},    // R4
36805                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36806                         },
36807                 },
36808         },
36809         {
36810                 name:           "STM2",
36811                 auxType:        auxSymOff,
36812                 argLen:         4,
36813                 clobberFlags:   true,
36814                 faultOnNilArg0: true,
36815                 symEffect:      SymWrite,
36816                 asm:            s390x.ASTMY,
36817                 reg: regInfo{
36818                         inputs: []inputInfo{
36819                                 {1, 2},     // R1
36820                                 {2, 4},     // R2
36821                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36822                         },
36823                 },
36824         },
36825         {
36826                 name:           "STM3",
36827                 auxType:        auxSymOff,
36828                 argLen:         5,
36829                 clobberFlags:   true,
36830                 faultOnNilArg0: true,
36831                 symEffect:      SymWrite,
36832                 asm:            s390x.ASTMY,
36833                 reg: regInfo{
36834                         inputs: []inputInfo{
36835                                 {1, 2},     // R1
36836                                 {2, 4},     // R2
36837                                 {3, 8},     // R3
36838                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36839                         },
36840                 },
36841         },
36842         {
36843                 name:           "STM4",
36844                 auxType:        auxSymOff,
36845                 argLen:         6,
36846                 clobberFlags:   true,
36847                 faultOnNilArg0: true,
36848                 symEffect:      SymWrite,
36849                 asm:            s390x.ASTMY,
36850                 reg: regInfo{
36851                         inputs: []inputInfo{
36852                                 {1, 2},     // R1
36853                                 {2, 4},     // R2
36854                                 {3, 8},     // R3
36855                                 {4, 16},    // R4
36856                                 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36857                         },
36858                 },
36859         },
36860         {
36861                 name:           "LoweredMove",
36862                 auxType:        auxInt64,
36863                 argLen:         4,
36864                 clobberFlags:   true,
36865                 faultOnNilArg0: true,
36866                 faultOnNilArg1: true,
36867                 reg: regInfo{
36868                         inputs: []inputInfo{
36869                                 {0, 2},     // R1
36870                                 {1, 4},     // R2
36871                                 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36872                         },
36873                         clobbers: 6, // R1 R2
36874                 },
36875         },
36876         {
36877                 name:           "LoweredZero",
36878                 auxType:        auxInt64,
36879                 argLen:         3,
36880                 clobberFlags:   true,
36881                 faultOnNilArg0: true,
36882                 reg: regInfo{
36883                         inputs: []inputInfo{
36884                                 {0, 2},     // R1
36885                                 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
36886                         },
36887                         clobbers: 2, // R1
36888                 },
36889         },
36890
36891         {
36892                 name:    "LoweredStaticCall",
36893                 auxType: auxCallOff,
36894                 argLen:  1,
36895                 call:    true,
36896                 reg: regInfo{
36897                         clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
36898                 },
36899         },
36900         {
36901                 name:     "LoweredTailCall",
36902                 auxType:  auxCallOff,
36903                 argLen:   1,
36904                 call:     true,
36905                 tailCall: true,
36906                 reg: regInfo{
36907                         clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
36908                 },
36909         },
36910         {
36911                 name:    "LoweredClosureCall",
36912                 auxType: auxCallOff,
36913                 argLen:  3,
36914                 call:    true,
36915                 reg: regInfo{
36916                         inputs: []inputInfo{
36917                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36918                                 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36919                         },
36920                         clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
36921                 },
36922         },
36923         {
36924                 name:    "LoweredInterCall",
36925                 auxType: auxCallOff,
36926                 argLen:  2,
36927                 call:    true,
36928                 reg: regInfo{
36929                         inputs: []inputInfo{
36930                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36931                         },
36932                         clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
36933                 },
36934         },
36935         {
36936                 name:              "LoweredAddr",
36937                 auxType:           auxSymOff,
36938                 argLen:            1,
36939                 rematerializeable: true,
36940                 symEffect:         SymAddr,
36941                 reg: regInfo{
36942                         inputs: []inputInfo{
36943                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
36944                         },
36945                         outputs: []outputInfo{
36946                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36947                         },
36948                 },
36949         },
36950         {
36951                 name:    "LoweredMove",
36952                 auxType: auxInt64,
36953                 argLen:  3,
36954                 reg: regInfo{
36955                         inputs: []inputInfo{
36956                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36957                                 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36958                         },
36959                 },
36960         },
36961         {
36962                 name:    "LoweredZero",
36963                 auxType: auxInt64,
36964                 argLen:  2,
36965                 reg: regInfo{
36966                         inputs: []inputInfo{
36967                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36968                         },
36969                 },
36970         },
36971         {
36972                 name:   "LoweredGetClosurePtr",
36973                 argLen: 0,
36974                 reg: regInfo{
36975                         outputs: []outputInfo{
36976                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36977                         },
36978                 },
36979         },
36980         {
36981                 name:              "LoweredGetCallerPC",
36982                 argLen:            0,
36983                 rematerializeable: true,
36984                 reg: regInfo{
36985                         outputs: []outputInfo{
36986                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36987                         },
36988                 },
36989         },
36990         {
36991                 name:              "LoweredGetCallerSP",
36992                 argLen:            1,
36993                 rematerializeable: true,
36994                 reg: regInfo{
36995                         outputs: []outputInfo{
36996                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
36997                         },
36998                 },
36999         },
37000         {
37001                 name:           "LoweredNilCheck",
37002                 argLen:         2,
37003                 nilCheck:       true,
37004                 faultOnNilArg0: true,
37005                 reg: regInfo{
37006                         inputs: []inputInfo{
37007                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37008                         },
37009                 },
37010         },
37011         {
37012                 name:    "LoweredWB",
37013                 auxType: auxInt64,
37014                 argLen:  1,
37015                 reg: regInfo{
37016                         clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
37017                         outputs: []outputInfo{
37018                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37019                         },
37020                 },
37021         },
37022         {
37023                 name:   "LoweredConvert",
37024                 argLen: 2,
37025                 reg: regInfo{
37026                         inputs: []inputInfo{
37027                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37028                         },
37029                         outputs: []outputInfo{
37030                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37031                         },
37032                 },
37033         },
37034         {
37035                 name:   "Select",
37036                 argLen: 3,
37037                 asm:    wasm.ASelect,
37038                 reg: regInfo{
37039                         inputs: []inputInfo{
37040                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37041                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37042                                 {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37043                         },
37044                         outputs: []outputInfo{
37045                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37046                         },
37047                 },
37048         },
37049         {
37050                 name:    "I64Load8U",
37051                 auxType: auxInt64,
37052                 argLen:  2,
37053                 asm:     wasm.AI64Load8U,
37054                 reg: regInfo{
37055                         inputs: []inputInfo{
37056                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37057                         },
37058                         outputs: []outputInfo{
37059                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37060                         },
37061                 },
37062         },
37063         {
37064                 name:    "I64Load8S",
37065                 auxType: auxInt64,
37066                 argLen:  2,
37067                 asm:     wasm.AI64Load8S,
37068                 reg: regInfo{
37069                         inputs: []inputInfo{
37070                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37071                         },
37072                         outputs: []outputInfo{
37073                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37074                         },
37075                 },
37076         },
37077         {
37078                 name:    "I64Load16U",
37079                 auxType: auxInt64,
37080                 argLen:  2,
37081                 asm:     wasm.AI64Load16U,
37082                 reg: regInfo{
37083                         inputs: []inputInfo{
37084                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37085                         },
37086                         outputs: []outputInfo{
37087                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37088                         },
37089                 },
37090         },
37091         {
37092                 name:    "I64Load16S",
37093                 auxType: auxInt64,
37094                 argLen:  2,
37095                 asm:     wasm.AI64Load16S,
37096                 reg: regInfo{
37097                         inputs: []inputInfo{
37098                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37099                         },
37100                         outputs: []outputInfo{
37101                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37102                         },
37103                 },
37104         },
37105         {
37106                 name:    "I64Load32U",
37107                 auxType: auxInt64,
37108                 argLen:  2,
37109                 asm:     wasm.AI64Load32U,
37110                 reg: regInfo{
37111                         inputs: []inputInfo{
37112                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37113                         },
37114                         outputs: []outputInfo{
37115                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37116                         },
37117                 },
37118         },
37119         {
37120                 name:    "I64Load32S",
37121                 auxType: auxInt64,
37122                 argLen:  2,
37123                 asm:     wasm.AI64Load32S,
37124                 reg: regInfo{
37125                         inputs: []inputInfo{
37126                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37127                         },
37128                         outputs: []outputInfo{
37129                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37130                         },
37131                 },
37132         },
37133         {
37134                 name:    "I64Load",
37135                 auxType: auxInt64,
37136                 argLen:  2,
37137                 asm:     wasm.AI64Load,
37138                 reg: regInfo{
37139                         inputs: []inputInfo{
37140                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37141                         },
37142                         outputs: []outputInfo{
37143                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37144                         },
37145                 },
37146         },
37147         {
37148                 name:    "I64Store8",
37149                 auxType: auxInt64,
37150                 argLen:  3,
37151                 asm:     wasm.AI64Store8,
37152                 reg: regInfo{
37153                         inputs: []inputInfo{
37154                                 {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37155                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37156                         },
37157                 },
37158         },
37159         {
37160                 name:    "I64Store16",
37161                 auxType: auxInt64,
37162                 argLen:  3,
37163                 asm:     wasm.AI64Store16,
37164                 reg: regInfo{
37165                         inputs: []inputInfo{
37166                                 {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37167                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37168                         },
37169                 },
37170         },
37171         {
37172                 name:    "I64Store32",
37173                 auxType: auxInt64,
37174                 argLen:  3,
37175                 asm:     wasm.AI64Store32,
37176                 reg: regInfo{
37177                         inputs: []inputInfo{
37178                                 {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37179                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37180                         },
37181                 },
37182         },
37183         {
37184                 name:    "I64Store",
37185                 auxType: auxInt64,
37186                 argLen:  3,
37187                 asm:     wasm.AI64Store,
37188                 reg: regInfo{
37189                         inputs: []inputInfo{
37190                                 {1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37191                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37192                         },
37193                 },
37194         },
37195         {
37196                 name:    "F32Load",
37197                 auxType: auxInt64,
37198                 argLen:  2,
37199                 asm:     wasm.AF32Load,
37200                 reg: regInfo{
37201                         inputs: []inputInfo{
37202                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37203                         },
37204                         outputs: []outputInfo{
37205                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37206                         },
37207                 },
37208         },
37209         {
37210                 name:    "F64Load",
37211                 auxType: auxInt64,
37212                 argLen:  2,
37213                 asm:     wasm.AF64Load,
37214                 reg: regInfo{
37215                         inputs: []inputInfo{
37216                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37217                         },
37218                         outputs: []outputInfo{
37219                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37220                         },
37221                 },
37222         },
37223         {
37224                 name:    "F32Store",
37225                 auxType: auxInt64,
37226                 argLen:  3,
37227                 asm:     wasm.AF32Store,
37228                 reg: regInfo{
37229                         inputs: []inputInfo{
37230                                 {1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37231                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37232                         },
37233                 },
37234         },
37235         {
37236                 name:    "F64Store",
37237                 auxType: auxInt64,
37238                 argLen:  3,
37239                 asm:     wasm.AF64Store,
37240                 reg: regInfo{
37241                         inputs: []inputInfo{
37242                                 {1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37243                                 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
37244                         },
37245                 },
37246         },
37247         {
37248                 name:              "I64Const",
37249                 auxType:           auxInt64,
37250                 argLen:            0,
37251                 rematerializeable: true,
37252                 reg: regInfo{
37253                         outputs: []outputInfo{
37254                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37255                         },
37256                 },
37257         },
37258         {
37259                 name:              "F32Const",
37260                 auxType:           auxFloat32,
37261                 argLen:            0,
37262                 rematerializeable: true,
37263                 reg: regInfo{
37264                         outputs: []outputInfo{
37265                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37266                         },
37267                 },
37268         },
37269         {
37270                 name:              "F64Const",
37271                 auxType:           auxFloat64,
37272                 argLen:            0,
37273                 rematerializeable: true,
37274                 reg: regInfo{
37275                         outputs: []outputInfo{
37276                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37277                         },
37278                 },
37279         },
37280         {
37281                 name:   "I64Eqz",
37282                 argLen: 1,
37283                 asm:    wasm.AI64Eqz,
37284                 reg: regInfo{
37285                         inputs: []inputInfo{
37286                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37287                         },
37288                         outputs: []outputInfo{
37289                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37290                         },
37291                 },
37292         },
37293         {
37294                 name:   "I64Eq",
37295                 argLen: 2,
37296                 asm:    wasm.AI64Eq,
37297                 reg: regInfo{
37298                         inputs: []inputInfo{
37299                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37300                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37301                         },
37302                         outputs: []outputInfo{
37303                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37304                         },
37305                 },
37306         },
37307         {
37308                 name:   "I64Ne",
37309                 argLen: 2,
37310                 asm:    wasm.AI64Ne,
37311                 reg: regInfo{
37312                         inputs: []inputInfo{
37313                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37314                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37315                         },
37316                         outputs: []outputInfo{
37317                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37318                         },
37319                 },
37320         },
37321         {
37322                 name:   "I64LtS",
37323                 argLen: 2,
37324                 asm:    wasm.AI64LtS,
37325                 reg: regInfo{
37326                         inputs: []inputInfo{
37327                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37328                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37329                         },
37330                         outputs: []outputInfo{
37331                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37332                         },
37333                 },
37334         },
37335         {
37336                 name:   "I64LtU",
37337                 argLen: 2,
37338                 asm:    wasm.AI64LtU,
37339                 reg: regInfo{
37340                         inputs: []inputInfo{
37341                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37342                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37343                         },
37344                         outputs: []outputInfo{
37345                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37346                         },
37347                 },
37348         },
37349         {
37350                 name:   "I64GtS",
37351                 argLen: 2,
37352                 asm:    wasm.AI64GtS,
37353                 reg: regInfo{
37354                         inputs: []inputInfo{
37355                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37356                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37357                         },
37358                         outputs: []outputInfo{
37359                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37360                         },
37361                 },
37362         },
37363         {
37364                 name:   "I64GtU",
37365                 argLen: 2,
37366                 asm:    wasm.AI64GtU,
37367                 reg: regInfo{
37368                         inputs: []inputInfo{
37369                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37370                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37371                         },
37372                         outputs: []outputInfo{
37373                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37374                         },
37375                 },
37376         },
37377         {
37378                 name:   "I64LeS",
37379                 argLen: 2,
37380                 asm:    wasm.AI64LeS,
37381                 reg: regInfo{
37382                         inputs: []inputInfo{
37383                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37384                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37385                         },
37386                         outputs: []outputInfo{
37387                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37388                         },
37389                 },
37390         },
37391         {
37392                 name:   "I64LeU",
37393                 argLen: 2,
37394                 asm:    wasm.AI64LeU,
37395                 reg: regInfo{
37396                         inputs: []inputInfo{
37397                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37398                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37399                         },
37400                         outputs: []outputInfo{
37401                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37402                         },
37403                 },
37404         },
37405         {
37406                 name:   "I64GeS",
37407                 argLen: 2,
37408                 asm:    wasm.AI64GeS,
37409                 reg: regInfo{
37410                         inputs: []inputInfo{
37411                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37412                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37413                         },
37414                         outputs: []outputInfo{
37415                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37416                         },
37417                 },
37418         },
37419         {
37420                 name:   "I64GeU",
37421                 argLen: 2,
37422                 asm:    wasm.AI64GeU,
37423                 reg: regInfo{
37424                         inputs: []inputInfo{
37425                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37426                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37427                         },
37428                         outputs: []outputInfo{
37429                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37430                         },
37431                 },
37432         },
37433         {
37434                 name:   "F32Eq",
37435                 argLen: 2,
37436                 asm:    wasm.AF32Eq,
37437                 reg: regInfo{
37438                         inputs: []inputInfo{
37439                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37440                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37441                         },
37442                         outputs: []outputInfo{
37443                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37444                         },
37445                 },
37446         },
37447         {
37448                 name:   "F32Ne",
37449                 argLen: 2,
37450                 asm:    wasm.AF32Ne,
37451                 reg: regInfo{
37452                         inputs: []inputInfo{
37453                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37454                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37455                         },
37456                         outputs: []outputInfo{
37457                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37458                         },
37459                 },
37460         },
37461         {
37462                 name:   "F32Lt",
37463                 argLen: 2,
37464                 asm:    wasm.AF32Lt,
37465                 reg: regInfo{
37466                         inputs: []inputInfo{
37467                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37468                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37469                         },
37470                         outputs: []outputInfo{
37471                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37472                         },
37473                 },
37474         },
37475         {
37476                 name:   "F32Gt",
37477                 argLen: 2,
37478                 asm:    wasm.AF32Gt,
37479                 reg: regInfo{
37480                         inputs: []inputInfo{
37481                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37482                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37483                         },
37484                         outputs: []outputInfo{
37485                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37486                         },
37487                 },
37488         },
37489         {
37490                 name:   "F32Le",
37491                 argLen: 2,
37492                 asm:    wasm.AF32Le,
37493                 reg: regInfo{
37494                         inputs: []inputInfo{
37495                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37496                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37497                         },
37498                         outputs: []outputInfo{
37499                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37500                         },
37501                 },
37502         },
37503         {
37504                 name:   "F32Ge",
37505                 argLen: 2,
37506                 asm:    wasm.AF32Ge,
37507                 reg: regInfo{
37508                         inputs: []inputInfo{
37509                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37510                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37511                         },
37512                         outputs: []outputInfo{
37513                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37514                         },
37515                 },
37516         },
37517         {
37518                 name:   "F64Eq",
37519                 argLen: 2,
37520                 asm:    wasm.AF64Eq,
37521                 reg: regInfo{
37522                         inputs: []inputInfo{
37523                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37524                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37525                         },
37526                         outputs: []outputInfo{
37527                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37528                         },
37529                 },
37530         },
37531         {
37532                 name:   "F64Ne",
37533                 argLen: 2,
37534                 asm:    wasm.AF64Ne,
37535                 reg: regInfo{
37536                         inputs: []inputInfo{
37537                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37538                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37539                         },
37540                         outputs: []outputInfo{
37541                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37542                         },
37543                 },
37544         },
37545         {
37546                 name:   "F64Lt",
37547                 argLen: 2,
37548                 asm:    wasm.AF64Lt,
37549                 reg: regInfo{
37550                         inputs: []inputInfo{
37551                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37552                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37553                         },
37554                         outputs: []outputInfo{
37555                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37556                         },
37557                 },
37558         },
37559         {
37560                 name:   "F64Gt",
37561                 argLen: 2,
37562                 asm:    wasm.AF64Gt,
37563                 reg: regInfo{
37564                         inputs: []inputInfo{
37565                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37566                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37567                         },
37568                         outputs: []outputInfo{
37569                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37570                         },
37571                 },
37572         },
37573         {
37574                 name:   "F64Le",
37575                 argLen: 2,
37576                 asm:    wasm.AF64Le,
37577                 reg: regInfo{
37578                         inputs: []inputInfo{
37579                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37580                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37581                         },
37582                         outputs: []outputInfo{
37583                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37584                         },
37585                 },
37586         },
37587         {
37588                 name:   "F64Ge",
37589                 argLen: 2,
37590                 asm:    wasm.AF64Ge,
37591                 reg: regInfo{
37592                         inputs: []inputInfo{
37593                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37594                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37595                         },
37596                         outputs: []outputInfo{
37597                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37598                         },
37599                 },
37600         },
37601         {
37602                 name:   "I64Add",
37603                 argLen: 2,
37604                 asm:    wasm.AI64Add,
37605                 reg: regInfo{
37606                         inputs: []inputInfo{
37607                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37608                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37609                         },
37610                         outputs: []outputInfo{
37611                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37612                         },
37613                 },
37614         },
37615         {
37616                 name:    "I64AddConst",
37617                 auxType: auxInt64,
37618                 argLen:  1,
37619                 asm:     wasm.AI64Add,
37620                 reg: regInfo{
37621                         inputs: []inputInfo{
37622                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37623                         },
37624                         outputs: []outputInfo{
37625                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37626                         },
37627                 },
37628         },
37629         {
37630                 name:   "I64Sub",
37631                 argLen: 2,
37632                 asm:    wasm.AI64Sub,
37633                 reg: regInfo{
37634                         inputs: []inputInfo{
37635                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37636                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37637                         },
37638                         outputs: []outputInfo{
37639                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37640                         },
37641                 },
37642         },
37643         {
37644                 name:   "I64Mul",
37645                 argLen: 2,
37646                 asm:    wasm.AI64Mul,
37647                 reg: regInfo{
37648                         inputs: []inputInfo{
37649                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37650                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37651                         },
37652                         outputs: []outputInfo{
37653                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37654                         },
37655                 },
37656         },
37657         {
37658                 name:   "I64DivS",
37659                 argLen: 2,
37660                 asm:    wasm.AI64DivS,
37661                 reg: regInfo{
37662                         inputs: []inputInfo{
37663                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37664                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37665                         },
37666                         outputs: []outputInfo{
37667                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37668                         },
37669                 },
37670         },
37671         {
37672                 name:   "I64DivU",
37673                 argLen: 2,
37674                 asm:    wasm.AI64DivU,
37675                 reg: regInfo{
37676                         inputs: []inputInfo{
37677                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37678                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37679                         },
37680                         outputs: []outputInfo{
37681                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37682                         },
37683                 },
37684         },
37685         {
37686                 name:   "I64RemS",
37687                 argLen: 2,
37688                 asm:    wasm.AI64RemS,
37689                 reg: regInfo{
37690                         inputs: []inputInfo{
37691                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37692                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37693                         },
37694                         outputs: []outputInfo{
37695                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37696                         },
37697                 },
37698         },
37699         {
37700                 name:   "I64RemU",
37701                 argLen: 2,
37702                 asm:    wasm.AI64RemU,
37703                 reg: regInfo{
37704                         inputs: []inputInfo{
37705                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37706                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37707                         },
37708                         outputs: []outputInfo{
37709                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37710                         },
37711                 },
37712         },
37713         {
37714                 name:   "I64And",
37715                 argLen: 2,
37716                 asm:    wasm.AI64And,
37717                 reg: regInfo{
37718                         inputs: []inputInfo{
37719                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37720                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37721                         },
37722                         outputs: []outputInfo{
37723                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37724                         },
37725                 },
37726         },
37727         {
37728                 name:   "I64Or",
37729                 argLen: 2,
37730                 asm:    wasm.AI64Or,
37731                 reg: regInfo{
37732                         inputs: []inputInfo{
37733                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37734                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37735                         },
37736                         outputs: []outputInfo{
37737                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37738                         },
37739                 },
37740         },
37741         {
37742                 name:   "I64Xor",
37743                 argLen: 2,
37744                 asm:    wasm.AI64Xor,
37745                 reg: regInfo{
37746                         inputs: []inputInfo{
37747                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37748                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37749                         },
37750                         outputs: []outputInfo{
37751                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37752                         },
37753                 },
37754         },
37755         {
37756                 name:   "I64Shl",
37757                 argLen: 2,
37758                 asm:    wasm.AI64Shl,
37759                 reg: regInfo{
37760                         inputs: []inputInfo{
37761                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37762                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37763                         },
37764                         outputs: []outputInfo{
37765                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37766                         },
37767                 },
37768         },
37769         {
37770                 name:   "I64ShrS",
37771                 argLen: 2,
37772                 asm:    wasm.AI64ShrS,
37773                 reg: regInfo{
37774                         inputs: []inputInfo{
37775                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37776                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37777                         },
37778                         outputs: []outputInfo{
37779                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37780                         },
37781                 },
37782         },
37783         {
37784                 name:   "I64ShrU",
37785                 argLen: 2,
37786                 asm:    wasm.AI64ShrU,
37787                 reg: regInfo{
37788                         inputs: []inputInfo{
37789                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37790                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
37791                         },
37792                         outputs: []outputInfo{
37793                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37794                         },
37795                 },
37796         },
37797         {
37798                 name:   "F32Neg",
37799                 argLen: 1,
37800                 asm:    wasm.AF32Neg,
37801                 reg: regInfo{
37802                         inputs: []inputInfo{
37803                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37804                         },
37805                         outputs: []outputInfo{
37806                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37807                         },
37808                 },
37809         },
37810         {
37811                 name:   "F32Add",
37812                 argLen: 2,
37813                 asm:    wasm.AF32Add,
37814                 reg: regInfo{
37815                         inputs: []inputInfo{
37816                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37817                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37818                         },
37819                         outputs: []outputInfo{
37820                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37821                         },
37822                 },
37823         },
37824         {
37825                 name:   "F32Sub",
37826                 argLen: 2,
37827                 asm:    wasm.AF32Sub,
37828                 reg: regInfo{
37829                         inputs: []inputInfo{
37830                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37831                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37832                         },
37833                         outputs: []outputInfo{
37834                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37835                         },
37836                 },
37837         },
37838         {
37839                 name:   "F32Mul",
37840                 argLen: 2,
37841                 asm:    wasm.AF32Mul,
37842                 reg: regInfo{
37843                         inputs: []inputInfo{
37844                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37845                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37846                         },
37847                         outputs: []outputInfo{
37848                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37849                         },
37850                 },
37851         },
37852         {
37853                 name:   "F32Div",
37854                 argLen: 2,
37855                 asm:    wasm.AF32Div,
37856                 reg: regInfo{
37857                         inputs: []inputInfo{
37858                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37859                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37860                         },
37861                         outputs: []outputInfo{
37862                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37863                         },
37864                 },
37865         },
37866         {
37867                 name:   "F64Neg",
37868                 argLen: 1,
37869                 asm:    wasm.AF64Neg,
37870                 reg: regInfo{
37871                         inputs: []inputInfo{
37872                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37873                         },
37874                         outputs: []outputInfo{
37875                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37876                         },
37877                 },
37878         },
37879         {
37880                 name:   "F64Add",
37881                 argLen: 2,
37882                 asm:    wasm.AF64Add,
37883                 reg: regInfo{
37884                         inputs: []inputInfo{
37885                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37886                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37887                         },
37888                         outputs: []outputInfo{
37889                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37890                         },
37891                 },
37892         },
37893         {
37894                 name:   "F64Sub",
37895                 argLen: 2,
37896                 asm:    wasm.AF64Sub,
37897                 reg: regInfo{
37898                         inputs: []inputInfo{
37899                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37900                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37901                         },
37902                         outputs: []outputInfo{
37903                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37904                         },
37905                 },
37906         },
37907         {
37908                 name:   "F64Mul",
37909                 argLen: 2,
37910                 asm:    wasm.AF64Mul,
37911                 reg: regInfo{
37912                         inputs: []inputInfo{
37913                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37914                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37915                         },
37916                         outputs: []outputInfo{
37917                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37918                         },
37919                 },
37920         },
37921         {
37922                 name:   "F64Div",
37923                 argLen: 2,
37924                 asm:    wasm.AF64Div,
37925                 reg: regInfo{
37926                         inputs: []inputInfo{
37927                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37928                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37929                         },
37930                         outputs: []outputInfo{
37931                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37932                         },
37933                 },
37934         },
37935         {
37936                 name:   "I64TruncSatF64S",
37937                 argLen: 1,
37938                 asm:    wasm.AI64TruncSatF64S,
37939                 reg: regInfo{
37940                         inputs: []inputInfo{
37941                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37942                         },
37943                         outputs: []outputInfo{
37944                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37945                         },
37946                 },
37947         },
37948         {
37949                 name:   "I64TruncSatF64U",
37950                 argLen: 1,
37951                 asm:    wasm.AI64TruncSatF64U,
37952                 reg: regInfo{
37953                         inputs: []inputInfo{
37954                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
37955                         },
37956                         outputs: []outputInfo{
37957                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37958                         },
37959                 },
37960         },
37961         {
37962                 name:   "I64TruncSatF32S",
37963                 argLen: 1,
37964                 asm:    wasm.AI64TruncSatF32S,
37965                 reg: regInfo{
37966                         inputs: []inputInfo{
37967                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37968                         },
37969                         outputs: []outputInfo{
37970                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37971                         },
37972                 },
37973         },
37974         {
37975                 name:   "I64TruncSatF32U",
37976                 argLen: 1,
37977                 asm:    wasm.AI64TruncSatF32U,
37978                 reg: regInfo{
37979                         inputs: []inputInfo{
37980                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37981                         },
37982                         outputs: []outputInfo{
37983                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37984                         },
37985                 },
37986         },
37987         {
37988                 name:   "F32ConvertI64S",
37989                 argLen: 1,
37990                 asm:    wasm.AF32ConvertI64S,
37991                 reg: regInfo{
37992                         inputs: []inputInfo{
37993                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
37994                         },
37995                         outputs: []outputInfo{
37996                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
37997                         },
37998                 },
37999         },
38000         {
38001                 name:   "F32ConvertI64U",
38002                 argLen: 1,
38003                 asm:    wasm.AF32ConvertI64U,
38004                 reg: regInfo{
38005                         inputs: []inputInfo{
38006                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38007                         },
38008                         outputs: []outputInfo{
38009                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38010                         },
38011                 },
38012         },
38013         {
38014                 name:   "F64ConvertI64S",
38015                 argLen: 1,
38016                 asm:    wasm.AF64ConvertI64S,
38017                 reg: regInfo{
38018                         inputs: []inputInfo{
38019                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38020                         },
38021                         outputs: []outputInfo{
38022                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38023                         },
38024                 },
38025         },
38026         {
38027                 name:   "F64ConvertI64U",
38028                 argLen: 1,
38029                 asm:    wasm.AF64ConvertI64U,
38030                 reg: regInfo{
38031                         inputs: []inputInfo{
38032                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38033                         },
38034                         outputs: []outputInfo{
38035                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38036                         },
38037                 },
38038         },
38039         {
38040                 name:   "F32DemoteF64",
38041                 argLen: 1,
38042                 asm:    wasm.AF32DemoteF64,
38043                 reg: regInfo{
38044                         inputs: []inputInfo{
38045                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38046                         },
38047                         outputs: []outputInfo{
38048                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38049                         },
38050                 },
38051         },
38052         {
38053                 name:   "F64PromoteF32",
38054                 argLen: 1,
38055                 asm:    wasm.AF64PromoteF32,
38056                 reg: regInfo{
38057                         inputs: []inputInfo{
38058                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38059                         },
38060                         outputs: []outputInfo{
38061                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38062                         },
38063                 },
38064         },
38065         {
38066                 name:   "I64Extend8S",
38067                 argLen: 1,
38068                 asm:    wasm.AI64Extend8S,
38069                 reg: regInfo{
38070                         inputs: []inputInfo{
38071                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38072                         },
38073                         outputs: []outputInfo{
38074                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38075                         },
38076                 },
38077         },
38078         {
38079                 name:   "I64Extend16S",
38080                 argLen: 1,
38081                 asm:    wasm.AI64Extend16S,
38082                 reg: regInfo{
38083                         inputs: []inputInfo{
38084                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38085                         },
38086                         outputs: []outputInfo{
38087                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38088                         },
38089                 },
38090         },
38091         {
38092                 name:   "I64Extend32S",
38093                 argLen: 1,
38094                 asm:    wasm.AI64Extend32S,
38095                 reg: regInfo{
38096                         inputs: []inputInfo{
38097                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38098                         },
38099                         outputs: []outputInfo{
38100                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38101                         },
38102                 },
38103         },
38104         {
38105                 name:   "F32Sqrt",
38106                 argLen: 1,
38107                 asm:    wasm.AF32Sqrt,
38108                 reg: regInfo{
38109                         inputs: []inputInfo{
38110                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38111                         },
38112                         outputs: []outputInfo{
38113                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38114                         },
38115                 },
38116         },
38117         {
38118                 name:   "F32Trunc",
38119                 argLen: 1,
38120                 asm:    wasm.AF32Trunc,
38121                 reg: regInfo{
38122                         inputs: []inputInfo{
38123                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38124                         },
38125                         outputs: []outputInfo{
38126                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38127                         },
38128                 },
38129         },
38130         {
38131                 name:   "F32Ceil",
38132                 argLen: 1,
38133                 asm:    wasm.AF32Ceil,
38134                 reg: regInfo{
38135                         inputs: []inputInfo{
38136                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38137                         },
38138                         outputs: []outputInfo{
38139                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38140                         },
38141                 },
38142         },
38143         {
38144                 name:   "F32Floor",
38145                 argLen: 1,
38146                 asm:    wasm.AF32Floor,
38147                 reg: regInfo{
38148                         inputs: []inputInfo{
38149                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38150                         },
38151                         outputs: []outputInfo{
38152                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38153                         },
38154                 },
38155         },
38156         {
38157                 name:   "F32Nearest",
38158                 argLen: 1,
38159                 asm:    wasm.AF32Nearest,
38160                 reg: regInfo{
38161                         inputs: []inputInfo{
38162                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38163                         },
38164                         outputs: []outputInfo{
38165                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38166                         },
38167                 },
38168         },
38169         {
38170                 name:   "F32Abs",
38171                 argLen: 1,
38172                 asm:    wasm.AF32Abs,
38173                 reg: regInfo{
38174                         inputs: []inputInfo{
38175                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38176                         },
38177                         outputs: []outputInfo{
38178                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38179                         },
38180                 },
38181         },
38182         {
38183                 name:   "F32Copysign",
38184                 argLen: 2,
38185                 asm:    wasm.AF32Copysign,
38186                 reg: regInfo{
38187                         inputs: []inputInfo{
38188                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38189                                 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38190                         },
38191                         outputs: []outputInfo{
38192                                 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
38193                         },
38194                 },
38195         },
38196         {
38197                 name:   "F64Sqrt",
38198                 argLen: 1,
38199                 asm:    wasm.AF64Sqrt,
38200                 reg: regInfo{
38201                         inputs: []inputInfo{
38202                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38203                         },
38204                         outputs: []outputInfo{
38205                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38206                         },
38207                 },
38208         },
38209         {
38210                 name:   "F64Trunc",
38211                 argLen: 1,
38212                 asm:    wasm.AF64Trunc,
38213                 reg: regInfo{
38214                         inputs: []inputInfo{
38215                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38216                         },
38217                         outputs: []outputInfo{
38218                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38219                         },
38220                 },
38221         },
38222         {
38223                 name:   "F64Ceil",
38224                 argLen: 1,
38225                 asm:    wasm.AF64Ceil,
38226                 reg: regInfo{
38227                         inputs: []inputInfo{
38228                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38229                         },
38230                         outputs: []outputInfo{
38231                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38232                         },
38233                 },
38234         },
38235         {
38236                 name:   "F64Floor",
38237                 argLen: 1,
38238                 asm:    wasm.AF64Floor,
38239                 reg: regInfo{
38240                         inputs: []inputInfo{
38241                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38242                         },
38243                         outputs: []outputInfo{
38244                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38245                         },
38246                 },
38247         },
38248         {
38249                 name:   "F64Nearest",
38250                 argLen: 1,
38251                 asm:    wasm.AF64Nearest,
38252                 reg: regInfo{
38253                         inputs: []inputInfo{
38254                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38255                         },
38256                         outputs: []outputInfo{
38257                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38258                         },
38259                 },
38260         },
38261         {
38262                 name:   "F64Abs",
38263                 argLen: 1,
38264                 asm:    wasm.AF64Abs,
38265                 reg: regInfo{
38266                         inputs: []inputInfo{
38267                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38268                         },
38269                         outputs: []outputInfo{
38270                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38271                         },
38272                 },
38273         },
38274         {
38275                 name:   "F64Copysign",
38276                 argLen: 2,
38277                 asm:    wasm.AF64Copysign,
38278                 reg: regInfo{
38279                         inputs: []inputInfo{
38280                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38281                                 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38282                         },
38283                         outputs: []outputInfo{
38284                                 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
38285                         },
38286                 },
38287         },
38288         {
38289                 name:   "I64Ctz",
38290                 argLen: 1,
38291                 asm:    wasm.AI64Ctz,
38292                 reg: regInfo{
38293                         inputs: []inputInfo{
38294                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38295                         },
38296                         outputs: []outputInfo{
38297                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38298                         },
38299                 },
38300         },
38301         {
38302                 name:   "I64Clz",
38303                 argLen: 1,
38304                 asm:    wasm.AI64Clz,
38305                 reg: regInfo{
38306                         inputs: []inputInfo{
38307                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38308                         },
38309                         outputs: []outputInfo{
38310                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38311                         },
38312                 },
38313         },
38314         {
38315                 name:   "I32Rotl",
38316                 argLen: 2,
38317                 asm:    wasm.AI32Rotl,
38318                 reg: regInfo{
38319                         inputs: []inputInfo{
38320                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38321                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38322                         },
38323                         outputs: []outputInfo{
38324                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38325                         },
38326                 },
38327         },
38328         {
38329                 name:   "I64Rotl",
38330                 argLen: 2,
38331                 asm:    wasm.AI64Rotl,
38332                 reg: regInfo{
38333                         inputs: []inputInfo{
38334                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38335                                 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38336                         },
38337                         outputs: []outputInfo{
38338                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38339                         },
38340                 },
38341         },
38342         {
38343                 name:   "I64Popcnt",
38344                 argLen: 1,
38345                 asm:    wasm.AI64Popcnt,
38346                 reg: regInfo{
38347                         inputs: []inputInfo{
38348                                 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
38349                         },
38350                         outputs: []outputInfo{
38351                                 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
38352                         },
38353                 },
38354         },
38355
38356         {
38357                 name:        "Add8",
38358                 argLen:      2,
38359                 commutative: true,
38360                 generic:     true,
38361         },
38362         {
38363                 name:        "Add16",
38364                 argLen:      2,
38365                 commutative: true,
38366                 generic:     true,
38367         },
38368         {
38369                 name:        "Add32",
38370                 argLen:      2,
38371                 commutative: true,
38372                 generic:     true,
38373         },
38374         {
38375                 name:        "Add64",
38376                 argLen:      2,
38377                 commutative: true,
38378                 generic:     true,
38379         },
38380         {
38381                 name:    "AddPtr",
38382                 argLen:  2,
38383                 generic: true,
38384         },
38385         {
38386                 name:        "Add32F",
38387                 argLen:      2,
38388                 commutative: true,
38389                 generic:     true,
38390         },
38391         {
38392                 name:        "Add64F",
38393                 argLen:      2,
38394                 commutative: true,
38395                 generic:     true,
38396         },
38397         {
38398                 name:    "Sub8",
38399                 argLen:  2,
38400                 generic: true,
38401         },
38402         {
38403                 name:    "Sub16",
38404                 argLen:  2,
38405                 generic: true,
38406         },
38407         {
38408                 name:    "Sub32",
38409                 argLen:  2,
38410                 generic: true,
38411         },
38412         {
38413                 name:    "Sub64",
38414                 argLen:  2,
38415                 generic: true,
38416         },
38417         {
38418                 name:    "SubPtr",
38419                 argLen:  2,
38420                 generic: true,
38421         },
38422         {
38423                 name:    "Sub32F",
38424                 argLen:  2,
38425                 generic: true,
38426         },
38427         {
38428                 name:    "Sub64F",
38429                 argLen:  2,
38430                 generic: true,
38431         },
38432         {
38433                 name:        "Mul8",
38434                 argLen:      2,
38435                 commutative: true,
38436                 generic:     true,
38437         },
38438         {
38439                 name:        "Mul16",
38440                 argLen:      2,
38441                 commutative: true,
38442                 generic:     true,
38443         },
38444         {
38445                 name:        "Mul32",
38446                 argLen:      2,
38447                 commutative: true,
38448                 generic:     true,
38449         },
38450         {
38451                 name:        "Mul64",
38452                 argLen:      2,
38453                 commutative: true,
38454                 generic:     true,
38455         },
38456         {
38457                 name:        "Mul32F",
38458                 argLen:      2,
38459                 commutative: true,
38460                 generic:     true,
38461         },
38462         {
38463                 name:        "Mul64F",
38464                 argLen:      2,
38465                 commutative: true,
38466                 generic:     true,
38467         },
38468         {
38469                 name:    "Div32F",
38470                 argLen:  2,
38471                 generic: true,
38472         },
38473         {
38474                 name:    "Div64F",
38475                 argLen:  2,
38476                 generic: true,
38477         },
38478         {
38479                 name:        "Hmul32",
38480                 argLen:      2,
38481                 commutative: true,
38482                 generic:     true,
38483         },
38484         {
38485                 name:        "Hmul32u",
38486                 argLen:      2,
38487                 commutative: true,
38488                 generic:     true,
38489         },
38490         {
38491                 name:        "Hmul64",
38492                 argLen:      2,
38493                 commutative: true,
38494                 generic:     true,
38495         },
38496         {
38497                 name:        "Hmul64u",
38498                 argLen:      2,
38499                 commutative: true,
38500                 generic:     true,
38501         },
38502         {
38503                 name:        "Mul32uhilo",
38504                 argLen:      2,
38505                 commutative: true,
38506                 generic:     true,
38507         },
38508         {
38509                 name:        "Mul64uhilo",
38510                 argLen:      2,
38511                 commutative: true,
38512                 generic:     true,
38513         },
38514         {
38515                 name:        "Mul32uover",
38516                 argLen:      2,
38517                 commutative: true,
38518                 generic:     true,
38519         },
38520         {
38521                 name:        "Mul64uover",
38522                 argLen:      2,
38523                 commutative: true,
38524                 generic:     true,
38525         },
38526         {
38527                 name:    "Avg32u",
38528                 argLen:  2,
38529                 generic: true,
38530         },
38531         {
38532                 name:    "Avg64u",
38533                 argLen:  2,
38534                 generic: true,
38535         },
38536         {
38537                 name:    "Div8",
38538                 argLen:  2,
38539                 generic: true,
38540         },
38541         {
38542                 name:    "Div8u",
38543                 argLen:  2,
38544                 generic: true,
38545         },
38546         {
38547                 name:    "Div16",
38548                 auxType: auxBool,
38549                 argLen:  2,
38550                 generic: true,
38551         },
38552         {
38553                 name:    "Div16u",
38554                 argLen:  2,
38555                 generic: true,
38556         },
38557         {
38558                 name:    "Div32",
38559                 auxType: auxBool,
38560                 argLen:  2,
38561                 generic: true,
38562         },
38563         {
38564                 name:    "Div32u",
38565                 argLen:  2,
38566                 generic: true,
38567         },
38568         {
38569                 name:    "Div64",
38570                 auxType: auxBool,
38571                 argLen:  2,
38572                 generic: true,
38573         },
38574         {
38575                 name:    "Div64u",
38576                 argLen:  2,
38577                 generic: true,
38578         },
38579         {
38580                 name:    "Div128u",
38581                 argLen:  3,
38582                 generic: true,
38583         },
38584         {
38585                 name:    "Mod8",
38586                 argLen:  2,
38587                 generic: true,
38588         },
38589         {
38590                 name:    "Mod8u",
38591                 argLen:  2,
38592                 generic: true,
38593         },
38594         {
38595                 name:    "Mod16",
38596                 auxType: auxBool,
38597                 argLen:  2,
38598                 generic: true,
38599         },
38600         {
38601                 name:    "Mod16u",
38602                 argLen:  2,
38603                 generic: true,
38604         },
38605         {
38606                 name:    "Mod32",
38607                 auxType: auxBool,
38608                 argLen:  2,
38609                 generic: true,
38610         },
38611         {
38612                 name:    "Mod32u",
38613                 argLen:  2,
38614                 generic: true,
38615         },
38616         {
38617                 name:    "Mod64",
38618                 auxType: auxBool,
38619                 argLen:  2,
38620                 generic: true,
38621         },
38622         {
38623                 name:    "Mod64u",
38624                 argLen:  2,
38625                 generic: true,
38626         },
38627         {
38628                 name:        "And8",
38629                 argLen:      2,
38630                 commutative: true,
38631                 generic:     true,
38632         },
38633         {
38634                 name:        "And16",
38635                 argLen:      2,
38636                 commutative: true,
38637                 generic:     true,
38638         },
38639         {
38640                 name:        "And32",
38641                 argLen:      2,
38642                 commutative: true,
38643                 generic:     true,
38644         },
38645         {
38646                 name:        "And64",
38647                 argLen:      2,
38648                 commutative: true,
38649                 generic:     true,
38650         },
38651         {
38652                 name:        "Or8",
38653                 argLen:      2,
38654                 commutative: true,
38655                 generic:     true,
38656         },
38657         {
38658                 name:        "Or16",
38659                 argLen:      2,
38660                 commutative: true,
38661                 generic:     true,
38662         },
38663         {
38664                 name:        "Or32",
38665                 argLen:      2,
38666                 commutative: true,
38667                 generic:     true,
38668         },
38669         {
38670                 name:        "Or64",
38671                 argLen:      2,
38672                 commutative: true,
38673                 generic:     true,
38674         },
38675         {
38676                 name:        "Xor8",
38677                 argLen:      2,
38678                 commutative: true,
38679                 generic:     true,
38680         },
38681         {
38682                 name:        "Xor16",
38683                 argLen:      2,
38684                 commutative: true,
38685                 generic:     true,
38686         },
38687         {
38688                 name:        "Xor32",
38689                 argLen:      2,
38690                 commutative: true,
38691                 generic:     true,
38692         },
38693         {
38694                 name:        "Xor64",
38695                 argLen:      2,
38696                 commutative: true,
38697                 generic:     true,
38698         },
38699         {
38700                 name:    "Lsh8x8",
38701                 auxType: auxBool,
38702                 argLen:  2,
38703                 generic: true,
38704         },
38705         {
38706                 name:    "Lsh8x16",
38707                 auxType: auxBool,
38708                 argLen:  2,
38709                 generic: true,
38710         },
38711         {
38712                 name:    "Lsh8x32",
38713                 auxType: auxBool,
38714                 argLen:  2,
38715                 generic: true,
38716         },
38717         {
38718                 name:    "Lsh8x64",
38719                 auxType: auxBool,
38720                 argLen:  2,
38721                 generic: true,
38722         },
38723         {
38724                 name:    "Lsh16x8",
38725                 auxType: auxBool,
38726                 argLen:  2,
38727                 generic: true,
38728         },
38729         {
38730                 name:    "Lsh16x16",
38731                 auxType: auxBool,
38732                 argLen:  2,
38733                 generic: true,
38734         },
38735         {
38736                 name:    "Lsh16x32",
38737                 auxType: auxBool,
38738                 argLen:  2,
38739                 generic: true,
38740         },
38741         {
38742                 name:    "Lsh16x64",
38743                 auxType: auxBool,
38744                 argLen:  2,
38745                 generic: true,
38746         },
38747         {
38748                 name:    "Lsh32x8",
38749                 auxType: auxBool,
38750                 argLen:  2,
38751                 generic: true,
38752         },
38753         {
38754                 name:    "Lsh32x16",
38755                 auxType: auxBool,
38756                 argLen:  2,
38757                 generic: true,
38758         },
38759         {
38760                 name:    "Lsh32x32",
38761                 auxType: auxBool,
38762                 argLen:  2,
38763                 generic: true,
38764         },
38765         {
38766                 name:    "Lsh32x64",
38767                 auxType: auxBool,
38768                 argLen:  2,
38769                 generic: true,
38770         },
38771         {
38772                 name:    "Lsh64x8",
38773                 auxType: auxBool,
38774                 argLen:  2,
38775                 generic: true,
38776         },
38777         {
38778                 name:    "Lsh64x16",
38779                 auxType: auxBool,
38780                 argLen:  2,
38781                 generic: true,
38782         },
38783         {
38784                 name:    "Lsh64x32",
38785                 auxType: auxBool,
38786                 argLen:  2,
38787                 generic: true,
38788         },
38789         {
38790                 name:    "Lsh64x64",
38791                 auxType: auxBool,
38792                 argLen:  2,
38793                 generic: true,
38794         },
38795         {
38796                 name:    "Rsh8x8",
38797                 auxType: auxBool,
38798                 argLen:  2,
38799                 generic: true,
38800         },
38801         {
38802                 name:    "Rsh8x16",
38803                 auxType: auxBool,
38804                 argLen:  2,
38805                 generic: true,
38806         },
38807         {
38808                 name:    "Rsh8x32",
38809                 auxType: auxBool,
38810                 argLen:  2,
38811                 generic: true,
38812         },
38813         {
38814                 name:    "Rsh8x64",
38815                 auxType: auxBool,
38816                 argLen:  2,
38817                 generic: true,
38818         },
38819         {
38820                 name:    "Rsh16x8",
38821                 auxType: auxBool,
38822                 argLen:  2,
38823                 generic: true,
38824         },
38825         {
38826                 name:    "Rsh16x16",
38827                 auxType: auxBool,
38828                 argLen:  2,
38829                 generic: true,
38830         },
38831         {
38832                 name:    "Rsh16x32",
38833                 auxType: auxBool,
38834                 argLen:  2,
38835                 generic: true,
38836         },
38837         {
38838                 name:    "Rsh16x64",
38839                 auxType: auxBool,
38840                 argLen:  2,
38841                 generic: true,
38842         },
38843         {
38844                 name:    "Rsh32x8",
38845                 auxType: auxBool,
38846                 argLen:  2,
38847                 generic: true,
38848         },
38849         {
38850                 name:    "Rsh32x16",
38851                 auxType: auxBool,
38852                 argLen:  2,
38853                 generic: true,
38854         },
38855         {
38856                 name:    "Rsh32x32",
38857                 auxType: auxBool,
38858                 argLen:  2,
38859                 generic: true,
38860         },
38861         {
38862                 name:    "Rsh32x64",
38863                 auxType: auxBool,
38864                 argLen:  2,
38865                 generic: true,
38866         },
38867         {
38868                 name:    "Rsh64x8",
38869                 auxType: auxBool,
38870                 argLen:  2,
38871                 generic: true,
38872         },
38873         {
38874                 name:    "Rsh64x16",
38875                 auxType: auxBool,
38876                 argLen:  2,
38877                 generic: true,
38878         },
38879         {
38880                 name:    "Rsh64x32",
38881                 auxType: auxBool,
38882                 argLen:  2,
38883                 generic: true,
38884         },
38885         {
38886                 name:    "Rsh64x64",
38887                 auxType: auxBool,
38888                 argLen:  2,
38889                 generic: true,
38890         },
38891         {
38892                 name:    "Rsh8Ux8",
38893                 auxType: auxBool,
38894                 argLen:  2,
38895                 generic: true,
38896         },
38897         {
38898                 name:    "Rsh8Ux16",
38899                 auxType: auxBool,
38900                 argLen:  2,
38901                 generic: true,
38902         },
38903         {
38904                 name:    "Rsh8Ux32",
38905                 auxType: auxBool,
38906                 argLen:  2,
38907                 generic: true,
38908         },
38909         {
38910                 name:    "Rsh8Ux64",
38911                 auxType: auxBool,
38912                 argLen:  2,
38913                 generic: true,
38914         },
38915         {
38916                 name:    "Rsh16Ux8",
38917                 auxType: auxBool,
38918                 argLen:  2,
38919                 generic: true,
38920         },
38921         {
38922                 name:    "Rsh16Ux16",
38923                 auxType: auxBool,
38924                 argLen:  2,
38925                 generic: true,
38926         },
38927         {
38928                 name:    "Rsh16Ux32",
38929                 auxType: auxBool,
38930                 argLen:  2,
38931                 generic: true,
38932         },
38933         {
38934                 name:    "Rsh16Ux64",
38935                 auxType: auxBool,
38936                 argLen:  2,
38937                 generic: true,
38938         },
38939         {
38940                 name:    "Rsh32Ux8",
38941                 auxType: auxBool,
38942                 argLen:  2,
38943                 generic: true,
38944         },
38945         {
38946                 name:    "Rsh32Ux16",
38947                 auxType: auxBool,
38948                 argLen:  2,
38949                 generic: true,
38950         },
38951         {
38952                 name:    "Rsh32Ux32",
38953                 auxType: auxBool,
38954                 argLen:  2,
38955                 generic: true,
38956         },
38957         {
38958                 name:    "Rsh32Ux64",
38959                 auxType: auxBool,
38960                 argLen:  2,
38961                 generic: true,
38962         },
38963         {
38964                 name:    "Rsh64Ux8",
38965                 auxType: auxBool,
38966                 argLen:  2,
38967                 generic: true,
38968         },
38969         {
38970                 name:    "Rsh64Ux16",
38971                 auxType: auxBool,
38972                 argLen:  2,
38973                 generic: true,
38974         },
38975         {
38976                 name:    "Rsh64Ux32",
38977                 auxType: auxBool,
38978                 argLen:  2,
38979                 generic: true,
38980         },
38981         {
38982                 name:    "Rsh64Ux64",
38983                 auxType: auxBool,
38984                 argLen:  2,
38985                 generic: true,
38986         },
38987         {
38988                 name:        "Eq8",
38989                 argLen:      2,
38990                 commutative: true,
38991                 generic:     true,
38992         },
38993         {
38994                 name:        "Eq16",
38995                 argLen:      2,
38996                 commutative: true,
38997                 generic:     true,
38998         },
38999         {
39000                 name:        "Eq32",
39001                 argLen:      2,
39002                 commutative: true,
39003                 generic:     true,
39004         },
39005         {
39006                 name:        "Eq64",
39007                 argLen:      2,
39008                 commutative: true,
39009                 generic:     true,
39010         },
39011         {
39012                 name:        "EqPtr",
39013                 argLen:      2,
39014                 commutative: true,
39015                 generic:     true,
39016         },
39017         {
39018                 name:    "EqInter",
39019                 argLen:  2,
39020                 generic: true,
39021         },
39022         {
39023                 name:    "EqSlice",
39024                 argLen:  2,
39025                 generic: true,
39026         },
39027         {
39028                 name:        "Eq32F",
39029                 argLen:      2,
39030                 commutative: true,
39031                 generic:     true,
39032         },
39033         {
39034                 name:        "Eq64F",
39035                 argLen:      2,
39036                 commutative: true,
39037                 generic:     true,
39038         },
39039         {
39040                 name:        "Neq8",
39041                 argLen:      2,
39042                 commutative: true,
39043                 generic:     true,
39044         },
39045         {
39046                 name:        "Neq16",
39047                 argLen:      2,
39048                 commutative: true,
39049                 generic:     true,
39050         },
39051         {
39052                 name:        "Neq32",
39053                 argLen:      2,
39054                 commutative: true,
39055                 generic:     true,
39056         },
39057         {
39058                 name:        "Neq64",
39059                 argLen:      2,
39060                 commutative: true,
39061                 generic:     true,
39062         },
39063         {
39064                 name:        "NeqPtr",
39065                 argLen:      2,
39066                 commutative: true,
39067                 generic:     true,
39068         },
39069         {
39070                 name:    "NeqInter",
39071                 argLen:  2,
39072                 generic: true,
39073         },
39074         {
39075                 name:    "NeqSlice",
39076                 argLen:  2,
39077                 generic: true,
39078         },
39079         {
39080                 name:        "Neq32F",
39081                 argLen:      2,
39082                 commutative: true,
39083                 generic:     true,
39084         },
39085         {
39086                 name:        "Neq64F",
39087                 argLen:      2,
39088                 commutative: true,
39089                 generic:     true,
39090         },
39091         {
39092                 name:    "Less8",
39093                 argLen:  2,
39094                 generic: true,
39095         },
39096         {
39097                 name:    "Less8U",
39098                 argLen:  2,
39099                 generic: true,
39100         },
39101         {
39102                 name:    "Less16",
39103                 argLen:  2,
39104                 generic: true,
39105         },
39106         {
39107                 name:    "Less16U",
39108                 argLen:  2,
39109                 generic: true,
39110         },
39111         {
39112                 name:    "Less32",
39113                 argLen:  2,
39114                 generic: true,
39115         },
39116         {
39117                 name:    "Less32U",
39118                 argLen:  2,
39119                 generic: true,
39120         },
39121         {
39122                 name:    "Less64",
39123                 argLen:  2,
39124                 generic: true,
39125         },
39126         {
39127                 name:    "Less64U",
39128                 argLen:  2,
39129                 generic: true,
39130         },
39131         {
39132                 name:    "Less32F",
39133                 argLen:  2,
39134                 generic: true,
39135         },
39136         {
39137                 name:    "Less64F",
39138                 argLen:  2,
39139                 generic: true,
39140         },
39141         {
39142                 name:    "Leq8",
39143                 argLen:  2,
39144                 generic: true,
39145         },
39146         {
39147                 name:    "Leq8U",
39148                 argLen:  2,
39149                 generic: true,
39150         },
39151         {
39152                 name:    "Leq16",
39153                 argLen:  2,
39154                 generic: true,
39155         },
39156         {
39157                 name:    "Leq16U",
39158                 argLen:  2,
39159                 generic: true,
39160         },
39161         {
39162                 name:    "Leq32",
39163                 argLen:  2,
39164                 generic: true,
39165         },
39166         {
39167                 name:    "Leq32U",
39168                 argLen:  2,
39169                 generic: true,
39170         },
39171         {
39172                 name:    "Leq64",
39173                 argLen:  2,
39174                 generic: true,
39175         },
39176         {
39177                 name:    "Leq64U",
39178                 argLen:  2,
39179                 generic: true,
39180         },
39181         {
39182                 name:    "Leq32F",
39183                 argLen:  2,
39184                 generic: true,
39185         },
39186         {
39187                 name:    "Leq64F",
39188                 argLen:  2,
39189                 generic: true,
39190         },
39191         {
39192                 name:    "CondSelect",
39193                 argLen:  3,
39194                 generic: true,
39195         },
39196         {
39197                 name:        "AndB",
39198                 argLen:      2,
39199                 commutative: true,
39200                 generic:     true,
39201         },
39202         {
39203                 name:        "OrB",
39204                 argLen:      2,
39205                 commutative: true,
39206                 generic:     true,
39207         },
39208         {
39209                 name:        "EqB",
39210                 argLen:      2,
39211                 commutative: true,
39212                 generic:     true,
39213         },
39214         {
39215                 name:        "NeqB",
39216                 argLen:      2,
39217                 commutative: true,
39218                 generic:     true,
39219         },
39220         {
39221                 name:    "Not",
39222                 argLen:  1,
39223                 generic: true,
39224         },
39225         {
39226                 name:    "Neg8",
39227                 argLen:  1,
39228                 generic: true,
39229         },
39230         {
39231                 name:    "Neg16",
39232                 argLen:  1,
39233                 generic: true,
39234         },
39235         {
39236                 name:    "Neg32",
39237                 argLen:  1,
39238                 generic: true,
39239         },
39240         {
39241                 name:    "Neg64",
39242                 argLen:  1,
39243                 generic: true,
39244         },
39245         {
39246                 name:    "Neg32F",
39247                 argLen:  1,
39248                 generic: true,
39249         },
39250         {
39251                 name:    "Neg64F",
39252                 argLen:  1,
39253                 generic: true,
39254         },
39255         {
39256                 name:    "Com8",
39257                 argLen:  1,
39258                 generic: true,
39259         },
39260         {
39261                 name:    "Com16",
39262                 argLen:  1,
39263                 generic: true,
39264         },
39265         {
39266                 name:    "Com32",
39267                 argLen:  1,
39268                 generic: true,
39269         },
39270         {
39271                 name:    "Com64",
39272                 argLen:  1,
39273                 generic: true,
39274         },
39275         {
39276                 name:    "Ctz8",
39277                 argLen:  1,
39278                 generic: true,
39279         },
39280         {
39281                 name:    "Ctz16",
39282                 argLen:  1,
39283                 generic: true,
39284         },
39285         {
39286                 name:    "Ctz32",
39287                 argLen:  1,
39288                 generic: true,
39289         },
39290         {
39291                 name:    "Ctz64",
39292                 argLen:  1,
39293                 generic: true,
39294         },
39295         {
39296                 name:    "Ctz8NonZero",
39297                 argLen:  1,
39298                 generic: true,
39299         },
39300         {
39301                 name:    "Ctz16NonZero",
39302                 argLen:  1,
39303                 generic: true,
39304         },
39305         {
39306                 name:    "Ctz32NonZero",
39307                 argLen:  1,
39308                 generic: true,
39309         },
39310         {
39311                 name:    "Ctz64NonZero",
39312                 argLen:  1,
39313                 generic: true,
39314         },
39315         {
39316                 name:    "BitLen8",
39317                 argLen:  1,
39318                 generic: true,
39319         },
39320         {
39321                 name:    "BitLen16",
39322                 argLen:  1,
39323                 generic: true,
39324         },
39325         {
39326                 name:    "BitLen32",
39327                 argLen:  1,
39328                 generic: true,
39329         },
39330         {
39331                 name:    "BitLen64",
39332                 argLen:  1,
39333                 generic: true,
39334         },
39335         {
39336                 name:    "Bswap16",
39337                 argLen:  1,
39338                 generic: true,
39339         },
39340         {
39341                 name:    "Bswap32",
39342                 argLen:  1,
39343                 generic: true,
39344         },
39345         {
39346                 name:    "Bswap64",
39347                 argLen:  1,
39348                 generic: true,
39349         },
39350         {
39351                 name:    "BitRev8",
39352                 argLen:  1,
39353                 generic: true,
39354         },
39355         {
39356                 name:    "BitRev16",
39357                 argLen:  1,
39358                 generic: true,
39359         },
39360         {
39361                 name:    "BitRev32",
39362                 argLen:  1,
39363                 generic: true,
39364         },
39365         {
39366                 name:    "BitRev64",
39367                 argLen:  1,
39368                 generic: true,
39369         },
39370         {
39371                 name:    "PopCount8",
39372                 argLen:  1,
39373                 generic: true,
39374         },
39375         {
39376                 name:    "PopCount16",
39377                 argLen:  1,
39378                 generic: true,
39379         },
39380         {
39381                 name:    "PopCount32",
39382                 argLen:  1,
39383                 generic: true,
39384         },
39385         {
39386                 name:    "PopCount64",
39387                 argLen:  1,
39388                 generic: true,
39389         },
39390         {
39391                 name:    "RotateLeft64",
39392                 argLen:  2,
39393                 generic: true,
39394         },
39395         {
39396                 name:    "RotateLeft32",
39397                 argLen:  2,
39398                 generic: true,
39399         },
39400         {
39401                 name:    "RotateLeft16",
39402                 argLen:  2,
39403                 generic: true,
39404         },
39405         {
39406                 name:    "RotateLeft8",
39407                 argLen:  2,
39408                 generic: true,
39409         },
39410         {
39411                 name:    "Sqrt",
39412                 argLen:  1,
39413                 generic: true,
39414         },
39415         {
39416                 name:    "Sqrt32",
39417                 argLen:  1,
39418                 generic: true,
39419         },
39420         {
39421                 name:    "Floor",
39422                 argLen:  1,
39423                 generic: true,
39424         },
39425         {
39426                 name:    "Ceil",
39427                 argLen:  1,
39428                 generic: true,
39429         },
39430         {
39431                 name:    "Trunc",
39432                 argLen:  1,
39433                 generic: true,
39434         },
39435         {
39436                 name:    "Round",
39437                 argLen:  1,
39438                 generic: true,
39439         },
39440         {
39441                 name:    "RoundToEven",
39442                 argLen:  1,
39443                 generic: true,
39444         },
39445         {
39446                 name:    "Abs",
39447                 argLen:  1,
39448                 generic: true,
39449         },
39450         {
39451                 name:    "Copysign",
39452                 argLen:  2,
39453                 generic: true,
39454         },
39455         {
39456                 name:    "Min64F",
39457                 argLen:  2,
39458                 generic: true,
39459         },
39460         {
39461                 name:    "Min32F",
39462                 argLen:  2,
39463                 generic: true,
39464         },
39465         {
39466                 name:    "Max64F",
39467                 argLen:  2,
39468                 generic: true,
39469         },
39470         {
39471                 name:    "Max32F",
39472                 argLen:  2,
39473                 generic: true,
39474         },
39475         {
39476                 name:    "FMA",
39477                 argLen:  3,
39478                 generic: true,
39479         },
39480         {
39481                 name:      "Phi",
39482                 argLen:    -1,
39483                 zeroWidth: true,
39484                 generic:   true,
39485         },
39486         {
39487                 name:    "Copy",
39488                 argLen:  1,
39489                 generic: true,
39490         },
39491         {
39492                 name:         "Convert",
39493                 argLen:       2,
39494                 resultInArg0: true,
39495                 zeroWidth:    true,
39496                 generic:      true,
39497         },
39498         {
39499                 name:    "ConstBool",
39500                 auxType: auxBool,
39501                 argLen:  0,
39502                 generic: true,
39503         },
39504         {
39505                 name:    "ConstString",
39506                 auxType: auxString,
39507                 argLen:  0,
39508                 generic: true,
39509         },
39510         {
39511                 name:    "ConstNil",
39512                 argLen:  0,
39513                 generic: true,
39514         },
39515         {
39516                 name:    "Const8",
39517                 auxType: auxInt8,
39518                 argLen:  0,
39519                 generic: true,
39520         },
39521         {
39522                 name:    "Const16",
39523                 auxType: auxInt16,
39524                 argLen:  0,
39525                 generic: true,
39526         },
39527         {
39528                 name:    "Const32",
39529                 auxType: auxInt32,
39530                 argLen:  0,
39531                 generic: true,
39532         },
39533         {
39534                 name:    "Const64",
39535                 auxType: auxInt64,
39536                 argLen:  0,
39537                 generic: true,
39538         },
39539         {
39540                 name:    "Const32F",
39541                 auxType: auxFloat32,
39542                 argLen:  0,
39543                 generic: true,
39544         },
39545         {
39546                 name:    "Const64F",
39547                 auxType: auxFloat64,
39548                 argLen:  0,
39549                 generic: true,
39550         },
39551         {
39552                 name:    "ConstInterface",
39553                 argLen:  0,
39554                 generic: true,
39555         },
39556         {
39557                 name:    "ConstSlice",
39558                 argLen:  0,
39559                 generic: true,
39560         },
39561         {
39562                 name:      "InitMem",
39563                 argLen:    0,
39564                 zeroWidth: true,
39565                 generic:   true,
39566         },
39567         {
39568                 name:      "Arg",
39569                 auxType:   auxSymOff,
39570                 argLen:    0,
39571                 zeroWidth: true,
39572                 symEffect: SymRead,
39573                 generic:   true,
39574         },
39575         {
39576                 name:      "ArgIntReg",
39577                 auxType:   auxNameOffsetInt8,
39578                 argLen:    0,
39579                 zeroWidth: true,
39580                 generic:   true,
39581         },
39582         {
39583                 name:      "ArgFloatReg",
39584                 auxType:   auxNameOffsetInt8,
39585                 argLen:    0,
39586                 zeroWidth: true,
39587                 generic:   true,
39588         },
39589         {
39590                 name:      "Addr",
39591                 auxType:   auxSym,
39592                 argLen:    1,
39593                 symEffect: SymAddr,
39594                 generic:   true,
39595         },
39596         {
39597                 name:      "LocalAddr",
39598                 auxType:   auxSym,
39599                 argLen:    2,
39600                 symEffect: SymAddr,
39601                 generic:   true,
39602         },
39603         {
39604                 name:      "SP",
39605                 argLen:    0,
39606                 zeroWidth: true,
39607                 generic:   true,
39608         },
39609         {
39610                 name:      "SB",
39611                 argLen:    0,
39612                 zeroWidth: true,
39613                 generic:   true,
39614         },
39615         {
39616                 name:      "SPanchored",
39617                 argLen:    2,
39618                 zeroWidth: true,
39619                 generic:   true,
39620         },
39621         {
39622                 name:    "Load",
39623                 argLen:  2,
39624                 generic: true,
39625         },
39626         {
39627                 name:    "Dereference",
39628                 argLen:  2,
39629                 generic: true,
39630         },
39631         {
39632                 name:    "Store",
39633                 auxType: auxTyp,
39634                 argLen:  3,
39635                 generic: true,
39636         },
39637         {
39638                 name:    "Move",
39639                 auxType: auxTypSize,
39640                 argLen:  3,
39641                 generic: true,
39642         },
39643         {
39644                 name:    "Zero",
39645                 auxType: auxTypSize,
39646                 argLen:  2,
39647                 generic: true,
39648         },
39649         {
39650                 name:    "StoreWB",
39651                 auxType: auxTyp,
39652                 argLen:  3,
39653                 generic: true,
39654         },
39655         {
39656                 name:    "MoveWB",
39657                 auxType: auxTypSize,
39658                 argLen:  3,
39659                 generic: true,
39660         },
39661         {
39662                 name:    "ZeroWB",
39663                 auxType: auxTypSize,
39664                 argLen:  2,
39665                 generic: true,
39666         },
39667         {
39668                 name:    "WBend",
39669                 argLen:  1,
39670                 generic: true,
39671         },
39672         {
39673                 name:    "WB",
39674                 auxType: auxInt64,
39675                 argLen:  1,
39676                 generic: true,
39677         },
39678         {
39679                 name:      "HasCPUFeature",
39680                 auxType:   auxSym,
39681                 argLen:    0,
39682                 symEffect: SymNone,
39683                 generic:   true,
39684         },
39685         {
39686                 name:    "PanicBounds",
39687                 auxType: auxInt64,
39688                 argLen:  3,
39689                 call:    true,
39690                 generic: true,
39691         },
39692         {
39693                 name:    "PanicExtend",
39694                 auxType: auxInt64,
39695                 argLen:  4,
39696                 call:    true,
39697                 generic: true,
39698         },
39699         {
39700                 name:    "ClosureCall",
39701                 auxType: auxCallOff,
39702                 argLen:  -1,
39703                 call:    true,
39704                 generic: true,
39705         },
39706         {
39707                 name:    "StaticCall",
39708                 auxType: auxCallOff,
39709                 argLen:  -1,
39710                 call:    true,
39711                 generic: true,
39712         },
39713         {
39714                 name:    "InterCall",
39715                 auxType: auxCallOff,
39716                 argLen:  -1,
39717                 call:    true,
39718                 generic: true,
39719         },
39720         {
39721                 name:    "TailCall",
39722                 auxType: auxCallOff,
39723                 argLen:  -1,
39724                 call:    true,
39725                 generic: true,
39726         },
39727         {
39728                 name:    "ClosureLECall",
39729                 auxType: auxCallOff,
39730                 argLen:  -1,
39731                 call:    true,
39732                 generic: true,
39733         },
39734         {
39735                 name:    "StaticLECall",
39736                 auxType: auxCallOff,
39737                 argLen:  -1,
39738                 call:    true,
39739                 generic: true,
39740         },
39741         {
39742                 name:    "InterLECall",
39743                 auxType: auxCallOff,
39744                 argLen:  -1,
39745                 call:    true,
39746                 generic: true,
39747         },
39748         {
39749                 name:    "TailLECall",
39750                 auxType: auxCallOff,
39751                 argLen:  -1,
39752                 call:    true,
39753                 generic: true,
39754         },
39755         {
39756                 name:    "SignExt8to16",
39757                 argLen:  1,
39758                 generic: true,
39759         },
39760         {
39761                 name:    "SignExt8to32",
39762                 argLen:  1,
39763                 generic: true,
39764         },
39765         {
39766                 name:    "SignExt8to64",
39767                 argLen:  1,
39768                 generic: true,
39769         },
39770         {
39771                 name:    "SignExt16to32",
39772                 argLen:  1,
39773                 generic: true,
39774         },
39775         {
39776                 name:    "SignExt16to64",
39777                 argLen:  1,
39778                 generic: true,
39779         },
39780         {
39781                 name:    "SignExt32to64",
39782                 argLen:  1,
39783                 generic: true,
39784         },
39785         {
39786                 name:    "ZeroExt8to16",
39787                 argLen:  1,
39788                 generic: true,
39789         },
39790         {
39791                 name:    "ZeroExt8to32",
39792                 argLen:  1,
39793                 generic: true,
39794         },
39795         {
39796                 name:    "ZeroExt8to64",
39797                 argLen:  1,
39798                 generic: true,
39799         },
39800         {
39801                 name:    "ZeroExt16to32",
39802                 argLen:  1,
39803                 generic: true,
39804         },
39805         {
39806                 name:    "ZeroExt16to64",
39807                 argLen:  1,
39808                 generic: true,
39809         },
39810         {
39811                 name:    "ZeroExt32to64",
39812                 argLen:  1,
39813                 generic: true,
39814         },
39815         {
39816                 name:    "Trunc16to8",
39817                 argLen:  1,
39818                 generic: true,
39819         },
39820         {
39821                 name:    "Trunc32to8",
39822                 argLen:  1,
39823                 generic: true,
39824         },
39825         {
39826                 name:    "Trunc32to16",
39827                 argLen:  1,
39828                 generic: true,
39829         },
39830         {
39831                 name:    "Trunc64to8",
39832                 argLen:  1,
39833                 generic: true,
39834         },
39835         {
39836                 name:    "Trunc64to16",
39837                 argLen:  1,
39838                 generic: true,
39839         },
39840         {
39841                 name:    "Trunc64to32",
39842                 argLen:  1,
39843                 generic: true,
39844         },
39845         {
39846                 name:    "Cvt32to32F",
39847                 argLen:  1,
39848                 generic: true,
39849         },
39850         {
39851                 name:    "Cvt32to64F",
39852                 argLen:  1,
39853                 generic: true,
39854         },
39855         {
39856                 name:    "Cvt64to32F",
39857                 argLen:  1,
39858                 generic: true,
39859         },
39860         {
39861                 name:    "Cvt64to64F",
39862                 argLen:  1,
39863                 generic: true,
39864         },
39865         {
39866                 name:    "Cvt32Fto32",
39867                 argLen:  1,
39868                 generic: true,
39869         },
39870         {
39871                 name:    "Cvt32Fto64",
39872                 argLen:  1,
39873                 generic: true,
39874         },
39875         {
39876                 name:    "Cvt64Fto32",
39877                 argLen:  1,
39878                 generic: true,
39879         },
39880         {
39881                 name:    "Cvt64Fto64",
39882                 argLen:  1,
39883                 generic: true,
39884         },
39885         {
39886                 name:    "Cvt32Fto64F",
39887                 argLen:  1,
39888                 generic: true,
39889         },
39890         {
39891                 name:    "Cvt64Fto32F",
39892                 argLen:  1,
39893                 generic: true,
39894         },
39895         {
39896                 name:    "CvtBoolToUint8",
39897                 argLen:  1,
39898                 generic: true,
39899         },
39900         {
39901                 name:    "Round32F",
39902                 argLen:  1,
39903                 generic: true,
39904         },
39905         {
39906                 name:    "Round64F",
39907                 argLen:  1,
39908                 generic: true,
39909         },
39910         {
39911                 name:    "IsNonNil",
39912                 argLen:  1,
39913                 generic: true,
39914         },
39915         {
39916                 name:    "IsInBounds",
39917                 argLen:  2,
39918                 generic: true,
39919         },
39920         {
39921                 name:    "IsSliceInBounds",
39922                 argLen:  2,
39923                 generic: true,
39924         },
39925         {
39926                 name:     "NilCheck",
39927                 argLen:   2,
39928                 nilCheck: true,
39929                 generic:  true,
39930         },
39931         {
39932                 name:      "GetG",
39933                 argLen:    1,
39934                 zeroWidth: true,
39935                 generic:   true,
39936         },
39937         {
39938                 name:    "GetClosurePtr",
39939                 argLen:  0,
39940                 generic: true,
39941         },
39942         {
39943                 name:    "GetCallerPC",
39944                 argLen:  0,
39945                 generic: true,
39946         },
39947         {
39948                 name:    "GetCallerSP",
39949                 argLen:  1,
39950                 generic: true,
39951         },
39952         {
39953                 name:    "PtrIndex",
39954                 argLen:  2,
39955                 generic: true,
39956         },
39957         {
39958                 name:    "OffPtr",
39959                 auxType: auxInt64,
39960                 argLen:  1,
39961                 generic: true,
39962         },
39963         {
39964                 name:    "SliceMake",
39965                 argLen:  3,
39966                 generic: true,
39967         },
39968         {
39969                 name:    "SlicePtr",
39970                 argLen:  1,
39971                 generic: true,
39972         },
39973         {
39974                 name:    "SliceLen",
39975                 argLen:  1,
39976                 generic: true,
39977         },
39978         {
39979                 name:    "SliceCap",
39980                 argLen:  1,
39981                 generic: true,
39982         },
39983         {
39984                 name:    "SlicePtrUnchecked",
39985                 argLen:  1,
39986                 generic: true,
39987         },
39988         {
39989                 name:    "ComplexMake",
39990                 argLen:  2,
39991                 generic: true,
39992         },
39993         {
39994                 name:    "ComplexReal",
39995                 argLen:  1,
39996                 generic: true,
39997         },
39998         {
39999                 name:    "ComplexImag",
40000                 argLen:  1,
40001                 generic: true,
40002         },
40003         {
40004                 name:    "StringMake",
40005                 argLen:  2,
40006                 generic: true,
40007         },
40008         {
40009                 name:    "StringPtr",
40010                 argLen:  1,
40011                 generic: true,
40012         },
40013         {
40014                 name:    "StringLen",
40015                 argLen:  1,
40016                 generic: true,
40017         },
40018         {
40019                 name:    "IMake",
40020                 argLen:  2,
40021                 generic: true,
40022         },
40023         {
40024                 name:    "ITab",
40025                 argLen:  1,
40026                 generic: true,
40027         },
40028         {
40029                 name:    "IData",
40030                 argLen:  1,
40031                 generic: true,
40032         },
40033         {
40034                 name:    "StructMake0",
40035                 argLen:  0,
40036                 generic: true,
40037         },
40038         {
40039                 name:    "StructMake1",
40040                 argLen:  1,
40041                 generic: true,
40042         },
40043         {
40044                 name:    "StructMake2",
40045                 argLen:  2,
40046                 generic: true,
40047         },
40048         {
40049                 name:    "StructMake3",
40050                 argLen:  3,
40051                 generic: true,
40052         },
40053         {
40054                 name:    "StructMake4",
40055                 argLen:  4,
40056                 generic: true,
40057         },
40058         {
40059                 name:    "StructSelect",
40060                 auxType: auxInt64,
40061                 argLen:  1,
40062                 generic: true,
40063         },
40064         {
40065                 name:    "ArrayMake0",
40066                 argLen:  0,
40067                 generic: true,
40068         },
40069         {
40070                 name:    "ArrayMake1",
40071                 argLen:  1,
40072                 generic: true,
40073         },
40074         {
40075                 name:    "ArraySelect",
40076                 auxType: auxInt64,
40077                 argLen:  1,
40078                 generic: true,
40079         },
40080         {
40081                 name:    "StoreReg",
40082                 argLen:  1,
40083                 generic: true,
40084         },
40085         {
40086                 name:    "LoadReg",
40087                 argLen:  1,
40088                 generic: true,
40089         },
40090         {
40091                 name:      "FwdRef",
40092                 auxType:   auxSym,
40093                 argLen:    0,
40094                 symEffect: SymNone,
40095                 generic:   true,
40096         },
40097         {
40098                 name:    "Unknown",
40099                 argLen:  0,
40100                 generic: true,
40101         },
40102         {
40103                 name:      "VarDef",
40104                 auxType:   auxSym,
40105                 argLen:    1,
40106                 zeroWidth: true,
40107                 symEffect: SymNone,
40108                 generic:   true,
40109         },
40110         {
40111                 name:      "VarLive",
40112                 auxType:   auxSym,
40113                 argLen:    1,
40114                 zeroWidth: true,
40115                 symEffect: SymRead,
40116                 generic:   true,
40117         },
40118         {
40119                 name:      "KeepAlive",
40120                 argLen:    2,
40121                 zeroWidth: true,
40122                 generic:   true,
40123         },
40124         {
40125                 name:    "InlMark",
40126                 auxType: auxInt32,
40127                 argLen:  1,
40128                 generic: true,
40129         },
40130         {
40131                 name:    "Int64Make",
40132                 argLen:  2,
40133                 generic: true,
40134         },
40135         {
40136                 name:    "Int64Hi",
40137                 argLen:  1,
40138                 generic: true,
40139         },
40140         {
40141                 name:    "Int64Lo",
40142                 argLen:  1,
40143                 generic: true,
40144         },
40145         {
40146                 name:        "Add32carry",
40147                 argLen:      2,
40148                 commutative: true,
40149                 generic:     true,
40150         },
40151         {
40152                 name:        "Add32withcarry",
40153                 argLen:      3,
40154                 commutative: true,
40155                 generic:     true,
40156         },
40157         {
40158                 name:    "Sub32carry",
40159                 argLen:  2,
40160                 generic: true,
40161         },
40162         {
40163                 name:    "Sub32withcarry",
40164                 argLen:  3,
40165                 generic: true,
40166         },
40167         {
40168                 name:        "Add64carry",
40169                 argLen:      3,
40170                 commutative: true,
40171                 generic:     true,
40172         },
40173         {
40174                 name:    "Sub64borrow",
40175                 argLen:  3,
40176                 generic: true,
40177         },
40178         {
40179                 name:    "Signmask",
40180                 argLen:  1,
40181                 generic: true,
40182         },
40183         {
40184                 name:    "Zeromask",
40185                 argLen:  1,
40186                 generic: true,
40187         },
40188         {
40189                 name:    "Slicemask",
40190                 argLen:  1,
40191                 generic: true,
40192         },
40193         {
40194                 name:    "SpectreIndex",
40195                 argLen:  2,
40196                 generic: true,
40197         },
40198         {
40199                 name:    "SpectreSliceIndex",
40200                 argLen:  2,
40201                 generic: true,
40202         },
40203         {
40204                 name:    "Cvt32Uto32F",
40205                 argLen:  1,
40206                 generic: true,
40207         },
40208         {
40209                 name:    "Cvt32Uto64F",
40210                 argLen:  1,
40211                 generic: true,
40212         },
40213         {
40214                 name:    "Cvt32Fto32U",
40215                 argLen:  1,
40216                 generic: true,
40217         },
40218         {
40219                 name:    "Cvt64Fto32U",
40220                 argLen:  1,
40221                 generic: true,
40222         },
40223         {
40224                 name:    "Cvt64Uto32F",
40225                 argLen:  1,
40226                 generic: true,
40227         },
40228         {
40229                 name:    "Cvt64Uto64F",
40230                 argLen:  1,
40231                 generic: true,
40232         },
40233         {
40234                 name:    "Cvt32Fto64U",
40235                 argLen:  1,
40236                 generic: true,
40237         },
40238         {
40239                 name:    "Cvt64Fto64U",
40240                 argLen:  1,
40241                 generic: true,
40242         },
40243         {
40244                 name:      "Select0",
40245                 argLen:    1,
40246                 zeroWidth: true,
40247                 generic:   true,
40248         },
40249         {
40250                 name:      "Select1",
40251                 argLen:    1,
40252                 zeroWidth: true,
40253                 generic:   true,
40254         },
40255         {
40256                 name:    "SelectN",
40257                 auxType: auxInt64,
40258                 argLen:  1,
40259                 generic: true,
40260         },
40261         {
40262                 name:    "SelectNAddr",
40263                 auxType: auxInt64,
40264                 argLen:  1,
40265                 generic: true,
40266         },
40267         {
40268                 name:    "MakeResult",
40269                 argLen:  -1,
40270                 generic: true,
40271         },
40272         {
40273                 name:    "AtomicLoad8",
40274                 argLen:  2,
40275                 generic: true,
40276         },
40277         {
40278                 name:    "AtomicLoad32",
40279                 argLen:  2,
40280                 generic: true,
40281         },
40282         {
40283                 name:    "AtomicLoad64",
40284                 argLen:  2,
40285                 generic: true,
40286         },
40287         {
40288                 name:    "AtomicLoadPtr",
40289                 argLen:  2,
40290                 generic: true,
40291         },
40292         {
40293                 name:    "AtomicLoadAcq32",
40294                 argLen:  2,
40295                 generic: true,
40296         },
40297         {
40298                 name:    "AtomicLoadAcq64",
40299                 argLen:  2,
40300                 generic: true,
40301         },
40302         {
40303                 name:           "AtomicStore8",
40304                 argLen:         3,
40305                 hasSideEffects: true,
40306                 generic:        true,
40307         },
40308         {
40309                 name:           "AtomicStore32",
40310                 argLen:         3,
40311                 hasSideEffects: true,
40312                 generic:        true,
40313         },
40314         {
40315                 name:           "AtomicStore64",
40316                 argLen:         3,
40317                 hasSideEffects: true,
40318                 generic:        true,
40319         },
40320         {
40321                 name:           "AtomicStorePtrNoWB",
40322                 argLen:         3,
40323                 hasSideEffects: true,
40324                 generic:        true,
40325         },
40326         {
40327                 name:           "AtomicStoreRel32",
40328                 argLen:         3,
40329                 hasSideEffects: true,
40330                 generic:        true,
40331         },
40332         {
40333                 name:           "AtomicStoreRel64",
40334                 argLen:         3,
40335                 hasSideEffects: true,
40336                 generic:        true,
40337         },
40338         {
40339                 name:           "AtomicExchange32",
40340                 argLen:         3,
40341                 hasSideEffects: true,
40342                 generic:        true,
40343         },
40344         {
40345                 name:           "AtomicExchange64",
40346                 argLen:         3,
40347                 hasSideEffects: true,
40348                 generic:        true,
40349         },
40350         {
40351                 name:           "AtomicAdd32",
40352                 argLen:         3,
40353                 hasSideEffects: true,
40354                 generic:        true,
40355         },
40356         {
40357                 name:           "AtomicAdd64",
40358                 argLen:         3,
40359                 hasSideEffects: true,
40360                 generic:        true,
40361         },
40362         {
40363                 name:           "AtomicCompareAndSwap32",
40364                 argLen:         4,
40365                 hasSideEffects: true,
40366                 generic:        true,
40367         },
40368         {
40369                 name:           "AtomicCompareAndSwap64",
40370                 argLen:         4,
40371                 hasSideEffects: true,
40372                 generic:        true,
40373         },
40374         {
40375                 name:           "AtomicCompareAndSwapRel32",
40376                 argLen:         4,
40377                 hasSideEffects: true,
40378                 generic:        true,
40379         },
40380         {
40381                 name:           "AtomicAnd8",
40382                 argLen:         3,
40383                 hasSideEffects: true,
40384                 generic:        true,
40385         },
40386         {
40387                 name:           "AtomicAnd32",
40388                 argLen:         3,
40389                 hasSideEffects: true,
40390                 generic:        true,
40391         },
40392         {
40393                 name:           "AtomicOr8",
40394                 argLen:         3,
40395                 hasSideEffects: true,
40396                 generic:        true,
40397         },
40398         {
40399                 name:           "AtomicOr32",
40400                 argLen:         3,
40401                 hasSideEffects: true,
40402                 generic:        true,
40403         },
40404         {
40405                 name:           "AtomicAdd32Variant",
40406                 argLen:         3,
40407                 hasSideEffects: true,
40408                 generic:        true,
40409         },
40410         {
40411                 name:           "AtomicAdd64Variant",
40412                 argLen:         3,
40413                 hasSideEffects: true,
40414                 generic:        true,
40415         },
40416         {
40417                 name:           "AtomicExchange32Variant",
40418                 argLen:         3,
40419                 hasSideEffects: true,
40420                 generic:        true,
40421         },
40422         {
40423                 name:           "AtomicExchange64Variant",
40424                 argLen:         3,
40425                 hasSideEffects: true,
40426                 generic:        true,
40427         },
40428         {
40429                 name:           "AtomicCompareAndSwap32Variant",
40430                 argLen:         4,
40431                 hasSideEffects: true,
40432                 generic:        true,
40433         },
40434         {
40435                 name:           "AtomicCompareAndSwap64Variant",
40436                 argLen:         4,
40437                 hasSideEffects: true,
40438                 generic:        true,
40439         },
40440         {
40441                 name:           "AtomicAnd8Variant",
40442                 argLen:         3,
40443                 hasSideEffects: true,
40444                 generic:        true,
40445         },
40446         {
40447                 name:           "AtomicAnd32Variant",
40448                 argLen:         3,
40449                 hasSideEffects: true,
40450                 generic:        true,
40451         },
40452         {
40453                 name:           "AtomicOr8Variant",
40454                 argLen:         3,
40455                 hasSideEffects: true,
40456                 generic:        true,
40457         },
40458         {
40459                 name:           "AtomicOr32Variant",
40460                 argLen:         3,
40461                 hasSideEffects: true,
40462                 generic:        true,
40463         },
40464         {
40465                 name:           "PubBarrier",
40466                 argLen:         1,
40467                 hasSideEffects: true,
40468                 generic:        true,
40469         },
40470         {
40471                 name:      "Clobber",
40472                 auxType:   auxSymOff,
40473                 argLen:    0,
40474                 symEffect: SymNone,
40475                 generic:   true,
40476         },
40477         {
40478                 name:    "ClobberReg",
40479                 argLen:  0,
40480                 generic: true,
40481         },
40482         {
40483                 name:           "PrefetchCache",
40484                 argLen:         2,
40485                 hasSideEffects: true,
40486                 generic:        true,
40487         },
40488         {
40489                 name:           "PrefetchCacheStreamed",
40490                 argLen:         2,
40491                 hasSideEffects: true,
40492                 generic:        true,
40493         },
40494 }
40495
40496 func (o Op) Asm() obj.As          { return opcodeTable[o].asm }
40497 func (o Op) Scale() int16         { return int16(opcodeTable[o].scale) }
40498 func (o Op) String() string       { return opcodeTable[o].name }
40499 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect }
40500 func (o Op) IsCall() bool         { return opcodeTable[o].call }
40501 func (o Op) IsTailCall() bool     { return opcodeTable[o].tailCall }
40502 func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects }
40503 func (o Op) UnsafePoint() bool    { return opcodeTable[o].unsafePoint }
40504 func (o Op) ResultInArg0() bool   { return opcodeTable[o].resultInArg0 }
40505
40506 var registers386 = [...]Register{
40507         {0, x86.REG_AX, 0, "AX"},
40508         {1, x86.REG_CX, 1, "CX"},
40509         {2, x86.REG_DX, 2, "DX"},
40510         {3, x86.REG_BX, 3, "BX"},
40511         {4, x86.REGSP, -1, "SP"},
40512         {5, x86.REG_BP, 4, "BP"},
40513         {6, x86.REG_SI, 5, "SI"},
40514         {7, x86.REG_DI, 6, "DI"},
40515         {8, x86.REG_X0, -1, "X0"},
40516         {9, x86.REG_X1, -1, "X1"},
40517         {10, x86.REG_X2, -1, "X2"},
40518         {11, x86.REG_X3, -1, "X3"},
40519         {12, x86.REG_X4, -1, "X4"},
40520         {13, x86.REG_X5, -1, "X5"},
40521         {14, x86.REG_X6, -1, "X6"},
40522         {15, x86.REG_X7, -1, "X7"},
40523         {16, 0, -1, "SB"},
40524 }
40525 var paramIntReg386 = []int8(nil)
40526 var paramFloatReg386 = []int8(nil)
40527 var gpRegMask386 = regMask(239)
40528 var fpRegMask386 = regMask(65280)
40529 var specialRegMask386 = regMask(0)
40530 var framepointerReg386 = int8(5)
40531 var linkReg386 = int8(-1)
40532 var registersAMD64 = [...]Register{
40533         {0, x86.REG_AX, 0, "AX"},
40534         {1, x86.REG_CX, 1, "CX"},
40535         {2, x86.REG_DX, 2, "DX"},
40536         {3, x86.REG_BX, 3, "BX"},
40537         {4, x86.REGSP, -1, "SP"},
40538         {5, x86.REG_BP, 4, "BP"},
40539         {6, x86.REG_SI, 5, "SI"},
40540         {7, x86.REG_DI, 6, "DI"},
40541         {8, x86.REG_R8, 7, "R8"},
40542         {9, x86.REG_R9, 8, "R9"},
40543         {10, x86.REG_R10, 9, "R10"},
40544         {11, x86.REG_R11, 10, "R11"},
40545         {12, x86.REG_R12, 11, "R12"},
40546         {13, x86.REG_R13, 12, "R13"},
40547         {14, x86.REGG, -1, "g"},
40548         {15, x86.REG_R15, 13, "R15"},
40549         {16, x86.REG_X0, -1, "X0"},
40550         {17, x86.REG_X1, -1, "X1"},
40551         {18, x86.REG_X2, -1, "X2"},
40552         {19, x86.REG_X3, -1, "X3"},
40553         {20, x86.REG_X4, -1, "X4"},
40554         {21, x86.REG_X5, -1, "X5"},
40555         {22, x86.REG_X6, -1, "X6"},
40556         {23, x86.REG_X7, -1, "X7"},
40557         {24, x86.REG_X8, -1, "X8"},
40558         {25, x86.REG_X9, -1, "X9"},
40559         {26, x86.REG_X10, -1, "X10"},
40560         {27, x86.REG_X11, -1, "X11"},
40561         {28, x86.REG_X12, -1, "X12"},
40562         {29, x86.REG_X13, -1, "X13"},
40563         {30, x86.REG_X14, -1, "X14"},
40564         {31, x86.REG_X15, -1, "X15"},
40565         {32, 0, -1, "SB"},
40566 }
40567 var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
40568 var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
40569 var gpRegMaskAMD64 = regMask(49135)
40570 var fpRegMaskAMD64 = regMask(2147418112)
40571 var specialRegMaskAMD64 = regMask(2147483648)
40572 var framepointerRegAMD64 = int8(5)
40573 var linkRegAMD64 = int8(-1)
40574 var registersARM = [...]Register{
40575         {0, arm.REG_R0, 0, "R0"},
40576         {1, arm.REG_R1, 1, "R1"},
40577         {2, arm.REG_R2, 2, "R2"},
40578         {3, arm.REG_R3, 3, "R3"},
40579         {4, arm.REG_R4, 4, "R4"},
40580         {5, arm.REG_R5, 5, "R5"},
40581         {6, arm.REG_R6, 6, "R6"},
40582         {7, arm.REG_R7, 7, "R7"},
40583         {8, arm.REG_R8, 8, "R8"},
40584         {9, arm.REG_R9, 9, "R9"},
40585         {10, arm.REGG, -1, "g"},
40586         {11, arm.REG_R11, -1, "R11"},
40587         {12, arm.REG_R12, 10, "R12"},
40588         {13, arm.REGSP, -1, "SP"},
40589         {14, arm.REG_R14, 11, "R14"},
40590         {15, arm.REG_R15, -1, "R15"},
40591         {16, arm.REG_F0, -1, "F0"},
40592         {17, arm.REG_F1, -1, "F1"},
40593         {18, arm.REG_F2, -1, "F2"},
40594         {19, arm.REG_F3, -1, "F3"},
40595         {20, arm.REG_F4, -1, "F4"},
40596         {21, arm.REG_F5, -1, "F5"},
40597         {22, arm.REG_F6, -1, "F6"},
40598         {23, arm.REG_F7, -1, "F7"},
40599         {24, arm.REG_F8, -1, "F8"},
40600         {25, arm.REG_F9, -1, "F9"},
40601         {26, arm.REG_F10, -1, "F10"},
40602         {27, arm.REG_F11, -1, "F11"},
40603         {28, arm.REG_F12, -1, "F12"},
40604         {29, arm.REG_F13, -1, "F13"},
40605         {30, arm.REG_F14, -1, "F14"},
40606         {31, arm.REG_F15, -1, "F15"},
40607         {32, 0, -1, "SB"},
40608 }
40609 var paramIntRegARM = []int8(nil)
40610 var paramFloatRegARM = []int8(nil)
40611 var gpRegMaskARM = regMask(21503)
40612 var fpRegMaskARM = regMask(4294901760)
40613 var specialRegMaskARM = regMask(0)
40614 var framepointerRegARM = int8(-1)
40615 var linkRegARM = int8(14)
40616 var registersARM64 = [...]Register{
40617         {0, arm64.REG_R0, 0, "R0"},
40618         {1, arm64.REG_R1, 1, "R1"},
40619         {2, arm64.REG_R2, 2, "R2"},
40620         {3, arm64.REG_R3, 3, "R3"},
40621         {4, arm64.REG_R4, 4, "R4"},
40622         {5, arm64.REG_R5, 5, "R5"},
40623         {6, arm64.REG_R6, 6, "R6"},
40624         {7, arm64.REG_R7, 7, "R7"},
40625         {8, arm64.REG_R8, 8, "R8"},
40626         {9, arm64.REG_R9, 9, "R9"},
40627         {10, arm64.REG_R10, 10, "R10"},
40628         {11, arm64.REG_R11, 11, "R11"},
40629         {12, arm64.REG_R12, 12, "R12"},
40630         {13, arm64.REG_R13, 13, "R13"},
40631         {14, arm64.REG_R14, 14, "R14"},
40632         {15, arm64.REG_R15, 15, "R15"},
40633         {16, arm64.REG_R16, 16, "R16"},
40634         {17, arm64.REG_R17, 17, "R17"},
40635         {18, arm64.REG_R18, -1, "R18"},
40636         {19, arm64.REG_R19, 18, "R19"},
40637         {20, arm64.REG_R20, 19, "R20"},
40638         {21, arm64.REG_R21, 20, "R21"},
40639         {22, arm64.REG_R22, 21, "R22"},
40640         {23, arm64.REG_R23, 22, "R23"},
40641         {24, arm64.REG_R24, 23, "R24"},
40642         {25, arm64.REG_R25, 24, "R25"},
40643         {26, arm64.REG_R26, 25, "R26"},
40644         {27, arm64.REGG, -1, "g"},
40645         {28, arm64.REG_R29, -1, "R29"},
40646         {29, arm64.REG_R30, 26, "R30"},
40647         {30, arm64.REGSP, -1, "SP"},
40648         {31, arm64.REG_F0, -1, "F0"},
40649         {32, arm64.REG_F1, -1, "F1"},
40650         {33, arm64.REG_F2, -1, "F2"},
40651         {34, arm64.REG_F3, -1, "F3"},
40652         {35, arm64.REG_F4, -1, "F4"},
40653         {36, arm64.REG_F5, -1, "F5"},
40654         {37, arm64.REG_F6, -1, "F6"},
40655         {38, arm64.REG_F7, -1, "F7"},
40656         {39, arm64.REG_F8, -1, "F8"},
40657         {40, arm64.REG_F9, -1, "F9"},
40658         {41, arm64.REG_F10, -1, "F10"},
40659         {42, arm64.REG_F11, -1, "F11"},
40660         {43, arm64.REG_F12, -1, "F12"},
40661         {44, arm64.REG_F13, -1, "F13"},
40662         {45, arm64.REG_F14, -1, "F14"},
40663         {46, arm64.REG_F15, -1, "F15"},
40664         {47, arm64.REG_F16, -1, "F16"},
40665         {48, arm64.REG_F17, -1, "F17"},
40666         {49, arm64.REG_F18, -1, "F18"},
40667         {50, arm64.REG_F19, -1, "F19"},
40668         {51, arm64.REG_F20, -1, "F20"},
40669         {52, arm64.REG_F21, -1, "F21"},
40670         {53, arm64.REG_F22, -1, "F22"},
40671         {54, arm64.REG_F23, -1, "F23"},
40672         {55, arm64.REG_F24, -1, "F24"},
40673         {56, arm64.REG_F25, -1, "F25"},
40674         {57, arm64.REG_F26, -1, "F26"},
40675         {58, arm64.REG_F27, -1, "F27"},
40676         {59, arm64.REG_F28, -1, "F28"},
40677         {60, arm64.REG_F29, -1, "F29"},
40678         {61, arm64.REG_F30, -1, "F30"},
40679         {62, arm64.REG_F31, -1, "F31"},
40680         {63, 0, -1, "SB"},
40681 }
40682 var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
40683 var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46}
40684 var gpRegMaskARM64 = regMask(670826495)
40685 var fpRegMaskARM64 = regMask(9223372034707292160)
40686 var specialRegMaskARM64 = regMask(0)
40687 var framepointerRegARM64 = int8(-1)
40688 var linkRegARM64 = int8(29)
40689 var registersLOONG64 = [...]Register{
40690         {0, loong64.REG_R0, -1, "R0"},
40691         {1, loong64.REG_R1, -1, "R1"},
40692         {2, loong64.REGSP, -1, "SP"},
40693         {3, loong64.REG_R4, 0, "R4"},
40694         {4, loong64.REG_R5, 1, "R5"},
40695         {5, loong64.REG_R6, 2, "R6"},
40696         {6, loong64.REG_R7, 3, "R7"},
40697         {7, loong64.REG_R8, 4, "R8"},
40698         {8, loong64.REG_R9, 5, "R9"},
40699         {9, loong64.REG_R10, 6, "R10"},
40700         {10, loong64.REG_R11, 7, "R11"},
40701         {11, loong64.REG_R12, 8, "R12"},
40702         {12, loong64.REG_R13, 9, "R13"},
40703         {13, loong64.REG_R14, 10, "R14"},
40704         {14, loong64.REG_R15, 11, "R15"},
40705         {15, loong64.REG_R16, 12, "R16"},
40706         {16, loong64.REG_R17, 13, "R17"},
40707         {17, loong64.REG_R18, 14, "R18"},
40708         {18, loong64.REG_R19, 15, "R19"},
40709         {19, loong64.REG_R20, 16, "R20"},
40710         {20, loong64.REG_R21, -1, "R21"},
40711         {21, loong64.REGG, -1, "g"},
40712         {22, loong64.REG_R23, 17, "R23"},
40713         {23, loong64.REG_R24, 18, "R24"},
40714         {24, loong64.REG_R25, 19, "R25"},
40715         {25, loong64.REG_R26, 20, "R26"},
40716         {26, loong64.REG_R27, 21, "R27"},
40717         {27, loong64.REG_R28, 22, "R28"},
40718         {28, loong64.REG_R29, 23, "R29"},
40719         {29, loong64.REG_R31, 24, "R31"},
40720         {30, loong64.REG_F0, -1, "F0"},
40721         {31, loong64.REG_F1, -1, "F1"},
40722         {32, loong64.REG_F2, -1, "F2"},
40723         {33, loong64.REG_F3, -1, "F3"},
40724         {34, loong64.REG_F4, -1, "F4"},
40725         {35, loong64.REG_F5, -1, "F5"},
40726         {36, loong64.REG_F6, -1, "F6"},
40727         {37, loong64.REG_F7, -1, "F7"},
40728         {38, loong64.REG_F8, -1, "F8"},
40729         {39, loong64.REG_F9, -1, "F9"},
40730         {40, loong64.REG_F10, -1, "F10"},
40731         {41, loong64.REG_F11, -1, "F11"},
40732         {42, loong64.REG_F12, -1, "F12"},
40733         {43, loong64.REG_F13, -1, "F13"},
40734         {44, loong64.REG_F14, -1, "F14"},
40735         {45, loong64.REG_F15, -1, "F15"},
40736         {46, loong64.REG_F16, -1, "F16"},
40737         {47, loong64.REG_F17, -1, "F17"},
40738         {48, loong64.REG_F18, -1, "F18"},
40739         {49, loong64.REG_F19, -1, "F19"},
40740         {50, loong64.REG_F20, -1, "F20"},
40741         {51, loong64.REG_F21, -1, "F21"},
40742         {52, loong64.REG_F22, -1, "F22"},
40743         {53, loong64.REG_F23, -1, "F23"},
40744         {54, loong64.REG_F24, -1, "F24"},
40745         {55, loong64.REG_F25, -1, "F25"},
40746         {56, loong64.REG_F26, -1, "F26"},
40747         {57, loong64.REG_F27, -1, "F27"},
40748         {58, loong64.REG_F28, -1, "F28"},
40749         {59, loong64.REG_F29, -1, "F29"},
40750         {60, loong64.REG_F30, -1, "F30"},
40751         {61, loong64.REG_F31, -1, "F31"},
40752         {62, 0, -1, "SB"},
40753 }
40754 var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10}
40755 var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37}
40756 var gpRegMaskLOONG64 = regMask(1070596088)
40757 var fpRegMaskLOONG64 = regMask(4611686017353646080)
40758 var specialRegMaskLOONG64 = regMask(0)
40759 var framepointerRegLOONG64 = int8(-1)
40760 var linkRegLOONG64 = int8(1)
40761 var registersMIPS = [...]Register{
40762         {0, mips.REG_R0, -1, "R0"},
40763         {1, mips.REG_R1, 0, "R1"},
40764         {2, mips.REG_R2, 1, "R2"},
40765         {3, mips.REG_R3, 2, "R3"},
40766         {4, mips.REG_R4, 3, "R4"},
40767         {5, mips.REG_R5, 4, "R5"},
40768         {6, mips.REG_R6, 5, "R6"},
40769         {7, mips.REG_R7, 6, "R7"},
40770         {8, mips.REG_R8, 7, "R8"},
40771         {9, mips.REG_R9, 8, "R9"},
40772         {10, mips.REG_R10, 9, "R10"},
40773         {11, mips.REG_R11, 10, "R11"},
40774         {12, mips.REG_R12, 11, "R12"},
40775         {13, mips.REG_R13, 12, "R13"},
40776         {14, mips.REG_R14, 13, "R14"},
40777         {15, mips.REG_R15, 14, "R15"},
40778         {16, mips.REG_R16, 15, "R16"},
40779         {17, mips.REG_R17, 16, "R17"},
40780         {18, mips.REG_R18, 17, "R18"},
40781         {19, mips.REG_R19, 18, "R19"},
40782         {20, mips.REG_R20, 19, "R20"},
40783         {21, mips.REG_R21, 20, "R21"},
40784         {22, mips.REG_R22, 21, "R22"},
40785         {23, mips.REG_R24, 22, "R24"},
40786         {24, mips.REG_R25, 23, "R25"},
40787         {25, mips.REG_R28, 24, "R28"},
40788         {26, mips.REGSP, -1, "SP"},
40789         {27, mips.REGG, -1, "g"},
40790         {28, mips.REG_R31, 25, "R31"},
40791         {29, mips.REG_F0, -1, "F0"},
40792         {30, mips.REG_F2, -1, "F2"},
40793         {31, mips.REG_F4, -1, "F4"},
40794         {32, mips.REG_F6, -1, "F6"},
40795         {33, mips.REG_F8, -1, "F8"},
40796         {34, mips.REG_F10, -1, "F10"},
40797         {35, mips.REG_F12, -1, "F12"},
40798         {36, mips.REG_F14, -1, "F14"},
40799         {37, mips.REG_F16, -1, "F16"},
40800         {38, mips.REG_F18, -1, "F18"},
40801         {39, mips.REG_F20, -1, "F20"},
40802         {40, mips.REG_F22, -1, "F22"},
40803         {41, mips.REG_F24, -1, "F24"},
40804         {42, mips.REG_F26, -1, "F26"},
40805         {43, mips.REG_F28, -1, "F28"},
40806         {44, mips.REG_F30, -1, "F30"},
40807         {45, mips.REG_HI, -1, "HI"},
40808         {46, mips.REG_LO, -1, "LO"},
40809         {47, 0, -1, "SB"},
40810 }
40811 var paramIntRegMIPS = []int8(nil)
40812 var paramFloatRegMIPS = []int8(nil)
40813 var gpRegMaskMIPS = regMask(335544318)
40814 var fpRegMaskMIPS = regMask(35183835217920)
40815 var specialRegMaskMIPS = regMask(105553116266496)
40816 var framepointerRegMIPS = int8(-1)
40817 var linkRegMIPS = int8(28)
40818 var registersMIPS64 = [...]Register{
40819         {0, mips.REG_R0, -1, "R0"},
40820         {1, mips.REG_R1, 0, "R1"},
40821         {2, mips.REG_R2, 1, "R2"},
40822         {3, mips.REG_R3, 2, "R3"},
40823         {4, mips.REG_R4, 3, "R4"},
40824         {5, mips.REG_R5, 4, "R5"},
40825         {6, mips.REG_R6, 5, "R6"},
40826         {7, mips.REG_R7, 6, "R7"},
40827         {8, mips.REG_R8, 7, "R8"},
40828         {9, mips.REG_R9, 8, "R9"},
40829         {10, mips.REG_R10, 9, "R10"},
40830         {11, mips.REG_R11, 10, "R11"},
40831         {12, mips.REG_R12, 11, "R12"},
40832         {13, mips.REG_R13, 12, "R13"},
40833         {14, mips.REG_R14, 13, "R14"},
40834         {15, mips.REG_R15, 14, "R15"},
40835         {16, mips.REG_R16, 15, "R16"},
40836         {17, mips.REG_R17, 16, "R17"},
40837         {18, mips.REG_R18, 17, "R18"},
40838         {19, mips.REG_R19, 18, "R19"},
40839         {20, mips.REG_R20, 19, "R20"},
40840         {21, mips.REG_R21, 20, "R21"},
40841         {22, mips.REG_R22, 21, "R22"},
40842         {23, mips.REG_R24, 22, "R24"},
40843         {24, mips.REG_R25, 23, "R25"},
40844         {25, mips.REGSP, -1, "SP"},
40845         {26, mips.REGG, -1, "g"},
40846         {27, mips.REG_R31, 24, "R31"},
40847         {28, mips.REG_F0, -1, "F0"},
40848         {29, mips.REG_F1, -1, "F1"},
40849         {30, mips.REG_F2, -1, "F2"},
40850         {31, mips.REG_F3, -1, "F3"},
40851         {32, mips.REG_F4, -1, "F4"},
40852         {33, mips.REG_F5, -1, "F5"},
40853         {34, mips.REG_F6, -1, "F6"},
40854         {35, mips.REG_F7, -1, "F7"},
40855         {36, mips.REG_F8, -1, "F8"},
40856         {37, mips.REG_F9, -1, "F9"},
40857         {38, mips.REG_F10, -1, "F10"},
40858         {39, mips.REG_F11, -1, "F11"},
40859         {40, mips.REG_F12, -1, "F12"},
40860         {41, mips.REG_F13, -1, "F13"},
40861         {42, mips.REG_F14, -1, "F14"},
40862         {43, mips.REG_F15, -1, "F15"},
40863         {44, mips.REG_F16, -1, "F16"},
40864         {45, mips.REG_F17, -1, "F17"},
40865         {46, mips.REG_F18, -1, "F18"},
40866         {47, mips.REG_F19, -1, "F19"},
40867         {48, mips.REG_F20, -1, "F20"},
40868         {49, mips.REG_F21, -1, "F21"},
40869         {50, mips.REG_F22, -1, "F22"},
40870         {51, mips.REG_F23, -1, "F23"},
40871         {52, mips.REG_F24, -1, "F24"},
40872         {53, mips.REG_F25, -1, "F25"},
40873         {54, mips.REG_F26, -1, "F26"},
40874         {55, mips.REG_F27, -1, "F27"},
40875         {56, mips.REG_F28, -1, "F28"},
40876         {57, mips.REG_F29, -1, "F29"},
40877         {58, mips.REG_F30, -1, "F30"},
40878         {59, mips.REG_F31, -1, "F31"},
40879         {60, mips.REG_HI, -1, "HI"},
40880         {61, mips.REG_LO, -1, "LO"},
40881         {62, 0, -1, "SB"},
40882 }
40883 var paramIntRegMIPS64 = []int8(nil)
40884 var paramFloatRegMIPS64 = []int8(nil)
40885 var gpRegMaskMIPS64 = regMask(167772158)
40886 var fpRegMaskMIPS64 = regMask(1152921504338411520)
40887 var specialRegMaskMIPS64 = regMask(3458764513820540928)
40888 var framepointerRegMIPS64 = int8(-1)
40889 var linkRegMIPS64 = int8(27)
40890 var registersPPC64 = [...]Register{
40891         {0, ppc64.REG_R0, -1, "R0"},
40892         {1, ppc64.REGSP, -1, "SP"},
40893         {2, 0, -1, "SB"},
40894         {3, ppc64.REG_R3, 0, "R3"},
40895         {4, ppc64.REG_R4, 1, "R4"},
40896         {5, ppc64.REG_R5, 2, "R5"},
40897         {6, ppc64.REG_R6, 3, "R6"},
40898         {7, ppc64.REG_R7, 4, "R7"},
40899         {8, ppc64.REG_R8, 5, "R8"},
40900         {9, ppc64.REG_R9, 6, "R9"},
40901         {10, ppc64.REG_R10, 7, "R10"},
40902         {11, ppc64.REG_R11, 8, "R11"},
40903         {12, ppc64.REG_R12, 9, "R12"},
40904         {13, ppc64.REG_R13, -1, "R13"},
40905         {14, ppc64.REG_R14, 10, "R14"},
40906         {15, ppc64.REG_R15, 11, "R15"},
40907         {16, ppc64.REG_R16, 12, "R16"},
40908         {17, ppc64.REG_R17, 13, "R17"},
40909         {18, ppc64.REG_R18, 14, "R18"},
40910         {19, ppc64.REG_R19, 15, "R19"},
40911         {20, ppc64.REG_R20, 16, "R20"},
40912         {21, ppc64.REG_R21, 17, "R21"},
40913         {22, ppc64.REG_R22, 18, "R22"},
40914         {23, ppc64.REG_R23, 19, "R23"},
40915         {24, ppc64.REG_R24, 20, "R24"},
40916         {25, ppc64.REG_R25, 21, "R25"},
40917         {26, ppc64.REG_R26, 22, "R26"},
40918         {27, ppc64.REG_R27, 23, "R27"},
40919         {28, ppc64.REG_R28, 24, "R28"},
40920         {29, ppc64.REG_R29, 25, "R29"},
40921         {30, ppc64.REGG, -1, "g"},
40922         {31, ppc64.REG_R31, -1, "R31"},
40923         {32, ppc64.REG_F0, -1, "F0"},
40924         {33, ppc64.REG_F1, -1, "F1"},
40925         {34, ppc64.REG_F2, -1, "F2"},
40926         {35, ppc64.REG_F3, -1, "F3"},
40927         {36, ppc64.REG_F4, -1, "F4"},
40928         {37, ppc64.REG_F5, -1, "F5"},
40929         {38, ppc64.REG_F6, -1, "F6"},
40930         {39, ppc64.REG_F7, -1, "F7"},
40931         {40, ppc64.REG_F8, -1, "F8"},
40932         {41, ppc64.REG_F9, -1, "F9"},
40933         {42, ppc64.REG_F10, -1, "F10"},
40934         {43, ppc64.REG_F11, -1, "F11"},
40935         {44, ppc64.REG_F12, -1, "F12"},
40936         {45, ppc64.REG_F13, -1, "F13"},
40937         {46, ppc64.REG_F14, -1, "F14"},
40938         {47, ppc64.REG_F15, -1, "F15"},
40939         {48, ppc64.REG_F16, -1, "F16"},
40940         {49, ppc64.REG_F17, -1, "F17"},
40941         {50, ppc64.REG_F18, -1, "F18"},
40942         {51, ppc64.REG_F19, -1, "F19"},
40943         {52, ppc64.REG_F20, -1, "F20"},
40944         {53, ppc64.REG_F21, -1, "F21"},
40945         {54, ppc64.REG_F22, -1, "F22"},
40946         {55, ppc64.REG_F23, -1, "F23"},
40947         {56, ppc64.REG_F24, -1, "F24"},
40948         {57, ppc64.REG_F25, -1, "F25"},
40949         {58, ppc64.REG_F26, -1, "F26"},
40950         {59, ppc64.REG_F27, -1, "F27"},
40951         {60, ppc64.REG_F28, -1, "F28"},
40952         {61, ppc64.REG_F29, -1, "F29"},
40953         {62, ppc64.REG_F30, -1, "F30"},
40954         {63, ppc64.REG_XER, -1, "XER"},
40955 }
40956 var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17}
40957 var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44}
40958 var gpRegMaskPPC64 = regMask(1073733624)
40959 var fpRegMaskPPC64 = regMask(9223372032559808512)
40960 var specialRegMaskPPC64 = regMask(9223372036854775808)
40961 var framepointerRegPPC64 = int8(-1)
40962 var linkRegPPC64 = int8(-1)
40963 var registersRISCV64 = [...]Register{
40964         {0, riscv.REG_X0, -1, "X0"},
40965         {1, riscv.REGSP, -1, "SP"},
40966         {2, riscv.REG_X3, -1, "X3"},
40967         {3, riscv.REG_X4, -1, "X4"},
40968         {4, riscv.REG_X5, 0, "X5"},
40969         {5, riscv.REG_X6, 1, "X6"},
40970         {6, riscv.REG_X7, 2, "X7"},
40971         {7, riscv.REG_X8, 3, "X8"},
40972         {8, riscv.REG_X9, 4, "X9"},
40973         {9, riscv.REG_X10, 5, "X10"},
40974         {10, riscv.REG_X11, 6, "X11"},
40975         {11, riscv.REG_X12, 7, "X12"},
40976         {12, riscv.REG_X13, 8, "X13"},
40977         {13, riscv.REG_X14, 9, "X14"},
40978         {14, riscv.REG_X15, 10, "X15"},
40979         {15, riscv.REG_X16, 11, "X16"},
40980         {16, riscv.REG_X17, 12, "X17"},
40981         {17, riscv.REG_X18, 13, "X18"},
40982         {18, riscv.REG_X19, 14, "X19"},
40983         {19, riscv.REG_X20, 15, "X20"},
40984         {20, riscv.REG_X21, 16, "X21"},
40985         {21, riscv.REG_X22, 17, "X22"},
40986         {22, riscv.REG_X23, 18, "X23"},
40987         {23, riscv.REG_X24, 19, "X24"},
40988         {24, riscv.REG_X25, 20, "X25"},
40989         {25, riscv.REG_X26, 21, "X26"},
40990         {26, riscv.REGG, -1, "g"},
40991         {27, riscv.REG_X28, 22, "X28"},
40992         {28, riscv.REG_X29, 23, "X29"},
40993         {29, riscv.REG_X30, 24, "X30"},
40994         {30, riscv.REG_X31, -1, "X31"},
40995         {31, riscv.REG_F0, -1, "F0"},
40996         {32, riscv.REG_F1, -1, "F1"},
40997         {33, riscv.REG_F2, -1, "F2"},
40998         {34, riscv.REG_F3, -1, "F3"},
40999         {35, riscv.REG_F4, -1, "F4"},
41000         {36, riscv.REG_F5, -1, "F5"},
41001         {37, riscv.REG_F6, -1, "F6"},
41002         {38, riscv.REG_F7, -1, "F7"},
41003         {39, riscv.REG_F8, -1, "F8"},
41004         {40, riscv.REG_F9, -1, "F9"},
41005         {41, riscv.REG_F10, -1, "F10"},
41006         {42, riscv.REG_F11, -1, "F11"},
41007         {43, riscv.REG_F12, -1, "F12"},
41008         {44, riscv.REG_F13, -1, "F13"},
41009         {45, riscv.REG_F14, -1, "F14"},
41010         {46, riscv.REG_F15, -1, "F15"},
41011         {47, riscv.REG_F16, -1, "F16"},
41012         {48, riscv.REG_F17, -1, "F17"},
41013         {49, riscv.REG_F18, -1, "F18"},
41014         {50, riscv.REG_F19, -1, "F19"},
41015         {51, riscv.REG_F20, -1, "F20"},
41016         {52, riscv.REG_F21, -1, "F21"},
41017         {53, riscv.REG_F22, -1, "F22"},
41018         {54, riscv.REG_F23, -1, "F23"},
41019         {55, riscv.REG_F24, -1, "F24"},
41020         {56, riscv.REG_F25, -1, "F25"},
41021         {57, riscv.REG_F26, -1, "F26"},
41022         {58, riscv.REG_F27, -1, "F27"},
41023         {59, riscv.REG_F28, -1, "F28"},
41024         {60, riscv.REG_F29, -1, "F29"},
41025         {61, riscv.REG_F30, -1, "F30"},
41026         {62, riscv.REG_F31, -1, "F31"},
41027         {63, 0, -1, "SB"},
41028 }
41029 var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22}
41030 var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54}
41031 var gpRegMaskRISCV64 = regMask(1006632944)
41032 var fpRegMaskRISCV64 = regMask(9223372034707292160)
41033 var specialRegMaskRISCV64 = regMask(0)
41034 var framepointerRegRISCV64 = int8(-1)
41035 var linkRegRISCV64 = int8(0)
41036 var registersS390X = [...]Register{
41037         {0, s390x.REG_R0, 0, "R0"},
41038         {1, s390x.REG_R1, 1, "R1"},
41039         {2, s390x.REG_R2, 2, "R2"},
41040         {3, s390x.REG_R3, 3, "R3"},
41041         {4, s390x.REG_R4, 4, "R4"},
41042         {5, s390x.REG_R5, 5, "R5"},
41043         {6, s390x.REG_R6, 6, "R6"},
41044         {7, s390x.REG_R7, 7, "R7"},
41045         {8, s390x.REG_R8, 8, "R8"},
41046         {9, s390x.REG_R9, 9, "R9"},
41047         {10, s390x.REG_R10, -1, "R10"},
41048         {11, s390x.REG_R11, 10, "R11"},
41049         {12, s390x.REG_R12, 11, "R12"},
41050         {13, s390x.REGG, -1, "g"},
41051         {14, s390x.REG_R14, 12, "R14"},
41052         {15, s390x.REGSP, -1, "SP"},
41053         {16, s390x.REG_F0, -1, "F0"},
41054         {17, s390x.REG_F1, -1, "F1"},
41055         {18, s390x.REG_F2, -1, "F2"},
41056         {19, s390x.REG_F3, -1, "F3"},
41057         {20, s390x.REG_F4, -1, "F4"},
41058         {21, s390x.REG_F5, -1, "F5"},
41059         {22, s390x.REG_F6, -1, "F6"},
41060         {23, s390x.REG_F7, -1, "F7"},
41061         {24, s390x.REG_F8, -1, "F8"},
41062         {25, s390x.REG_F9, -1, "F9"},
41063         {26, s390x.REG_F10, -1, "F10"},
41064         {27, s390x.REG_F11, -1, "F11"},
41065         {28, s390x.REG_F12, -1, "F12"},
41066         {29, s390x.REG_F13, -1, "F13"},
41067         {30, s390x.REG_F14, -1, "F14"},
41068         {31, s390x.REG_F15, -1, "F15"},
41069         {32, 0, -1, "SB"},
41070 }
41071 var paramIntRegS390X = []int8(nil)
41072 var paramFloatRegS390X = []int8(nil)
41073 var gpRegMaskS390X = regMask(23551)
41074 var fpRegMaskS390X = regMask(4294901760)
41075 var specialRegMaskS390X = regMask(0)
41076 var framepointerRegS390X = int8(-1)
41077 var linkRegS390X = int8(14)
41078 var registersWasm = [...]Register{
41079         {0, wasm.REG_R0, 0, "R0"},
41080         {1, wasm.REG_R1, 1, "R1"},
41081         {2, wasm.REG_R2, 2, "R2"},
41082         {3, wasm.REG_R3, 3, "R3"},
41083         {4, wasm.REG_R4, 4, "R4"},
41084         {5, wasm.REG_R5, 5, "R5"},
41085         {6, wasm.REG_R6, 6, "R6"},
41086         {7, wasm.REG_R7, 7, "R7"},
41087         {8, wasm.REG_R8, 8, "R8"},
41088         {9, wasm.REG_R9, 9, "R9"},
41089         {10, wasm.REG_R10, 10, "R10"},
41090         {11, wasm.REG_R11, 11, "R11"},
41091         {12, wasm.REG_R12, 12, "R12"},
41092         {13, wasm.REG_R13, 13, "R13"},
41093         {14, wasm.REG_R14, 14, "R14"},
41094         {15, wasm.REG_R15, 15, "R15"},
41095         {16, wasm.REG_F0, -1, "F0"},
41096         {17, wasm.REG_F1, -1, "F1"},
41097         {18, wasm.REG_F2, -1, "F2"},
41098         {19, wasm.REG_F3, -1, "F3"},
41099         {20, wasm.REG_F4, -1, "F4"},
41100         {21, wasm.REG_F5, -1, "F5"},
41101         {22, wasm.REG_F6, -1, "F6"},
41102         {23, wasm.REG_F7, -1, "F7"},
41103         {24, wasm.REG_F8, -1, "F8"},
41104         {25, wasm.REG_F9, -1, "F9"},
41105         {26, wasm.REG_F10, -1, "F10"},
41106         {27, wasm.REG_F11, -1, "F11"},
41107         {28, wasm.REG_F12, -1, "F12"},
41108         {29, wasm.REG_F13, -1, "F13"},
41109         {30, wasm.REG_F14, -1, "F14"},
41110         {31, wasm.REG_F15, -1, "F15"},
41111         {32, wasm.REG_F16, -1, "F16"},
41112         {33, wasm.REG_F17, -1, "F17"},
41113         {34, wasm.REG_F18, -1, "F18"},
41114         {35, wasm.REG_F19, -1, "F19"},
41115         {36, wasm.REG_F20, -1, "F20"},
41116         {37, wasm.REG_F21, -1, "F21"},
41117         {38, wasm.REG_F22, -1, "F22"},
41118         {39, wasm.REG_F23, -1, "F23"},
41119         {40, wasm.REG_F24, -1, "F24"},
41120         {41, wasm.REG_F25, -1, "F25"},
41121         {42, wasm.REG_F26, -1, "F26"},
41122         {43, wasm.REG_F27, -1, "F27"},
41123         {44, wasm.REG_F28, -1, "F28"},
41124         {45, wasm.REG_F29, -1, "F29"},
41125         {46, wasm.REG_F30, -1, "F30"},
41126         {47, wasm.REG_F31, -1, "F31"},
41127         {48, wasm.REGSP, -1, "SP"},
41128         {49, wasm.REGG, -1, "g"},
41129         {50, 0, -1, "SB"},
41130 }
41131 var paramIntRegWasm = []int8(nil)
41132 var paramFloatRegWasm = []int8(nil)
41133 var gpRegMaskWasm = regMask(65535)
41134 var fpRegMaskWasm = regMask(281474976645120)
41135 var fp32RegMaskWasm = regMask(4294901760)
41136 var fp64RegMaskWasm = regMask(281470681743360)
41137 var specialRegMaskWasm = regMask(0)
41138 var framepointerRegWasm = int8(-1)
41139 var linkRegWasm = int8(-1)