1 // cmd/9c/9.out.h from Vita Nuova.
3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
5 // Portions Copyright © 1997-1999 Vita Nuova Limited
6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
7 // Portions Copyright © 2004,2006 Bruce Ellis
8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
10 // Portions Copyright © 2009 The Go Authors. All rights reserved.
12 // Permission is hereby granted, free of charge, to any person obtaining a copy
13 // of this software and associated documentation files (the "Software"), to deal
14 // in the Software without restriction, including without limitation the rights
15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 // copies of the Software, and to permit persons to whom the Software is
17 // furnished to do so, subject to the following conditions:
19 // The above copyright notice and this permission notice shall be included in
20 // all copies or substantial portions of the Software.
22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 import "cmd/internal/obj"
34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
42 NREG = 32 /* number of general registers */
43 NFREG = 32 /* number of floating point registers */
47 /* RBasePPC64 = 4096 */
48 /* R0=4096 ... R31=4127 */
49 REG_R0 = obj.RBasePPC64 + iota
82 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32
116 /* Align FPR and VSR vectors such that when masked with 0x3F they produce
117 an equivalent VSX register. */
118 /* F0=4160 ... F31=4191 */
152 /* V0=4192 ... V31=4223 */
186 /* VS0=4224 ... VS63=4287 */
261 // MMA accumulator registers, these shadow VSR 0-31
262 // e.g MMAx shadows VSRx*4-VSRx*4+3 or
263 // MMA0 shadows VSR0-VSR3
277 REG_SPECIAL = REG_CR0
279 REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0
281 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
283 REG_XER = REG_SPR0 + 1
284 REG_LR = REG_SPR0 + 8
285 REG_CTR = REG_SPR0 + 9
287 REGZERO = REG_R0 /* set to zero */
291 REGARG = -1 /* -1 disables passing the first argument in register */
292 REGRT1 = REG_R20 /* reserved for runtime, duffzero and duffcopy */
293 REGRT2 = REG_R21 /* reserved for runtime, duffcopy */
294 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */
295 REGCTXT = REG_R11 /* context for closures */
296 REGTLS = REG_R13 /* C ABI TLS base pointer */
298 REGEXT = REG_R30 /* external registers allocated from here down */
299 REGG = REG_R30 /* G */
300 REGTMP = REG_R31 /* used by the linker */
302 FREGMIN = REG_F17 /* first register variable */
303 FREGMAX = REG_F26 /* last register variable for 9g only */
304 FREGEXT = REG_F26 /* first external register */
307 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
308 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
309 var PPC64DWARFRegisters = map[int16]int16{}
312 // f assigns dwarfregister[from:to] = (base):(to-from+base)
313 f := func(from, to, base int16) {
314 for r := int16(from); r <= to; r++ {
315 PPC64DWARFRegisters[r] = r - from + base
318 f(REG_R0, REG_R31, 0)
319 f(REG_F0, REG_F31, 32)
320 f(REG_V0, REG_V31, 77)
321 f(REG_CR0, REG_CR7, 68)
323 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31
324 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
325 PPC64DWARFRegisters[REG_LR] = 65
326 PPC64DWARFRegisters[REG_CTR] = 66
327 PPC64DWARFRegisters[REG_XER] = 76
333 * compiler allocates R3 up as temps
334 * compiler allocates register variables R7-R27
335 * compiler allocates external registers R30 down
337 * compiler allocates register variables F17-F26
338 * compiler allocates external registers F26 down
356 PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary
359 // Values for use in branch instruction BC
361 // BO is type of branch + likely bits described below
362 // BI is CR value + branch type
363 // ex: BEQ CR2,label is BC 12,10,label
365 // 10 = BI_CR2 + BI_EQ
382 // Common values for the BO field.
385 BO_ALWAYS = 20 // branch unconditionally
386 BO_BCTR = 16 // decrement ctr, branch on ctr != 0
387 BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0
388 BO_BCR = 12 // branch on cr value
389 BO_BCRBCTR = 8 // decrement ctr, branch on ctr != 0 and cr value
390 BO_NOTBCR = 4 // branch on not cr value
393 // Bit settings from the CR
396 C_COND_LT = iota // 0 result is negative
397 C_COND_GT // 1 result is positive
398 C_COND_EQ // 2 result is zero
399 C_COND_SO // 3 summary overflow or FP compare w/ NaN
404 C_REGP /* An even numbered gpr which can be used a gpr pair argument */
405 C_REG /* Any gpr register */
406 C_FREGP /* An even numbered fpr which can be used a fpr pair argument */
407 C_FREG /* Any fpr register */
408 C_VREG /* Any vector register */
409 C_VSREGP /* An even numbered vsx register which can be used as a vsx register pair argument */
410 C_VSREG /* Any vector-scalar register */
411 C_CREG /* The condition registor (CR) */
412 C_CRBIT /* A single bit of the CR register (0-31) */
413 C_SPR /* special processor register */
414 C_AREG /* MMA accumulator register */
415 C_ZCON /* The constant zero */
416 C_U1CON /* 1 bit unsigned constant */
417 C_U2CON /* 2 bit unsigned constant */
418 C_U3CON /* 3 bit unsigned constant */
419 C_U4CON /* 4 bit unsigned constant */
420 C_U5CON /* 5 bit unsigned constant */
421 C_U8CON /* 8 bit unsigned constant */
422 C_U15CON /* 15 bit unsigned constant */
423 C_S16CON /* 16 bit signed constant */
424 C_U16CON /* 16 bit unsigned constant */
425 C_32S16CON /* Any 32 bit constant of the form 0x....0000, signed or unsigned */
426 C_32CON /* Any constant which fits into 32 bits. Can be signed or unsigned */
427 C_S34CON /* 34 bit signed constant */
428 C_64CON /* Any constant which fits into 64 bits. Can be signed or unsigned */
429 C_SACON /* $n(REG) where n <= int16 */
430 C_LACON /* $n(REG) where n <= int32 */
431 C_DACON /* $n(REG) where n <= int64 */
432 C_SBRA /* A short offset argument to a branching instruction */
433 C_LBRA /* A long offset argument to a branching instruction */
434 C_LBRAPIC /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */
435 C_ZOREG /* An $0+reg memory op */
436 C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */
437 C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */
438 C_XOREG /* An reg+reg memory arg */
439 C_FPSCR /* The fpscr register */
440 C_XER /* The xer, holds the carry bit */
441 C_LR /* The link register */
442 C_CTR /* The count register */
443 C_ANY /* Any argument */
444 C_GOK /* A non-matched argument */
445 C_ADDR /* A symbolic memory location */
446 C_TLS_LE /* A thread local, local-exec, type memory arg */
447 C_TLS_IE /* A thread local, initial-exec, type memory arg */
448 C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */
450 C_NCLASS /* must be the last */
452 /* Aliased names which should be cleaned up, or integrated. */
459 /* Aliased names which may be generated by ppc64map for the optab. */
460 C_S3216CON = C_32S16CON // TODO: these should be treated differently (e.g xoris vs addis)
461 C_U3216CON = C_32S16CON
467 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
497 ABGE // not LT = G/E/U
499 ABLE // not GT = L/E/U
501 ABNE // not EQ = L/G/U
502 ABVC // Branch if float not unordered (also branch on not summary overflow)
503 ABVS // Branch if float unordered (also branch on summary overflow)
504 ABDNZ // Decrement CTR, and branch if CTR != 0
505 ABDZ // Decrement CTR, and branch if CTR == 0
702 /* optional on 32-bit */
726 ACMPW /* CMP with L=0 */
745 /* AFCFIW; AFCFIWCC */
806 /* 64-bit pseudo operation */
811 /* more 64-bit operations */
1089 ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map.
1094 ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table.