cmd/internal/obj/ppc64: add VC[LT]ZLSBB instructions

These are ISA 3.0 power9 instructions which are helpful when reducing
a vector compare result into a GPR.

They are used in a future patch to improve the bytes.IndexByte asm
routine.

Change-Id: I424e2628e577167b9b7c0fcbd82099daf568ea35
Reviewed-on: https://go-review.googlesource.com/c/go/+/478115
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Heschi Kreinick <heschi@google.com>
Run-TryBot: Paul Murphy <murp@ibm.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>

diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s
index 7a83fb952bb83e69d6727d3953d25fa52dd78601..a0f1276aa1f43853c431ef55362e5672d2c7ff0e 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/ppc64.s
+++ b/src/cmd/asm/internal/asm/testdata/ppc64.s
@@ -1088,5 +1088,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
        PNOP                            // 0700000000000000
 
        SETB CR1,R3                     // 7c640100
+       VCLZLSBB V1, R2                 // 10400e02
+       VCTZLSBB V1, R2                 // 10410e02
 
        RET

diff --git a/src/cmd/internal/obj/ppc64/a.out.go b/src/cmd/internal/obj/ppc64/a.out.go
index 09b0a87a07531820901c0ba2fa722f91cf154251..efc10ea0f2f1f73e8c51b764b4ed607cf9774958 100644 (file)
--- a/src/cmd/internal/obj/ppc64/a.out.go
+++ b/src/cmd/internal/obj/ppc64/a.out.go
@@ -997,6 +997,8 @@ const (
        AVSHASIGMAD
        AVMRGEW
        AVMRGOW
+       AVCLZLSBB
+       AVCTZLSBB
 
        /* VSX */
        ALXV

diff --git a/src/cmd/internal/obj/ppc64/anames.go b/src/cmd/internal/obj/ppc64/anames.go
index 81e1fd1ea42461e67ff7b94aef26a2f2c3c3224a..f4680cc368a37f3dd61687e6af93fd6fde14417a 100644 (file)
--- a/src/cmd/internal/obj/ppc64/anames.go
+++ b/src/cmd/internal/obj/ppc64/anames.go
@@ -523,6 +523,8 @@ var Anames = []string{
        "VSHASIGMAD",
        "VMRGEW",
        "VMRGOW",
+       "VCLZLSBB",
+       "VCTZLSBB",
        "LXV",
        "LXVL",
        "LXVLL",

diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go
index 799def6ef781a84953a402a6175d79b8cde416d5..dbc1a5b81950fb618d3a40ca53665e8177fb870c 100644 (file)
--- a/src/cmd/internal/obj/ppc64/asm9.go
+++ b/src/cmd/internal/obj/ppc64/asm9.go
@@ -327,6 +327,7 @@ var optab = []Optab{
 
        /* Misc ISA 3.0 instructions */
        {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
+       {as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
 
        /* Vector instructions */
 
@@ -2089,6 +2090,9 @@ func buildop(ctxt *obj.Link) {
                case AMOVW: /* load/store/move word with sign extension; move 32-bit literals  */
                        opset(AMOVWZ, r0) /* Same as above, but zero extended */
 
+               case AVCLZLSBB:
+                       opset(AVCTZLSBB, r0)
+
                case AADD,
                        AADDIS,
                        AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */
@@ -4784,6 +4788,11 @@ func (c *ctxt9) oprrr(a obj.As) uint32 {
        case AVCLZD:
                return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */
 
+       case AVCLZLSBB:
+               return OPVX(4, 1538, 0, 0) /* vclzlsbb - v3.0 */
+       case AVCTZLSBB:
+               return OPVX(4, 1538, 0, 0) | 1<<16 /* vctzlsbb - v3.0 */
+
        case AVPOPCNTB:
                return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */
        case AVPOPCNTH: