1 // Based on cmd/internal/obj/ppc64/asm9.go.
3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
5 // Portions Copyright © 1997-1999 Vita Nuova Limited
6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
7 // Portions Copyright © 2004,2006 Bruce Ellis
8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
10 // Portions Copyright © 2009 The Go Authors. All rights reserved.
12 // Permission is hereby granted, free of charge, to any person obtaining a copy
13 // of this software and associated documentation files (the "Software"), to deal
14 // in the Software without restriction, including without limitation the rights
15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 // copies of the Software, and to permit persons to whom the Software is
17 // furnished to do so, subject to the following conditions:
19 // The above copyright notice and this permission notice shall be included in
20 // all copies or substantial portions of the Software.
22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
39 // instruction layout.
51 param int16 // REGSP for auto variables
55 // instruction, From, Reg, From3, To, type, param
56 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0},
57 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0},
60 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
61 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
62 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
63 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
64 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
65 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0},
66 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
69 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
70 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
71 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
72 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
73 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
74 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
75 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
76 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
79 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_ADDR, 73, 0},
80 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0},
81 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0},
82 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0},
83 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0},
84 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0},
85 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
86 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
87 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
88 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
89 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
90 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
91 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LOREG, 72, 0},
92 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0},
93 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0},
94 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0},
95 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0},
96 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0},
99 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
100 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
101 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
102 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
103 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
104 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
105 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
106 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
107 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
108 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
109 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
110 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
111 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
112 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
113 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
114 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
115 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
116 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
117 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
120 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
121 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
122 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
123 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
124 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
125 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
126 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
127 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
128 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
129 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
130 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
131 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
132 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
133 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
134 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
135 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
136 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
137 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
138 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
140 // integer arithmetic
141 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0},
142 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
143 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0},
144 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0},
145 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0},
146 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0},
147 Optab{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 0},
148 Optab{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 0},
149 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0},
150 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
151 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0},
152 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0},
153 Optab{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 0},
154 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0},
155 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0},
158 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0},
159 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0},
160 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0},
161 Optab{AAND, C_LCON, C_REG, C_NONE, C_REG, 23, 0},
162 Optab{AOR, C_REG, C_REG, C_NONE, C_REG, 6, 0},
163 Optab{AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 0},
164 Optab{AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 0},
165 Optab{AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 0},
166 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0},
167 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0},
168 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0},
169 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0},
172 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0},
175 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 0},
176 Optab{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 0},
177 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0},
178 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0},
179 Optab{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 0},
180 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0},
181 Optab{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 0},
182 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP},
183 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0},
184 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0},
185 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
186 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0},
187 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0},
188 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0},
189 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0},
190 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0},
192 // load symbol address (plus offset)
193 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0},
194 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0},
195 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0},
196 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0},
199 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0},
200 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0},
203 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0},
204 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0},
205 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0},
206 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0},
207 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0},
208 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0},
209 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0},
210 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0},
211 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0},
212 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0},
213 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0},
214 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0},
217 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0},
218 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0},
219 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0},
220 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0},
221 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0},
222 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0},
224 // 32-bit access registers
225 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
226 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
227 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0},
228 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0},
231 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0},
232 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP},
234 // load/store multiple
235 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0},
236 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP},
237 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0},
238 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP},
241 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0},
242 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0},
243 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0},
244 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0},
246 // fast synchronization
247 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0},
250 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP},
251 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0},
253 // storage and storage
254 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0},
255 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP},
256 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP},
259 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0},
260 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0},
261 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0},
262 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP},
263 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0},
266 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0},
267 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0},
268 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0},
269 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0},
270 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0},
272 // vector instructions
275 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0},
276 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP},
277 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0},
278 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP},
281 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0},
282 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP},
283 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0},
284 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP},
287 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0},
288 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP},
291 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0},
292 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP},
294 // VRS element shift/rotate and load gr to/from vr element
295 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0},
296 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0},
297 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0},
298 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0},
299 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0},
300 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0},
301 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0},
302 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0},
304 // VRS store multiple
305 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0},
306 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP},
309 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0},
310 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP},
312 // VRS store with length
313 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0},
314 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP},
316 // VRS load with length
317 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0},
318 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP},
321 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0},
322 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0},
323 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0},
324 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0},
325 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0},
326 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0},
328 // VRI-b generate mask
329 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0},
332 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0},
334 // VRI-d element rotate and insert under mask and
335 // shift left double by byte
336 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0},
337 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0},
339 // VRI-d fp test data class immediate
340 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0},
343 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0},
346 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0},
349 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
350 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
351 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
354 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0},
355 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0},
356 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0},
357 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0},
360 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0},
361 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0},
365 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0},
368 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0},
371 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0},
374 var oprange [ALAST & obj.AMask][]Optab
376 var xcmp [C_NCLASS][C_NCLASS]bool
378 func spanz(ctxt *obj.Link, cursym *obj.LSym) {
380 if p == nil || p.Link == nil { // handle external functions and ELF section symbols
384 ctxt.Autosize = int32(p.To.Offset)
386 if oprange[AANDN&obj.AMask] == nil {
390 buffer := make([]byte, 0)
395 ctxt.Diag("stuck in spanz loop")
400 ctxt.Cursym.R = make([]obj.Reloc, 0)
401 for p := cursym.Text; p != nil; p = p.Link {
402 pc := int64(len(buffer))
409 asmout(ctxt, &buffer)
410 if pc == int64(len(buffer)) {
412 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
415 ctxt.Diag("zero-width instruction\n%v", p)
422 cursym.Size = int64(len(buffer))
423 if cursym.Size%FuncAlign != 0 {
424 cursym.Size += FuncAlign - (cursym.Size % FuncAlign)
426 cursym.Grow(cursym.Size)
427 copy(cursym.P, buffer)
430 func isint32(v int64) bool {
431 return int64(int32(v)) == v
434 func isuint32(v uint64) bool {
435 return uint64(uint32(v)) == v
438 func aclass(ctxt *obj.Link, a *obj.Addr) int {
444 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
447 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
450 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
453 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
460 case obj.NAME_EXTERN,
463 // must have a symbol
466 ctxt.Instoffset = a.Offset
467 if a.Sym.Type == obj.STLSBSS {
468 if ctxt.Flag_shared {
469 return C_TLS_IE // initial exec model
471 return C_TLS_LE // local exec model
475 case obj.NAME_GOTREF:
479 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
480 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
486 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize()
487 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
493 ctxt.Instoffset = a.Offset
494 if ctxt.Instoffset == 0 {
497 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
505 case obj.TYPE_TEXTSIZE:
508 case obj.TYPE_FCONST:
509 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
512 ctxt.Diag("cannot handle the floating point constant %v", a.Val)
518 ctxt.Instoffset = a.Offset
520 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG {
523 if isint32(ctxt.Instoffset) {
530 case obj.NAME_EXTERN,
536 ctxt.Instoffset = a.Offset
537 if s.Type == obj.SCONST {
544 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
545 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
551 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize()
552 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
561 if ctxt.Instoffset == 0 {
564 if ctxt.Instoffset >= 0 {
565 if ctxt.Instoffset <= 0x7fff {
568 if ctxt.Instoffset <= 0xffff {
571 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */
574 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) {
580 if ctxt.Instoffset >= -0x8000 {
583 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) {
586 if isint32(ctxt.Instoffset) {
591 case obj.TYPE_BRANCH:
598 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab {
603 a1 = int(p.From.Class)
605 a1 = aclass(ctxt, &p.From) + 1
606 p.From.Class = int8(a1)
612 a3 = int(p.From3.Class)
614 a3 = aclass(ctxt, p.From3) + 1
615 p.From3.Class = int8(a3)
620 a4 := int(p.To.Class)
622 a4 = aclass(ctxt, &p.To) + 1
623 p.To.Class = int8(a4)
629 if REG_R0 <= p.Reg && p.Reg <= REG_R15 {
631 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
633 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 {
635 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 {
640 ops := oprange[p.As&obj.AMask]
647 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] {
648 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
653 // cannot find a case; abort
654 ctxt.Diag("illegal combination %v %v %v %v %v\n", obj.Aconv(p.As), DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4))
655 ctxt.Diag("prog: %v\n", p)
659 func cmp(a int, b int) bool {
670 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
675 if b == C_ZCON || b == C_SCON {
680 if b == C_ZCON || b == C_SCON {
685 if b == C_ZCON || b == C_SCON {
710 if b == C_ZOREG || b == C_SOREG {
728 func (x ocmp) Len() int {
732 func (x ocmp) Swap(i, j int) {
733 x[i], x[j] = x[j], x[i]
736 func (x ocmp) Less(i, j int) bool {
739 n := int(p1.as) - int(p2.as)
743 n = int(p1.a1) - int(p2.a1)
747 n = int(p1.a2) - int(p2.a2)
751 n = int(p1.a3) - int(p2.a3)
755 n = int(p1.a4) - int(p2.a4)
761 func opset(a, b obj.As) {
762 oprange[a&obj.AMask] = oprange[b&obj.AMask]
765 func buildop(ctxt *obj.Link) {
766 for i := 0; i < C_NCLASS; i++ {
767 for n := 0; n < C_NCLASS; n++ {
773 sort.Sort(ocmp(optab))
774 for i := 0; i < len(optab); i++ {
777 for ; i+1 < len(optab); i++ {
778 if optab[i+1].as != r {
782 oprange[r&obj.AMask] = optab[start : i+1]
784 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array.
785 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog.
1301 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32)
1302 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP)
1303 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP)
1304 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP)
1305 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP)
1306 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP)
1307 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP)
1308 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP)
1309 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP)
1310 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP)
1311 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP)
1312 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32)
1313 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64)
1314 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32)
1315 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32)
1316 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32)
1317 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64)
1318 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16)
1319 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64)
1320 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64)
1321 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8)
1322 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD
1323 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32)
1324 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32)
1325 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32)
1326 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16)
1327 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD
1328 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32)
1329 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32)
1330 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32)
1331 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64)
1332 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64)
1333 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32)
1334 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32)
1335 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64)
1336 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32)
1337 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32)
1338 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32)
1339 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16)
1340 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64)
1341 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64)
1342 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8)
1343 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32)
1344 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32)
1345 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16)
1346 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32)
1347 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32)
1348 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8)
1349 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32)
1350 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32)
1351 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32)
1352 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL
1353 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32)
1354 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32)
1355 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8)
1356 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP)
1357 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP)
1358 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP)
1359 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP)
1360 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP)
1361 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP)
1362 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP)
1363 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP)
1364 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32)
1365 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK
1366 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK
1367 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK
1368 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE
1369 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE
1370 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE
1371 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION
1372 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION
1373 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32)
1374 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64)
1375 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64)
1376 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32)
1377 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD
1378 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD
1379 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE
1380 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG
1381 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION
1382 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG
1383 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32)
1384 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64)
1385 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32)
1386 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32)
1387 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64)
1388 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32)
1389 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64)
1390 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY
1391 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP
1392 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE
1393 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32)
1394 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64)
1395 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32)
1396 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64)
1397 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32)
1398 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP)
1399 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP)
1400 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP)
1401 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP)
1402 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP)
1403 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP)
1404 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP)
1405 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP)
1406 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP)
1407 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP)
1408 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP)
1409 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP)
1410 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP)
1411 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP)
1412 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP)
1413 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP)
1414 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP)
1415 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32)
1416 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64)
1417 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP)
1418 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32)
1419 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP)
1420 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP)
1421 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP)
1422 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP)
1423 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP)
1424 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP)
1425 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP)
1426 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP)
1427 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP)
1428 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP)
1429 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP)
1430 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP)
1431 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP)
1432 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP)
1433 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP)
1434 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP)
1435 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP)
1436 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD
1437 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32)
1438 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32)
1439 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32)
1440 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32)
1441 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32)
1442 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32)
1443 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32)
1444 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32)
1445 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32)
1446 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32)
1447 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32)
1448 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32)
1449 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64)
1450 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64)
1451 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64)
1452 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64)
1453 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64)
1454 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64)
1455 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64)
1456 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64)
1457 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64)
1458 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32)
1459 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32)
1460 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32)
1461 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32)
1462 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16)
1463 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16)
1464 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16)
1465 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16)
1466 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8)
1467 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8)
1468 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16)
1469 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64)
1470 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64)
1471 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64)
1472 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64)
1473 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64)
1474 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64)
1475 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64)
1476 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64)
1477 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64)
1478 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64)
1479 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16)
1480 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32)
1481 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32)
1482 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16)
1483 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16)
1484 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32)
1485 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16)
1486 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16)
1487 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16)
1488 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8)
1489 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32)
1490 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8)
1491 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16)
1492 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM
1493 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32)
1494 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character)
1495 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG
1496 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED
1497 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE
1498 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32)
1499 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32)
1500 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32)
1501 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16)
1502 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32)
1503 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16)
1504 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32)
1505 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32)
1506 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64)
1507 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64)
1508 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64)
1509 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64)
1510 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32)
1511 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32)
1512 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32)
1513 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32)
1514 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16)
1515 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16)
1516 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8)
1517 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8)
1518 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16)
1519 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64)
1520 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64)
1521 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64)
1522 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64)
1523 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64)
1524 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64)
1525 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64)
1526 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64)
1527 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32)
1528 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32)
1529 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16)
1530 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32)
1531 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16)
1532 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate)
1533 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8)
1534 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32)
1535 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8)
1536 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate)
1537 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low)
1538 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high)
1539 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low)
1540 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32)
1541 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32)
1542 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32)
1543 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32)
1544 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32)
1545 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING
1546 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32)
1547 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32)
1548 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL
1549 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL
1550 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long)
1551 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS
1552 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32)
1553 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32)
1554 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY
1555 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32)
1556 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32)
1557 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32)
1558 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32)
1559 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL
1560 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64)
1561 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64)
1562 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE
1563 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE
1564 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE
1565 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128)
1566 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32)
1567 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16
1568 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32
1569 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8
1570 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32
1571 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8
1572 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16
1573 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64)
1574 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL
1575 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE
1576 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8
1577 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128)
1578 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32)
1579 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64)
1580 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32)
1581 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32)
1582 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64)
1583 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32)
1584 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP)
1585 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP)
1586 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP)
1587 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP)
1588 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP)
1589 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP)
1590 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP)
1591 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP)
1592 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP)
1593 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP)
1594 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP)
1595 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP)
1596 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP)
1597 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP)
1598 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP)
1599 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP)
1600 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP)
1601 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP)
1602 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP)
1603 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32)
1604 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP)
1605 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP)
1606 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64)
1607 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP)
1608 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP)
1609 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP)
1610 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP)
1611 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP)
1612 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP)
1613 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP)
1614 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP)
1615 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP)
1616 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP)
1617 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP)
1618 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP)
1619 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64)
1620 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128)
1621 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128)
1622 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64)
1623 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL
1624 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64)
1625 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64)
1626 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32)
1627 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32)
1628 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64)
1629 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP)
1630 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP)
1631 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP)
1632 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP)
1633 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS
1634 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE
1635 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME
1636 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT
1637 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK
1638 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64)
1639 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64)
1640 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC
1641 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE
1642 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN
1643 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW
1644 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32)
1645 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64)
1646 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE
1647 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN
1648 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP)
1649 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY
1650 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE
1651 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP)
1652 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH
1653 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE
1654 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG
1655 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP)
1656 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP)
1657 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP)
1658 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP)
1659 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP)
1660 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP)
1661 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP)
1662 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP)
1663 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP)
1664 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP)
1665 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP)
1666 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE
1667 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP)
1668 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP)
1669 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL
1670 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL
1671 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER
1672 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low)
1673 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high)
1674 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low)
1675 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER
1676 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY
1677 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP)
1678 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP)
1679 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high)
1680 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high)
1681 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low)
1682 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low)
1683 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high)
1684 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low)
1685 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY
1686 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK
1687 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY
1688 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED
1689 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY
1690 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP)
1691 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP)
1692 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP)
1693 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP)
1694 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP)
1695 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST
1696 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST
1697 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE
1698 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE
1699 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING
1700 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER
1701 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB
1702 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB
1703 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP)
1704 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP)
1705 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32)
1706 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS
1707 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32)
1708 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64)
1709 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32)
1710 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64)
1711 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED
1712 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED
1713 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE
1714 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE
1715 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32)
1716 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64)
1717 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32)
1718 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64)
1719 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG
1720 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS
1721 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32)
1722 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32)
1723 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64)
1724 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS
1725 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32)
1726 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8)
1727 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32)
1728 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP)
1729 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long)
1730 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP)
1731 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP)
1732 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP)
1733 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32)
1734 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64)
1735 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32)
1736 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32)
1737 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64)
1738 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP)
1739 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP)
1740 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long)
1741 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP)
1742 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP)
1743 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP)
1744 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP)
1745 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP)
1746 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long)
1747 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long)
1748 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP)
1749 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP)
1750 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP)
1751 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP)
1752 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long)
1753 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short)
1754 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP)
1755 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP)
1756 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP)
1757 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP)
1758 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short)
1759 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP)
1760 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP)
1761 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP)
1762 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short)
1763 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL
1764 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32)
1765 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32)
1766 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC
1767 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64)
1768 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64)
1769 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64)
1770 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64)
1771 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64)
1772 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32)
1773 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32)
1774 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32)
1775 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32)
1776 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64)
1777 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64)
1778 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64)
1779 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16)
1780 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64)
1781 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64)
1782 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32)
1783 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16)
1784 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32)
1785 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32)
1786 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16)
1787 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32)
1788 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32)
1789 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8)
1790 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32)
1791 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64)
1792 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64)
1793 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32)
1794 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32)
1795 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32)
1796 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32)
1797 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64)
1798 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64)
1799 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16)
1800 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS
1801 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31)
1802 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS
1803 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32)
1804 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16)
1805 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32)
1806 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16)
1807 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high)
1808 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high)
1809 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low)
1810 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low)
1811 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high)
1812 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low)
1813 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32)
1814 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT
1815 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64)
1816 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH
1817 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32)
1818 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP)
1819 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long)
1820 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP)
1821 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP)
1822 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP)
1823 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32)
1824 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64)
1825 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32)
1826 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP)
1827 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP)
1828 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32)
1829 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64)
1830 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64)
1831 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32)
1832 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32)
1833 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP)
1834 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long)
1835 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64)
1836 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP)
1837 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP)
1838 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP)
1839 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32)
1840 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64)
1841 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD
1842 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32)
1843 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW
1844 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED
1845 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS
1846 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP)
1847 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP)
1848 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32)
1849 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32)
1850 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64)
1851 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32)
1852 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP)
1853 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP)
1854 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32)
1855 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32)
1856 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64)
1857 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64)
1858 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16)
1859 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32)
1860 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32)
1861 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP)
1862 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP)
1863 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP)
1864 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP)
1865 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP)
1866 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64)
1867 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32)
1868 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32)
1869 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64)
1870 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32)
1871 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP)
1872 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP)
1873 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP)
1874 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32)
1875 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64)
1876 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP)
1877 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP)
1878 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP)
1879 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP)
1880 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP)
1881 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP)
1882 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP)
1883 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP)
1884 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP)
1885 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended)
1886 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32)
1887 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long)
1888 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short)
1889 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended)
1890 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32)
1891 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP)
1892 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP)
1893 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP)
1894 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP)
1895 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP)
1896 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP)
1897 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP)
1898 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP)
1899 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP)
1900 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP)
1901 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP)
1902 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP)
1903 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP)
1904 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP)
1905 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL
1906 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP)
1907 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP)
1908 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP)
1909 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP)
1910 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP)
1911 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP)
1912 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP)
1913 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP)
1914 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP)
1915 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP)
1916 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP)
1917 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP)
1918 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP)
1919 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP)
1920 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP)
1921 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP)
1922 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32)
1923 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64)
1924 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32)
1925 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32)
1926 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32)
1927 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32)
1928 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64)
1929 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64)
1930 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32)
1931 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL
1932 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32)
1933 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32)
1934 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL
1935 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP)
1936 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP)
1937 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP)
1938 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP)
1939 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP)
1940 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP)
1941 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP)
1942 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP)
1943 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32)
1944 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64)
1945 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32)
1946 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32)
1947 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32)
1948 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64)
1949 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32)
1950 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE
1951 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32)
1952 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character)
1953 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY
1954 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE
1955 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY
1956 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG
1957 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED
1958 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE
1959 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS
1960 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY
1961 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY
1962 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY
1963 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16)
1964 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16)
1965 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16)
1966 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate)
1967 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate)
1968 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS
1969 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET
1970 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE
1971 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING
1972 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES
1973 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP)
1974 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP)
1975 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP)
1976 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP)
1977 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP)
1978 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP)
1979 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP)
1980 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP)
1981 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP)
1982 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP)
1983 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP)
1984 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP)
1985 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP)
1986 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP)
1987 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32)
1988 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character)
1989 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64)
1990 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64)
1991 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64)
1992 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate)
1993 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT
1994 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high)
1995 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high)
1996 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low)
1997 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low)
1998 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high)
1999 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low)
2000 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate)
2001 op_NR uint32 = 0x1400 // FORMAT_RR AND (32)
2002 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32)
2003 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE
2004 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32)
2005 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32)
2006 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character)
2007 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64)
2008 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64)
2009 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64)
2010 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate)
2011 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high)
2012 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high)
2013 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low)
2014 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low)
2015 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high)
2016 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low)
2017 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate)
2018 op_OR uint32 = 0x1600 // FORMAT_RR OR (32)
2019 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32)
2020 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32)
2021 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK
2022 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB
2023 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL
2024 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION
2025 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS
2026 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA
2027 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG
2028 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION
2029 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION
2030 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN
2031 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT
2032 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII
2033 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE
2034 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION
2035 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT
2036 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST
2037 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN
2038 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER
2039 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION
2040 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION
2041 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE
2042 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB
2043 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP)
2044 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP)
2045 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH
2046 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS
2047 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS
2048 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH
2049 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW
2050 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32)
2051 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64)
2052 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS
2053 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS
2054 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM
2055 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED
2056 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE
2057 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP)
2058 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP)
2059 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL
2060 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS
2061 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32)
2062 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL
2063 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST
2064 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT
2065 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24)
2066 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31)
2067 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64)
2068 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS
2069 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR
2070 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK
2071 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR
2072 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD
2073 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP)
2074 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP)
2075 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP)
2076 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP)
2077 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP)
2078 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP)
2079 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP)
2080 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP)
2081 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP)
2082 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP)
2083 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL
2084 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC
2085 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64)
2086 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32)
2087 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32)
2088 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64)
2089 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64)
2090 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD
2091 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32)
2092 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32)
2093 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD
2094 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR
2095 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32)
2096 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32)
2097 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64)
2098 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32)
2099 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32)
2100 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64)
2101 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64)
2102 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32)
2103 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE
2104 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL
2105 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP)
2106 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32)
2107 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64)
2108 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32)
2109 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32)
2110 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32)
2111 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64)
2112 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64)
2113 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32)
2114 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32)
2115 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32)
2116 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64)
2117 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32)
2118 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32)
2119 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32)
2120 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP)
2121 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32)
2122 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL
2123 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS
2124 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK
2125 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER
2126 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX
2127 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP)
2128 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP)
2129 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP)
2130 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP)
2131 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP)
2132 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP)
2133 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP)
2134 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP)
2135 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP)
2136 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP)
2137 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32)
2138 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32)
2139 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64)
2140 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32)
2141 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE
2142 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL
2143 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP)
2144 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32)
2145 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32)
2146 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64)
2147 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32)
2148 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit)
2149 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit)
2150 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE
2151 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL
2152 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING
2153 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE
2154 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP)
2155 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE
2156 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN
2157 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL
2158 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED
2159 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK
2160 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32)
2161 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE
2162 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE
2163 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS
2164 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER
2165 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8)
2166 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK
2167 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR
2168 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED
2169 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST
2170 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low)
2171 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high)
2172 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low)
2173 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS
2174 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD
2175 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64)
2176 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32)
2177 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER
2178 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long)
2179 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long)
2180 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short)
2181 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short)
2182 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32)
2183 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST
2184 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED
2185 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC
2186 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64)
2187 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64)
2188 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD
2189 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16)
2190 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG
2191 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD
2192 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID
2193 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32)
2194 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64)
2195 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH
2196 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32)
2197 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK
2198 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32)
2199 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64)
2200 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK
2201 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD
2202 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER
2203 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX
2204 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS
2205 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32)
2206 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32)
2207 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64)
2208 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16)
2209 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL
2210 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION
2211 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32)
2212 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64)
2213 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32)
2214 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP)
2215 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP)
2216 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL
2217 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP)
2218 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP)
2219 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP)
2220 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP)
2221 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP)
2222 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP)
2223 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32)
2224 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT
2225 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE
2226 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS
2227 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK
2228 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long)
2229 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short)
2230 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN
2231 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN
2232 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP)
2233 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP)
2234 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP)
2235 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP)
2236 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP)
2237 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP)
2238 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP)
2239 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP)
2240 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP)
2241 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END
2242 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long)
2243 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long)
2244 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK
2245 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH
2246 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high)
2247 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low)
2248 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW
2249 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high)
2250 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low)
2251 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK
2252 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL
2253 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION
2254 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION
2255 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE
2256 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32)
2257 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64)
2258 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP
2259 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP
2260 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED
2261 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE
2262 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO
2263 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST
2264 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED
2265 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE
2266 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE
2267 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED
2268 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO
2269 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET
2270 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL
2271 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK
2272 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII
2273 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE
2274 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE
2275 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32)
2276 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character)
2277 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64)
2278 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64)
2279 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64)
2280 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate)
2281 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high)
2282 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low)
2283 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate)
2284 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32)
2285 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32)
2286 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL
2287 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32)
2288 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD
2291 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP)
2292 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP)
2293 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP)
2294 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP)
2295 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32)
2296 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64)
2297 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY
2298 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16)
2299 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16)
2300 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16)
2301 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32)
2302 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32)
2303 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32)
2304 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION
2305 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD
2306 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY
2307 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY
2308 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY
2309 op_VN uint32 = 0xE768 // VRR-c VECTOR AND
2310 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT
2311 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE
2312 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL
2313 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM
2314 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL
2315 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH
2316 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL
2317 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS
2318 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS
2319 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE
2320 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL
2321 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
2322 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL
2323 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL
2324 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT
2325 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT
2326 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC
2327 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC
2328 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL
2329 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL
2330 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR
2331 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL
2332 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL
2333 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL
2334 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD
2335 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR
2336 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL
2337 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH
2338 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL
2339 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR
2340 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT
2341 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT
2342 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT
2343 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT
2344 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE
2345 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED
2346 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED
2347 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY
2348 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD
2349 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT
2350 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION
2351 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT
2352 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT
2353 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE
2354 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM
2355 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE
2356 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32)
2357 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64)
2358 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK
2359 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK
2360 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING
2361 op_VL uint32 = 0xE706 // VRX VECTOR LOAD
2362 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD
2363 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE
2364 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT
2365 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16)
2366 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32)
2367 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64)
2368 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8)
2369 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16)
2370 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32)
2371 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64)
2372 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8)
2373 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER
2374 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT
2375 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO
2376 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE
2377 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE
2378 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY
2379 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR
2380 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT
2381 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH
2382 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM
2383 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL
2384 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH
2385 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW
2386 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM
2387 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL
2388 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN
2389 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH
2390 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN
2391 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH
2392 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD
2393 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW
2394 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD
2395 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN
2396 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH
2397 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL
2398 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL
2399 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL
2400 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW
2401 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD
2402 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR
2403 op_VO uint32 = 0xE76A // VRR-c VECTOR OR
2404 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK
2405 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE
2406 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE
2407 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE
2408 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE
2409 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT
2410 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE
2411 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE
2412 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32)
2413 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64)
2414 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT
2415 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT
2416 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE
2417 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE
2418 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC
2419 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE
2420 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL
2421 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE
2422 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD
2423 op_VST uint32 = 0xE70E // VRX VECTOR STORE
2424 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16)
2425 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32)
2426 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64)
2427 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8)
2428 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE
2429 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH
2430 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE
2431 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT
2432 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION
2433 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
2434 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION
2435 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD
2436 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD
2437 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD
2438 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK
2439 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH
2440 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH
2441 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW
2442 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW
2445 func oclass(a *obj.Addr) int {
2446 return int(a.Class) - 1
2449 // Add a relocation for the immediate in a RIL style instruction.
2450 // The addend will be adjusted as required.
2451 func addrilreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc {
2453 ctxt.Diag("require symbol to apply relocation")
2455 offset := int64(2) // relocation offset from start of instruction
2456 rel := obj.Addrel(ctxt.Cursym)
2457 rel.Off = int32(ctxt.Pc + offset)
2460 rel.Add = add + offset + int64(rel.Siz)
2461 rel.Type = obj.R_PCRELDBL
2465 func addrilrelocoffset(ctxt *obj.Link, sym *obj.LSym, add, offset int64) *obj.Reloc {
2467 ctxt.Diag("require symbol to apply relocation")
2469 offset += int64(2) // relocation offset from start of instruction
2470 rel := obj.Addrel(ctxt.Cursym)
2471 rel.Off = int32(ctxt.Pc + offset)
2474 rel.Add = add + offset + int64(rel.Siz)
2475 rel.Type = obj.R_PCRELDBL
2479 // Add a CALL relocation for the immediate in a RIL style instruction.
2480 // The addend will be adjusted as required.
2481 func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc {
2483 ctxt.Diag("require symbol to apply relocation")
2485 offset := int64(2) // relocation offset from start of instruction
2486 rel := obj.Addrel(ctxt.Cursym)
2487 rel.Off = int32(ctxt.Pc + offset)
2490 rel.Add = add + offset + int64(rel.Siz)
2491 rel.Type = obj.R_CALL
2495 func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 {
2497 case ABEQ, ACMPBEQ, ACMPUBEQ:
2499 case ABGE, ACMPBGE, ACMPUBGE:
2501 case ABGT, ACMPBGT, ACMPUBGT:
2503 case ABLE, ACMPBLE, ACMPUBLE:
2505 case ABLT, ACMPBLT, ACMPUBLT:
2507 case ABNE, ACMPBNE, ACMPUBNE:
2510 return 0x0 //needs extra instruction
2514 ctxt.Diag("unknown conditional branch %v", p.As)
2518 func asmout(ctxt *obj.Link, asm *[]byte) {
2520 o := oplook(ctxt, p)
2525 ctxt.Diag("unknown type %d", o.type_)
2527 case 0: // PSEUDO OPS
2530 case 1: // mov reg reg
2533 ctxt.Diag("unhandled operation: %v", p.As)
2535 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2538 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2540 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2542 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2545 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2547 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2549 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2552 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2554 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2556 case AFMOVD, AFMOVS:
2557 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2560 case 2: // arithmetic op reg [reg] reg
2570 ctxt.Diag("invalid opcode")
2607 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2609 case AADDE, AMULLW, AMULLD:
2610 if r == int(p.To.Reg) {
2611 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2612 } else if p.From.Reg == p.To.Reg {
2613 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2615 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2616 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2619 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2620 if p.As == ADIVWU || p.As == ADIVDU {
2621 zRRE(op_LGR, REGTMP, REGZERO, asm)
2623 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2624 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm)
2625 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2628 if r == int(p.To.Reg) {
2629 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2630 } else if p.From.Reg == p.To.Reg {
2631 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2633 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm)
2634 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2637 case AFSUB, AFSUBS, AFDIV, AFDIVS:
2638 if r == int(p.To.Reg) {
2639 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2640 } else if p.From.Reg == p.To.Reg {
2641 zRRE(op_LGDR, REGTMP, uint32(r), asm)
2642 zRRE(opcode, uint32(r), uint32(p.From.Reg), asm)
2643 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm)
2644 zRRE(op_LDGR, uint32(r), REGTMP, asm)
2646 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm)
2647 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2652 case 3: // mov $constant reg
2653 v := vregoff(ctxt, &p.From)
2658 v = int64(uint16(v))
2660 v = int64(uint32(v))
2669 zRI(op_LLILL, uint32(p.To.Reg), uint32(v), asm)
2670 } else if v&0xffff0000 == v {
2671 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2672 } else if v&0xffff00000000 == v {
2673 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2674 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2675 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2676 } else if int64(int16(v)) == v {
2677 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2678 } else if int64(int32(v)) == v {
2679 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2680 } else if int64(uint32(v)) == v {
2681 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2682 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2683 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2685 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2686 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2689 case 4: // multiply high (a*b)>>64
2694 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2695 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm)
2698 // Unsigned: move result into correct register.
2699 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm)
2701 // Signed: need to convert result.
2702 // See Hacker's Delight 8-3.
2703 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2704 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2705 zRRE(op_SGR, REGTMP, REGTMP2, asm)
2706 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2707 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2708 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm)
2714 case 6: // logical op reg [reg] reg
2716 ctxt.Diag("literal operation on R0\n%v", p)
2720 case AAND, AOR, AXOR:
2721 var opcode1, opcode2 uint32
2737 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2739 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2743 var opcode1, opcode2 uint32
2756 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm)
2757 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2759 zRRE(op_LCGR, REGTMP, uint32(r), asm)
2760 zRRF(opcode2, REGTMP, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2764 var opcode1, opcode2 uint32
2777 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2779 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2782 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm)
2785 case 7: // shift/rotate reg [reg] reg
2786 d2 := vregoff(ctxt, &p.From)
2813 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2815 case 10: // subtract reg [reg] reg
2822 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2824 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2828 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2830 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2837 if r == int(p.To.Reg) {
2838 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2839 } else if p.From.Reg == p.To.Reg {
2840 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
2841 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2842 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm)
2844 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2845 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2853 v = int32((p.Pcond.Pc - p.Pc) >> 1)
2856 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
2857 zRI(op_BRC, 0xF, uint32(v), asm)
2860 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
2862 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
2864 if p.To.Sym != nil {
2865 addcallreloc(ctxt, p.To.Sym, p.To.Offset)
2869 case 15: // br/bl (reg)
2871 if p.As == ABCL || p.As == ABL {
2872 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
2874 zRR(op_BCR, 0xF, uint32(r), asm)
2877 case 16: // conditional branch
2880 v = int32((p.Pcond.Pc - p.Pc) >> 1)
2882 mask := branchMask(ctxt, p)
2883 if p.To.Sym == nil && int32(int16(v)) == v {
2884 zRI(op_BRC, mask, uint32(v), asm)
2886 zRIL(_c, op_BRCL, mask, uint32(v), asm)
2888 if p.To.Sym != nil {
2889 addrilreloc(ctxt, p.To.Sym, p.To.Offset)
2892 case 18: // br/bl reg
2894 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
2896 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm)
2899 case 19: // mov $sym+n(SB) reg
2900 d := vregoff(ctxt, &p.From)
2901 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
2903 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
2906 addrilreloc(ctxt, p.From.Sym, d)
2908 case 22: // arithmetic op $constant [reg] reg
2909 if p.From.Sym != nil {
2910 ctxt.Diag("%v is not supported", p)
2912 v := vregoff(ctxt, &p.From)
2921 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm)
2922 } else if int64(int16(v)) == v {
2923 zRIE(_d, op_AGHIK, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
2925 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2926 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm)
2930 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2932 zRIL(_a, op_ALGFI, uint32(p.To.Reg), uint32(v), asm)
2933 case AMULLW, AMULLD:
2935 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2937 if int64(int16(v)) == v {
2938 zRI(op_MGHI, uint32(p.To.Reg), uint32(v), asm)
2940 zRIL(_a, op_MSGFI, uint32(p.To.Reg), uint32(v), asm)
2944 case 23: // logical op $constant [reg] reg
2945 v := vregoff(ctxt, &p.From)
2954 ctxt.Diag("%v is not supported", p)
2956 if v >= 0 { // needs zero extend
2957 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
2958 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm)
2959 } else if int64(int16(v)) == v {
2960 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
2961 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v)
2962 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
2965 if int64(uint32(v)) != v { // needs sign extend
2966 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
2967 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm)
2968 } else if int64(uint16(v)) == v {
2969 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
2971 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
2974 if int64(uint32(v)) != v { // needs sign extend
2975 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
2976 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm)
2978 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
2984 ctxt.Diag("%v is not supported", p)
2992 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
2993 zRRF(opcode, uint32(r), 0, uint32(p.To.Reg), REGTMP, asm)
2996 case 26: // mov $addr/sym reg
2997 v := regoff(ctxt, &p.From)
3002 if v >= 0 && v < DISP12 {
3003 zRX(op_LA, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm)
3004 } else if v >= -DISP20/2 && v < DISP20/2 {
3005 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm)
3007 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3008 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, 0, asm)
3012 wd := uint64(vregoff(ctxt, &p.From))
3023 case 32: // fmul freg [freg] freg
3033 ctxt.Diag("invalid opcode")
3040 if r == int(p.To.Reg) {
3041 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3042 } else if p.From.Reg == p.To.Reg {
3043 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3045 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm)
3046 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3049 case 33: // float op [freg] freg
3051 if oclass(&p.From) == C_NONE {
3072 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3074 case 34: // float multiply-add freg freg freg freg
3079 ctxt.Diag("invalid opcode")
3098 zRR(op_LDR, uint32(p.To.Reg), uint32(p.Reg), asm)
3099 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From3.Reg), asm)
3101 if p.As == AFNMADD || p.As == AFNMADDS || p.As == AFNMSUB || p.As == AFNMSUBS {
3102 zRRE(op_LCDFR, uint32(p.To.Reg), uint32(p.To.Reg), asm)
3105 case 35: // mov reg mem (no relocation)
3106 d2 := regoff(ctxt, &p.To)
3112 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3113 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm)
3115 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm)
3120 zRXY(zopstore(ctxt, p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3122 case 36: // mov mem reg (no relocation)
3123 d2 := regoff(ctxt, &p.From)
3129 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3130 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm)
3132 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm)
3137 zRXY(zopload(ctxt, p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3139 case 40: // word/byte
3140 wd := uint32(regoff(ctxt, &p.From))
3141 if p.As == AWORD { //WORD
3142 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3144 *asm = append(*asm, uint8(wd))
3147 case 47: // arithmetic op (carry) reg [reg] reg
3152 r := int(p.From.Reg)
3153 if p.To.Reg == p.From.Reg {
3154 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
3157 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
3158 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
3161 r := int(p.From.Reg)
3162 if p.To.Reg == p.From.Reg {
3163 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
3166 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0
3167 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
3170 r := int(p.From.Reg)
3171 if p.To.Reg == p.From.Reg {
3172 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
3175 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
3176 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
3179 r := int(p.From.Reg)
3180 if p.To.Reg == p.From.Reg {
3181 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
3184 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0
3185 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
3188 r := int(p.From.Reg)
3192 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3195 case 67: // fmov $0 freg
3203 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3205 case 68: // movw areg reg
3206 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3208 case 69: // movw reg areg
3209 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3211 case 70: // cmp reg reg
3212 if p.As == ACMPW || p.As == ACMPWU {
3213 zRR(zoprr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3215 zRRE(zoprre(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3218 case 71: // cmp reg $constant
3219 v := vregoff(ctxt, &p.To)
3222 if int64(int32(v)) != v {
3223 ctxt.Diag("%v overflows an int32", v)
3226 if int64(uint32(v)) != v {
3227 ctxt.Diag("%v overflows a uint32", v)
3230 zRIL(_a, zopril(ctxt, p.As), uint32(p.From.Reg), uint32(regoff(ctxt, &p.To)), asm)
3232 case 72: // mov $constant/$addr mem
3233 v := regoff(ctxt, &p.From)
3234 d := regoff(ctxt, &p.To)
3240 if p.From.Sym != nil {
3241 zRIL(_b, op_LARL, REGTMP, 0, asm)
3244 zRX(op_LA, REGTMP, REGTMP, 0, 1, asm)
3246 addrilreloc(ctxt, p.From.Sym, int64(v))
3247 if d < -DISP20/2 || d >= DISP20/2 {
3248 zRIL(_a, op_LGFI, REGTMP2, uint32(d), asm)
3250 zRRE(op_AGR, REGTMP2, uint32(x), asm)
3255 zRXY(zopstore(ctxt, p.As), REGTMP, uint32(x), uint32(r), uint32(d), asm)
3256 } else if int32(int16(v)) == v && x == 0 {
3257 if d < 0 || d >= DISP12 {
3258 if r == REGTMP || r == REGTMP2 {
3259 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm)
3261 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm)
3262 zRRE(op_AGR, REGTMP, uint32(r), asm)
3278 if opcode == op_MVI {
3279 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3281 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3284 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm)
3285 if d < -DISP20/2 || d >= DISP20/2 {
3287 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm)
3289 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm)
3291 zRRE(op_AGR, REGTMP, uint32(x), asm)
3297 zRXY(zopstore(ctxt, p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm)
3300 case 73: // mov $constant addr (including relocation)
3301 v := regoff(ctxt, &p.From)
3302 d := regoff(ctxt, &p.To)
3308 zRIL(_b, op_LARL, REGTMP, uint32(d), asm)
3309 addrilreloc(ctxt, p.To.Sym, int64(d))
3310 if p.From.Sym != nil {
3311 zRIL(_b, op_LARL, REGTMP2, 0, asm)
3315 zRX(op_LA, REGTMP2, REGTMP2, 0, 1, asm)
3317 addrilrelocoffset(ctxt, p.From.Sym, int64(v), sizeRIL)
3318 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm)
3319 } else if int32(int16(v)) == v {
3331 if opcode == op_MVI {
3332 zSI(opcode, uint32(v), REGTMP, a, asm)
3334 zSIL(opcode, REGTMP, a, uint32(v), asm)
3337 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm)
3338 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm)
3341 case 74: // mov reg addr (including relocation)
3342 i2 := regoff(ctxt, &p.To)
3345 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3346 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions
3347 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3348 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions
3349 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3350 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions
3351 zRIL(_b, op_LARL, REGTMP, 0, asm)
3352 adj := uint32(0) // adjustment needed for odd addresses
3357 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm)
3359 zRIL(_b, op_LARL, REGTMP, 0, asm)
3360 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm)
3362 zRIL(_b, op_LARL, REGTMP, 0, asm)
3363 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm)
3365 addrilreloc(ctxt, p.To.Sym, int64(i2))
3367 case 75: // mov addr reg (including relocation)
3368 i2 := regoff(ctxt, &p.From)
3372 zRIL(_b, op_LARL, REGTMP, 0, asm)
3373 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm)
3376 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3379 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3381 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3383 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3385 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3387 zRIL(_b, op_LARL, REGTMP, 0, asm)
3388 adj := uint32(0) // adjustment needed for odd addresses
3395 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm)
3397 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm)
3400 zRIL(_a, op_LARL, REGTMP, 0, asm)
3401 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm)
3403 zRIL(_a, op_LARL, REGTMP, 0, asm)
3404 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm)
3406 addrilreloc(ctxt, p.From.Sym, int64(i2))
3408 case 77: // syscall $constant
3409 if p.From.Offset > 255 || p.From.Offset < 1 {
3410 ctxt.Diag("illegal system call; system call number out of range: %v", p)
3411 zE(op_TRAP2, asm) // trap always
3413 zI(op_SVC, uint32(p.From.Offset), asm)
3417 // "An instruction consisting entirely of binary 0s is guaranteed
3418 // always to be an illegal instruction."
3419 *asm = append(*asm, 0, 0, 0, 0)
3421 case 79: // compare and swap reg reg reg
3422 v := regoff(ctxt, &p.To)
3427 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3428 } else if p.As == ACSG {
3429 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3433 zRR(op_BCR, 0xE, 0, asm)
3435 case 82: // fixed to float conversion
3439 log.Fatalf("unexpected opcode %v", p.As)
3457 // set immediate operand M3 to 0 to use the default BFP rounding mode
3458 // (usually round to nearest, ties to even)
3459 // TODO(mundaym): should this be fixed at round to nearest, ties to even?
3460 // M4 is reserved and must be 0
3461 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3463 case 83: // float to fixed conversion
3467 log.Fatalf("unexpected opcode %v", p.As)
3485 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec)
3486 // M4 is reserved and must be 0
3487 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3489 case 84: // storage-and-storage operations $length mem mem (length in From3)
3490 l := regoff(ctxt, p.From3)
3491 if l < 1 || l > 256 {
3492 ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3494 if p.From.Index != 0 || p.To.Index != 0 {
3495 ctxt.Diag("cannot use index reg")
3505 d1 := regoff(ctxt, &p.To)
3506 d2 := regoff(ctxt, &p.From)
3507 if d1 < 0 || d1 >= DISP12 {
3509 ctxt.Diag("REGTMP conflict")
3512 zRRE(op_LGR, REGTMP, uint32(b1), asm)
3514 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm)
3515 if d1 == d2 && b1 == b2 {
3522 if d2 < 0 || d2 >= DISP12 {
3524 ctxt.Diag("REGTMP2 conflict")
3527 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3529 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3536 ctxt.Diag("unexpected opcode %v", p.As)
3541 // swap operand order for CLC so that it matches CMP
3551 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3553 case 85: // load address relative long
3554 v := regoff(ctxt, &p.From)
3555 if p.From.Sym == nil {
3557 ctxt.Diag("cannot use LARL with odd offset: %v", v)
3560 addrilreloc(ctxt, p.From.Sym, int64(v))
3563 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3565 case 86: // load address
3566 d := vregoff(ctxt, &p.From)
3574 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3576 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3579 case 87: // execute relative long
3580 v := vregoff(ctxt, &p.From)
3581 if p.From.Sym == nil {
3583 ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3586 addrilreloc(ctxt, p.From.Sym, v)
3589 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3591 case 88: // store clock
3603 v := vregoff(ctxt, &p.To)
3608 zS(opcode, uint32(r), uint32(v), asm)
3610 case 89: // compare and branch reg reg
3613 v = int32((p.Pcond.Pc - p.Pc) >> 1)
3615 var opcode, opcode2 uint32
3617 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3620 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3624 mask := branchMask(ctxt, p)
3625 if int32(int16(v)) != v {
3626 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm)
3627 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm)
3629 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm)
3632 case 90: // compare and branch reg $constant
3635 v = int32((p.Pcond.Pc - p.Pc) >> 1)
3637 var opcode, opcode2 uint32
3639 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3642 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3646 mask := branchMask(ctxt, p)
3647 if int32(int16(v)) != v {
3648 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(regoff(ctxt, p.From3)), asm)
3649 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm)
3651 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(regoff(ctxt, p.From3)), asm)
3654 case 93: // GOT lookup
3655 v := vregoff(ctxt, &p.To)
3657 ctxt.Diag("invalid offset against GOT slot %v", p)
3659 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3660 rel := obj.Addrel(ctxt.Cursym)
3661 rel.Off = int32(ctxt.Pc + 2)
3663 rel.Sym = p.From.Sym
3664 rel.Type = obj.R_GOTPCREL
3665 rel.Add = 2 + int64(rel.Siz)
3667 case 94: // TLS local exec model
3668 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm)
3669 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm)
3670 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
3671 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
3672 rel := obj.Addrel(ctxt.Cursym)
3673 rel.Off = int32(ctxt.Pc + sizeRIL + sizeRXY + sizeRI)
3675 rel.Sym = p.From.Sym
3676 rel.Type = obj.R_TLS_LE
3679 case 95: // TLS initial exec model
3680 // Assembly | Relocation symbol | Done Here?
3681 // --------------------------------------------------------------
3682 // ear %r11, %a0 | |
3683 // sllg %r11, %r11, 32 | |
3684 // ear %r11, %a1 | |
3685 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y
3686 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y
3687 // la %r10, 0(%r10, %r11) | |
3688 // --------------------------------------------------------------
3691 zRIL(_b, op_LARL, REGTMP, 0, asm)
3692 ieent := obj.Addrel(ctxt.Cursym)
3693 ieent.Off = int32(ctxt.Pc + 2)
3695 ieent.Sym = p.From.Sym
3696 ieent.Type = obj.R_TLS_IE
3697 ieent.Add = 2 + int64(ieent.Siz)
3700 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm)
3701 // TODO(mundaym): add R_390_TLS_LOAD relocation here
3702 // not strictly required but might allow the linker to optimize
3704 case 96: // clear macro
3705 length := vregoff(ctxt, &p.From)
3706 offset := vregoff(ctxt, &p.To)
3712 ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
3715 if offset < 0 || offset >= DISP12 {
3716 if offset >= -DISP20/2 && offset < DISP20/2 {
3717 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm)
3720 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3722 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3734 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
3736 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
3738 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
3740 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
3742 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
3749 case 97: // store multiple
3750 rstart := p.From.Reg
3752 offset := regoff(ctxt, &p.To)
3757 if offset < -DISP20/2 || offset >= DISP20/2 {
3759 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3761 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3767 if offset >= 0 && offset < DISP12 {
3768 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3770 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3773 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3776 case 98: // load multiple
3779 offset := regoff(ctxt, &p.From)
3784 if offset < -DISP20/2 || offset >= DISP20/2 {
3786 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3788 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3794 if offset >= 0 && offset < DISP12 {
3795 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3797 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3800 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3803 case 100: // VRX STORE
3804 op, m3, _ := vop(p.As)
3806 m3 = uint32(vregoff(ctxt, p.From3))
3812 d2 := uint32(vregoff(ctxt, &p.To))
3813 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
3815 case 101: // VRX LOAD
3816 op, m3, _ := vop(p.As)
3818 m3 = uint32(vregoff(ctxt, p.From3))
3824 d2 := uint32(vregoff(ctxt, &p.From))
3825 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm)
3827 case 102: // VRV SCATTER
3828 op, m3, _ := vop(p.As)
3830 m3 = uint32(vregoff(ctxt, p.From3))
3836 d2 := uint32(vregoff(ctxt, &p.To))
3837 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
3839 case 103: // VRV GATHER
3840 op, m3, _ := vop(p.As)
3842 m3 = uint32(vregoff(ctxt, p.From3))
3848 d2 := uint32(vregoff(ctxt, &p.From))
3849 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm)
3851 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT
3852 op, m4, _ := vop(p.As)
3857 bits := uint32(vregoff(ctxt, &p.From))
3858 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
3860 case 105: // VRS STORE MULTIPLE
3861 op, _, _ := vop(p.As)
3862 offset := uint32(vregoff(ctxt, &p.To))
3867 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
3869 case 106: // VRS LOAD MULTIPLE
3870 op, _, _ := vop(p.As)
3871 offset := uint32(vregoff(ctxt, &p.From))
3876 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
3878 case 107: // VRS STORE WITH LENGTH
3879 op, _, _ := vop(p.As)
3880 offset := uint32(vregoff(ctxt, &p.To))
3885 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm)
3887 case 108: // VRS LOAD WITH LENGTH
3888 op, _, _ := vop(p.As)
3889 offset := uint32(vregoff(ctxt, &p.From))
3894 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm)
3897 op, _, _ := vop(p.As)
3898 i2 := uint32(vregoff(ctxt, &p.From))
3907 m3 = uint32(vregoff(ctxt, p.From3))
3909 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
3912 op, m4, _ := vop(p.As)
3913 i2 := uint32(vregoff(ctxt, p.From3))
3914 i3 := uint32(vregoff(ctxt, &p.From))
3915 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
3918 op, m4, _ := vop(p.As)
3919 i2 := uint32(vregoff(ctxt, &p.From))
3920 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
3923 op, m5, _ := vop(p.As)
3924 i4 := uint32(vregoff(ctxt, p.From3))
3925 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm)
3928 op, m4, _ := vop(p.As)
3929 m5 := singleElementMask(p.As)
3930 i3 := uint32(vregoff(ctxt, &p.From))
3931 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
3934 op, m3, m5 := vop(p.As)
3935 m4 := singleElementMask(p.As)
3936 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
3938 case 115: // VRR-a COMPARE
3939 op, m3, m5 := vop(p.As)
3940 m4 := singleElementMask(p.As)
3941 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
3946 op, m4, m5 := vop(p.As)
3947 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
3950 op, m4, m6 := vop(p.As)
3951 m5 := singleElementMask(p.As)
3956 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
3958 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.)
3959 op, m4, m6 := vop(p.As)
3960 m5 := singleElementMask(p.As)
3965 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
3968 op, m6, _ := vop(p.As)
3969 m5 := singleElementMask(p.As)
3970 v1 := uint32(p.To.Reg)
3971 v2 := uint32(p.From3.Reg)
3972 v3 := uint32(p.From.Reg)
3974 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
3977 op, m6, _ := vop(p.As)
3978 m5 := singleElementMask(p.As)
3979 v1 := uint32(p.To.Reg)
3980 v2 := uint32(p.From3.Reg)
3981 v3 := uint32(p.From.Reg)
3983 zVRRe(op, v1, v2, v3, m5, m6, v4, asm)
3985 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT
3986 op, _, _ := vop(p.As)
3987 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3989 case 123: // VPDI $m4, V2, V3, V1
3990 op, _, _ := vop(p.As)
3991 m4 := regoff(ctxt, p.From3)
3992 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm)
3996 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 {
4001 return ctxt.Instoffset
4004 func regoff(ctxt *obj.Link, a *obj.Addr) int32 {
4005 return int32(vregoff(ctxt, a))
4008 // zopload returns the RXY op for the given load
4009 func zopload(ctxt *obj.Link, a obj.As) uint32 {
4027 // floating point load
4033 // byte reversed load
4042 ctxt.Diag("unknown store opcode %v", obj.Aconv(a))
4046 // zopstore returns the RXY op for the given store
4047 func zopstore(ctxt *obj.Link, a obj.As) uint32 {
4049 // fixed point store
4059 // floating point store
4065 // byte reversed store
4074 ctxt.Diag("unknown store opcode %v", obj.Aconv(a))
4078 // zoprre returns the RRE op for the given a
4079 func zoprre(ctxt *obj.Link, a obj.As) uint32 {
4085 case AFCMPO: //ordered
4087 case AFCMPU: //unordered
4092 ctxt.Diag("unknown rre opcode %v", obj.Aconv(a))
4096 // zoprr returns the RR op for the given a
4097 func zoprr(ctxt *obj.Link, a obj.As) uint32 {
4104 ctxt.Diag("unknown rr opcode %v", obj.Aconv(a))
4108 // zopril returns the RIL op for the given a
4109 func zopril(ctxt *obj.Link, a obj.As) uint32 {
4120 ctxt.Diag("unknown ril opcode %v", obj.Aconv(a))
4124 // z instructions sizes
4189 // instruction format variations
4201 func zE(op uint32, asm *[]byte) {
4202 *asm = append(*asm, uint8(op>>8), uint8(op))
4205 func zI(op, i1 uint32, asm *[]byte) {
4206 *asm = append(*asm, uint8(op>>8), uint8(i1))
4209 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4212 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4219 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4222 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4227 // Expected argument values for the instruction formats.
4229 // Format a1 a2 a3 a4 a5 a6 a7
4230 // ------------------------------------
4231 // a r1, 0, i2, 0, 0, m3, 0
4232 // b r1, r2, ri4, 0, 0, m3, 0
4233 // c r1, m3, ri4, 0, 0, 0, i2
4234 // d r1, r3, i2, 0, 0, 0, 0
4235 // e r1, r3, ri2, 0, 0, 0, 0
4236 // f r1, r2, 0, i3, i4, 0, i5
4237 // g r1, m3, i2, 0, 0, 0, 0
4238 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4239 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4243 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4245 *asm = append(*asm, uint8(i3), uint8(i4))
4250 *asm = append(*asm, uint8(m3)<<4)
4252 *asm = append(*asm, uint8(i2_i5))
4255 *asm = append(*asm, uint8(op))
4258 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4259 if f == _a || f == _b {
4260 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base
4264 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4271 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4274 (uint8(r1)<<4)|uint8(m3&0x0F),
4275 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4281 func zRR(op, r1, r2 uint32, asm *[]byte) {
4282 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4285 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4290 (uint8(r3)<<4)|uint8(r2&0x0F))
4293 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4298 (uint8(r1)<<4)|uint8(r2&0x0F))
4301 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4305 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4306 (uint8(r1)<<4)|uint8(r2&0x0F))
4309 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4312 (uint8(r1)<<4)|uint8(r2&0x0F),
4313 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4319 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4322 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4323 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4327 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4330 (uint8(r1)<<4)|uint8(r3&0x0F),
4335 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4339 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4344 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4345 dl2 := uint16(d2) & 0x0FFF
4348 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4349 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4355 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4358 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4359 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4363 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4366 (uint8(r1)<<4)|uint8(x2&0x0F),
4367 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4373 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4376 (uint8(r3)<<4)|uint8(x2&0x0F),
4377 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4383 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4384 dl2 := uint16(d2) & 0x0FFF
4387 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4388 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4394 func zS(op, b2, d2 uint32, asm *[]byte) {
4398 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4402 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4406 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4410 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4414 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4420 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4421 dl1 := uint16(d1) & 0x0FFF
4425 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4431 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4435 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4441 // Expected argument values for the instruction formats.
4443 // Format a1 a2 a3 a4 a5 a6
4444 // -------------------------------
4445 // a l1, 0, b1, d1, b2, d2
4446 // b l1, l2, b1, d1, b2, d2
4447 // c l1, i3, b1, d1, b2, d2
4448 // d r1, r3, b1, d1, b2, d2
4449 // e r1, r3, b2, d2, b4, d4
4450 // f 0, l2, b1, d1, b2, d2
4451 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4452 *asm = append(*asm, uint8(op>>8))
4456 *asm = append(*asm, uint8(l1_r1))
4457 case _b, _c, _d, _e:
4458 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4460 *asm = append(*asm, uint8(l2_i3_r3))
4464 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4466 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4470 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4474 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4476 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4480 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4483 (uint8(r3)<<4)|(uint8(op)&0x0F),
4484 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4486 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4490 func rxb(va, vb, vc, vd uint32) uint8 {
4492 if va >= REG_V16 && va <= REG_V31 {
4495 if vb >= REG_V16 && vb <= REG_V31 {
4498 if vc >= REG_V16 && vc <= REG_V31 {
4501 if vd >= REG_V16 && vd <= REG_V31 {
4507 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
4510 (uint8(v1)<<4)|(uint8(x2)&0xf),
4511 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4513 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4517 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
4520 (uint8(v1)<<4)|(uint8(v2)&0xf),
4521 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4523 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4527 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
4530 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
4531 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4533 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
4537 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
4540 (uint8(v1)<<4)|(uint8(v2)&0xf),
4542 (uint8(m5)<<4)|(uint8(m4)&0xf),
4543 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4547 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
4550 (uint8(v1)<<4)|(uint8(v2)&0xf),
4553 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4557 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
4560 (uint8(v1)<<4)|(uint8(v2)&0xf),
4562 (uint8(m6)<<4)|(uint8(m5)&0xf),
4563 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4567 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
4570 (uint8(v1)<<4)|(uint8(v2)&0xf),
4571 (uint8(v3)<<4)|(uint8(m5)&0xf),
4573 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4577 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
4580 (uint8(v1)<<4)|(uint8(v2)&0xf),
4581 (uint8(v3)<<4)|(uint8(m6)&0xf),
4583 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4587 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
4590 (uint8(v1)<<4)|(uint8(r2)&0xf),
4597 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
4603 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4607 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
4613 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
4617 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
4620 (uint8(v1)<<4)|(uint8(v3)&0xf),
4623 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
4627 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
4630 (uint8(v1)<<4)|(uint8(v2)&0xf),
4633 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
4637 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
4640 (uint8(v1)<<4)|(uint8(v2)&0xf),
4642 (uint8(i3)<<4)|(uint8(m5)&0xf),
4643 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),