1 // cmd/9c/9.out.h from Vita Nuova.
3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
5 // Portions Copyright © 1997-1999 Vita Nuova Limited
6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
7 // Portions Copyright © 2004,2006 Bruce Ellis
8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
10 // Portions Copyright © 2009 The Go Authors. All rights reserved.
12 // Permission is hereby granted, free of charge, to any person obtaining a copy
13 // of this software and associated documentation files (the "Software"), to deal
14 // in the Software without restriction, including without limitation the rights
15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 // copies of the Software, and to permit persons to whom the Software is
17 // furnished to do so, subject to the following conditions:
19 // The above copyright notice and this permission notice shall be included in
20 // all copies or substantial portions of the Software.
22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 import "cmd/internal/obj"
34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
42 NREG = 32 /* number of general registers */
43 NFREG = 32 /* number of floating point registers */
47 REG_R0 = obj.RBasePPC64 + iota
126 REG_SPECIAL = REG_CR0
128 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
129 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers
131 REG_XER = REG_SPR0 + 1
132 REG_LR = REG_SPR0 + 8
133 REG_CTR = REG_SPR0 + 9
135 REGZERO = REG_R0 /* set to zero */
139 REGARG = -1 /* -1 disables passing the first argument in register */
140 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */
141 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */
142 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */
143 REGCTXT = REG_R11 /* context for closures */
144 REGTLS = REG_R13 /* C ABI TLS base pointer */
146 REGEXT = REG_R30 /* external registers allocated from here down */
147 REGG = REG_R30 /* G */
148 REGTMP = REG_R31 /* used by the linker */
150 FREGMIN = REG_F17 /* first register variable */
151 FREGMAX = REG_F26 /* last register variable for 9g only */
152 FREGEXT = REG_F26 /* first external register */
153 FREGCVI = REG_F27 /* floating conversion constant */
154 FREGZERO = REG_F28 /* both float and double */
155 FREGHALF = REG_F29 /* double */
156 FREGONE = REG_F30 /* double */
157 FREGTWO = REG_F31 /* double */
163 * compiler allocates R3 up as temps
164 * compiler allocates register variables R7-R27
165 * compiler allocates external registers R30 down
167 * compiler allocates register variables F17-F26
168 * compiler allocates external registers F26 down
193 C_SPR /* special processor register */
195 C_SCON /* 16 bit signed */
196 C_UCON /* 32 bit signed, low 16 bits 0 */
197 C_ADDCON /* -0x8000 <= v < 0 */
198 C_ANDCON /* 0 < v <= 0xFFFF */
199 C_LCON /* other 32 */
200 C_DCON /* other 64 (could subdivide further) */
201 C_SACON /* $n(REG) where n <= int16 */
203 C_LACON /* $n(REG) where int16 < n <= int32 */
205 C_DACON /* $n(REG) where int32 < n */
229 C_NCLASS /* must be the last */
233 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
452 /* optional on 32-bit */
468 ACMPW /* CMP with L=0 */
480 /* AFCFIW; AFCFIWCC */
523 /* 64-bit pseudo operation */
534 /* more 64-bit operations */