1 // cmd/9c/9.out.h from Vita Nuova.
3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
5 // Portions Copyright © 1997-1999 Vita Nuova Limited
6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
7 // Portions Copyright © 2004,2006 Bruce Ellis
8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
10 // Portions Copyright © 2009 The Go Authors. All rights reserved.
12 // Permission is hereby granted, free of charge, to any person obtaining a copy
13 // of this software and associated documentation files (the "Software"), to deal
14 // in the Software without restriction, including without limitation the rights
15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 // copies of the Software, and to permit persons to whom the Software is
17 // furnished to do so, subject to the following conditions:
19 // The above copyright notice and this permission notice shall be included in
20 // all copies or substantial portions of the Software.
22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 import "cmd/internal/obj"
34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
42 NREG = 32 /* number of general registers */
43 NFREG = 32 /* number of floating point registers */
47 REG_R0 = obj.RBaseMIPS64 + iota
116 // co-processor 0 control registers
150 // FPU control registers
184 REG_LAST = REG_FCR31 // the last defined register
188 REGZERO = REG_R0 /* set to zero */
193 REGARG = -1 /* -1 disables passing the first argument in register */
194 REGRT1 = REG_R1 /* reserved for runtime, duffzero and duffcopy */
195 REGRT2 = REG_R2 /* reserved for runtime, duffcopy */
196 REGCTXT = REG_R22 /* context for closures */
197 REGG = REG_R30 /* G */
198 REGTMP = REG_R23 /* used by the linker */
200 FREGZERO = REG_F24 /* both float and double */
201 FREGHALF = REG_F26 /* double */
202 FREGONE = REG_F28 /* double */
203 FREGTWO = REG_F30 /* double */
229 C_MREG /* special processor register */
233 C_SCON /* 16 bit signed */
234 C_UCON /* 32 bit signed, low 16 bits 0 */
237 C_ADDCON /* -0x8000 <= v < 0 */
238 C_ANDCON /* 0 < v <= 0xFFFF */
239 C_LCON /* other 32 */
240 C_DCON /* other 64 (could subdivide further) */
241 C_SACON /* $n(REG) where n <= int16 */
243 C_LACON /* $n(REG) where int16 < n <= int32 */
245 C_DACON /* $n(REG) where int32 < n */
246 C_STCON /* $tlsvar */
261 C_NCLASS /* must be the last */
265 AABSD = obj.ABaseMIPS64 + obj.A_ARCHSPECIFIC + iota