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[dev.ssa] Merge branch 'master' into dev.ssa
[gostls13.git] / src / cmd / compile / internal / ssa / opGen.go
1 // autogenerated: do not edit!
2 // generated from gen/*Ops.go
3
4 package ssa
5
6 import (
7         "cmd/internal/obj"
8         "cmd/internal/obj/arm"
9         "cmd/internal/obj/x86"
10 )
11
12 const (
13         BlockInvalid BlockKind = iota
14
15         BlockAMD64EQ
16         BlockAMD64NE
17         BlockAMD64LT
18         BlockAMD64LE
19         BlockAMD64GT
20         BlockAMD64GE
21         BlockAMD64ULT
22         BlockAMD64ULE
23         BlockAMD64UGT
24         BlockAMD64UGE
25         BlockAMD64EQF
26         BlockAMD64NEF
27         BlockAMD64ORD
28         BlockAMD64NAN
29
30         BlockARMEQ
31         BlockARMNE
32         BlockARMLT
33         BlockARMLE
34         BlockARMGT
35         BlockARMGE
36         BlockARMULT
37         BlockARMULE
38         BlockARMUGT
39         BlockARMUGE
40
41         BlockPlain
42         BlockIf
43         BlockCall
44         BlockDefer
45         BlockCheck
46         BlockRet
47         BlockRetJmp
48         BlockExit
49         BlockFirst
50 )
51
52 var blockString = [...]string{
53         BlockInvalid: "BlockInvalid",
54
55         BlockAMD64EQ:  "EQ",
56         BlockAMD64NE:  "NE",
57         BlockAMD64LT:  "LT",
58         BlockAMD64LE:  "LE",
59         BlockAMD64GT:  "GT",
60         BlockAMD64GE:  "GE",
61         BlockAMD64ULT: "ULT",
62         BlockAMD64ULE: "ULE",
63         BlockAMD64UGT: "UGT",
64         BlockAMD64UGE: "UGE",
65         BlockAMD64EQF: "EQF",
66         BlockAMD64NEF: "NEF",
67         BlockAMD64ORD: "ORD",
68         BlockAMD64NAN: "NAN",
69
70         BlockARMEQ:  "EQ",
71         BlockARMNE:  "NE",
72         BlockARMLT:  "LT",
73         BlockARMLE:  "LE",
74         BlockARMGT:  "GT",
75         BlockARMGE:  "GE",
76         BlockARMULT: "ULT",
77         BlockARMULE: "ULE",
78         BlockARMUGT: "UGT",
79         BlockARMUGE: "UGE",
80
81         BlockPlain:  "Plain",
82         BlockIf:     "If",
83         BlockCall:   "Call",
84         BlockDefer:  "Defer",
85         BlockCheck:  "Check",
86         BlockRet:    "Ret",
87         BlockRetJmp: "RetJmp",
88         BlockExit:   "Exit",
89         BlockFirst:  "First",
90 }
91
92 func (k BlockKind) String() string { return blockString[k] }
93
94 const (
95         OpInvalid Op = iota
96
97         OpAMD64ADDSS
98         OpAMD64ADDSD
99         OpAMD64SUBSS
100         OpAMD64SUBSD
101         OpAMD64MULSS
102         OpAMD64MULSD
103         OpAMD64DIVSS
104         OpAMD64DIVSD
105         OpAMD64MOVSSload
106         OpAMD64MOVSDload
107         OpAMD64MOVSSconst
108         OpAMD64MOVSDconst
109         OpAMD64MOVSSloadidx1
110         OpAMD64MOVSSloadidx4
111         OpAMD64MOVSDloadidx1
112         OpAMD64MOVSDloadidx8
113         OpAMD64MOVSSstore
114         OpAMD64MOVSDstore
115         OpAMD64MOVSSstoreidx1
116         OpAMD64MOVSSstoreidx4
117         OpAMD64MOVSDstoreidx1
118         OpAMD64MOVSDstoreidx8
119         OpAMD64ADDQ
120         OpAMD64ADDL
121         OpAMD64ADDQconst
122         OpAMD64ADDLconst
123         OpAMD64SUBQ
124         OpAMD64SUBL
125         OpAMD64SUBQconst
126         OpAMD64SUBLconst
127         OpAMD64MULQ
128         OpAMD64MULL
129         OpAMD64MULQconst
130         OpAMD64MULLconst
131         OpAMD64HMULQ
132         OpAMD64HMULL
133         OpAMD64HMULW
134         OpAMD64HMULB
135         OpAMD64HMULQU
136         OpAMD64HMULLU
137         OpAMD64HMULWU
138         OpAMD64HMULBU
139         OpAMD64AVGQU
140         OpAMD64DIVQ
141         OpAMD64DIVL
142         OpAMD64DIVW
143         OpAMD64DIVQU
144         OpAMD64DIVLU
145         OpAMD64DIVWU
146         OpAMD64MODQ
147         OpAMD64MODL
148         OpAMD64MODW
149         OpAMD64MODQU
150         OpAMD64MODLU
151         OpAMD64MODWU
152         OpAMD64ANDQ
153         OpAMD64ANDL
154         OpAMD64ANDQconst
155         OpAMD64ANDLconst
156         OpAMD64ORQ
157         OpAMD64ORL
158         OpAMD64ORQconst
159         OpAMD64ORLconst
160         OpAMD64XORQ
161         OpAMD64XORL
162         OpAMD64XORQconst
163         OpAMD64XORLconst
164         OpAMD64CMPQ
165         OpAMD64CMPL
166         OpAMD64CMPW
167         OpAMD64CMPB
168         OpAMD64CMPQconst
169         OpAMD64CMPLconst
170         OpAMD64CMPWconst
171         OpAMD64CMPBconst
172         OpAMD64UCOMISS
173         OpAMD64UCOMISD
174         OpAMD64TESTQ
175         OpAMD64TESTL
176         OpAMD64TESTW
177         OpAMD64TESTB
178         OpAMD64TESTQconst
179         OpAMD64TESTLconst
180         OpAMD64TESTWconst
181         OpAMD64TESTBconst
182         OpAMD64SHLQ
183         OpAMD64SHLL
184         OpAMD64SHLQconst
185         OpAMD64SHLLconst
186         OpAMD64SHRQ
187         OpAMD64SHRL
188         OpAMD64SHRW
189         OpAMD64SHRB
190         OpAMD64SHRQconst
191         OpAMD64SHRLconst
192         OpAMD64SHRWconst
193         OpAMD64SHRBconst
194         OpAMD64SARQ
195         OpAMD64SARL
196         OpAMD64SARW
197         OpAMD64SARB
198         OpAMD64SARQconst
199         OpAMD64SARLconst
200         OpAMD64SARWconst
201         OpAMD64SARBconst
202         OpAMD64ROLQconst
203         OpAMD64ROLLconst
204         OpAMD64ROLWconst
205         OpAMD64ROLBconst
206         OpAMD64NEGQ
207         OpAMD64NEGL
208         OpAMD64NOTQ
209         OpAMD64NOTL
210         OpAMD64BSFQ
211         OpAMD64BSFL
212         OpAMD64BSFW
213         OpAMD64BSRQ
214         OpAMD64BSRL
215         OpAMD64BSRW
216         OpAMD64CMOVQEQconst
217         OpAMD64CMOVLEQconst
218         OpAMD64CMOVWEQconst
219         OpAMD64CMOVQNEconst
220         OpAMD64CMOVLNEconst
221         OpAMD64CMOVWNEconst
222         OpAMD64BSWAPQ
223         OpAMD64BSWAPL
224         OpAMD64SQRTSD
225         OpAMD64SBBQcarrymask
226         OpAMD64SBBLcarrymask
227         OpAMD64SETEQ
228         OpAMD64SETNE
229         OpAMD64SETL
230         OpAMD64SETLE
231         OpAMD64SETG
232         OpAMD64SETGE
233         OpAMD64SETB
234         OpAMD64SETBE
235         OpAMD64SETA
236         OpAMD64SETAE
237         OpAMD64SETEQF
238         OpAMD64SETNEF
239         OpAMD64SETORD
240         OpAMD64SETNAN
241         OpAMD64SETGF
242         OpAMD64SETGEF
243         OpAMD64MOVBQSX
244         OpAMD64MOVBQZX
245         OpAMD64MOVWQSX
246         OpAMD64MOVWQZX
247         OpAMD64MOVLQSX
248         OpAMD64MOVLQZX
249         OpAMD64MOVLconst
250         OpAMD64MOVQconst
251         OpAMD64CVTTSD2SL
252         OpAMD64CVTTSD2SQ
253         OpAMD64CVTTSS2SL
254         OpAMD64CVTTSS2SQ
255         OpAMD64CVTSL2SS
256         OpAMD64CVTSL2SD
257         OpAMD64CVTSQ2SS
258         OpAMD64CVTSQ2SD
259         OpAMD64CVTSD2SS
260         OpAMD64CVTSS2SD
261         OpAMD64PXOR
262         OpAMD64LEAQ
263         OpAMD64LEAQ1
264         OpAMD64LEAQ2
265         OpAMD64LEAQ4
266         OpAMD64LEAQ8
267         OpAMD64MOVBload
268         OpAMD64MOVBQSXload
269         OpAMD64MOVWload
270         OpAMD64MOVWQSXload
271         OpAMD64MOVLload
272         OpAMD64MOVLQSXload
273         OpAMD64MOVQload
274         OpAMD64MOVBstore
275         OpAMD64MOVWstore
276         OpAMD64MOVLstore
277         OpAMD64MOVQstore
278         OpAMD64MOVOload
279         OpAMD64MOVOstore
280         OpAMD64MOVBloadidx1
281         OpAMD64MOVWloadidx1
282         OpAMD64MOVWloadidx2
283         OpAMD64MOVLloadidx1
284         OpAMD64MOVLloadidx4
285         OpAMD64MOVQloadidx1
286         OpAMD64MOVQloadidx8
287         OpAMD64MOVBstoreidx1
288         OpAMD64MOVWstoreidx1
289         OpAMD64MOVWstoreidx2
290         OpAMD64MOVLstoreidx1
291         OpAMD64MOVLstoreidx4
292         OpAMD64MOVQstoreidx1
293         OpAMD64MOVQstoreidx8
294         OpAMD64MOVBstoreconst
295         OpAMD64MOVWstoreconst
296         OpAMD64MOVLstoreconst
297         OpAMD64MOVQstoreconst
298         OpAMD64MOVBstoreconstidx1
299         OpAMD64MOVWstoreconstidx1
300         OpAMD64MOVWstoreconstidx2
301         OpAMD64MOVLstoreconstidx1
302         OpAMD64MOVLstoreconstidx4
303         OpAMD64MOVQstoreconstidx1
304         OpAMD64MOVQstoreconstidx8
305         OpAMD64DUFFZERO
306         OpAMD64MOVOconst
307         OpAMD64REPSTOSQ
308         OpAMD64CALLstatic
309         OpAMD64CALLclosure
310         OpAMD64CALLdefer
311         OpAMD64CALLgo
312         OpAMD64CALLinter
313         OpAMD64DUFFCOPY
314         OpAMD64REPMOVSQ
315         OpAMD64InvertFlags
316         OpAMD64LoweredGetG
317         OpAMD64LoweredGetClosurePtr
318         OpAMD64LoweredNilCheck
319         OpAMD64MOVQconvert
320         OpAMD64FlagEQ
321         OpAMD64FlagLT_ULT
322         OpAMD64FlagLT_UGT
323         OpAMD64FlagGT_UGT
324         OpAMD64FlagGT_ULT
325
326         OpARMADD
327         OpARMADDconst
328         OpARMSUB
329         OpARMSUBconst
330         OpARMRSB
331         OpARMRSBconst
332         OpARMMUL
333         OpARMHMUL
334         OpARMHMULU
335         OpARMAND
336         OpARMANDconst
337         OpARMOR
338         OpARMORconst
339         OpARMXOR
340         OpARMXORconst
341         OpARMBIC
342         OpARMBICconst
343         OpARMMVN
344         OpARMSLL
345         OpARMSLLconst
346         OpARMSRL
347         OpARMSRLconst
348         OpARMSRA
349         OpARMSRAconst
350         OpARMCMP
351         OpARMCMPconst
352         OpARMCMN
353         OpARMCMNconst
354         OpARMTST
355         OpARMTSTconst
356         OpARMTEQ
357         OpARMTEQconst
358         OpARMMOVWconst
359         OpARMMOVBload
360         OpARMMOVBUload
361         OpARMMOVHload
362         OpARMMOVHUload
363         OpARMMOVWload
364         OpARMMOVBstore
365         OpARMMOVHstore
366         OpARMMOVWstore
367         OpARMMOVBreg
368         OpARMMOVBUreg
369         OpARMMOVHreg
370         OpARMMOVHUreg
371         OpARMCALLstatic
372         OpARMCALLclosure
373         OpARMCALLdefer
374         OpARMCALLgo
375         OpARMCALLinter
376         OpARMLoweredNilCheck
377         OpARMEqual
378         OpARMNotEqual
379         OpARMLessThan
380         OpARMLessEqual
381         OpARMGreaterThan
382         OpARMGreaterEqual
383         OpARMLessThanU
384         OpARMLessEqualU
385         OpARMGreaterThanU
386         OpARMGreaterEqualU
387         OpARMDUFFZERO
388         OpARMDUFFCOPY
389         OpARMLoweredZero
390         OpARMLoweredMove
391
392         OpAdd8
393         OpAdd16
394         OpAdd32
395         OpAdd64
396         OpAddPtr
397         OpAdd32F
398         OpAdd64F
399         OpSub8
400         OpSub16
401         OpSub32
402         OpSub64
403         OpSubPtr
404         OpSub32F
405         OpSub64F
406         OpMul8
407         OpMul16
408         OpMul32
409         OpMul64
410         OpMul32F
411         OpMul64F
412         OpDiv32F
413         OpDiv64F
414         OpHmul8
415         OpHmul8u
416         OpHmul16
417         OpHmul16u
418         OpHmul32
419         OpHmul32u
420         OpHmul64
421         OpHmul64u
422         OpAvg64u
423         OpDiv8
424         OpDiv8u
425         OpDiv16
426         OpDiv16u
427         OpDiv32
428         OpDiv32u
429         OpDiv64
430         OpDiv64u
431         OpMod8
432         OpMod8u
433         OpMod16
434         OpMod16u
435         OpMod32
436         OpMod32u
437         OpMod64
438         OpMod64u
439         OpAnd8
440         OpAnd16
441         OpAnd32
442         OpAnd64
443         OpOr8
444         OpOr16
445         OpOr32
446         OpOr64
447         OpXor8
448         OpXor16
449         OpXor32
450         OpXor64
451         OpLsh8x8
452         OpLsh8x16
453         OpLsh8x32
454         OpLsh8x64
455         OpLsh16x8
456         OpLsh16x16
457         OpLsh16x32
458         OpLsh16x64
459         OpLsh32x8
460         OpLsh32x16
461         OpLsh32x32
462         OpLsh32x64
463         OpLsh64x8
464         OpLsh64x16
465         OpLsh64x32
466         OpLsh64x64
467         OpRsh8x8
468         OpRsh8x16
469         OpRsh8x32
470         OpRsh8x64
471         OpRsh16x8
472         OpRsh16x16
473         OpRsh16x32
474         OpRsh16x64
475         OpRsh32x8
476         OpRsh32x16
477         OpRsh32x32
478         OpRsh32x64
479         OpRsh64x8
480         OpRsh64x16
481         OpRsh64x32
482         OpRsh64x64
483         OpRsh8Ux8
484         OpRsh8Ux16
485         OpRsh8Ux32
486         OpRsh8Ux64
487         OpRsh16Ux8
488         OpRsh16Ux16
489         OpRsh16Ux32
490         OpRsh16Ux64
491         OpRsh32Ux8
492         OpRsh32Ux16
493         OpRsh32Ux32
494         OpRsh32Ux64
495         OpRsh64Ux8
496         OpRsh64Ux16
497         OpRsh64Ux32
498         OpRsh64Ux64
499         OpLrot8
500         OpLrot16
501         OpLrot32
502         OpLrot64
503         OpEq8
504         OpEq16
505         OpEq32
506         OpEq64
507         OpEqPtr
508         OpEqInter
509         OpEqSlice
510         OpEq32F
511         OpEq64F
512         OpNeq8
513         OpNeq16
514         OpNeq32
515         OpNeq64
516         OpNeqPtr
517         OpNeqInter
518         OpNeqSlice
519         OpNeq32F
520         OpNeq64F
521         OpLess8
522         OpLess8U
523         OpLess16
524         OpLess16U
525         OpLess32
526         OpLess32U
527         OpLess64
528         OpLess64U
529         OpLess32F
530         OpLess64F
531         OpLeq8
532         OpLeq8U
533         OpLeq16
534         OpLeq16U
535         OpLeq32
536         OpLeq32U
537         OpLeq64
538         OpLeq64U
539         OpLeq32F
540         OpLeq64F
541         OpGreater8
542         OpGreater8U
543         OpGreater16
544         OpGreater16U
545         OpGreater32
546         OpGreater32U
547         OpGreater64
548         OpGreater64U
549         OpGreater32F
550         OpGreater64F
551         OpGeq8
552         OpGeq8U
553         OpGeq16
554         OpGeq16U
555         OpGeq32
556         OpGeq32U
557         OpGeq64
558         OpGeq64U
559         OpGeq32F
560         OpGeq64F
561         OpAndB
562         OpOrB
563         OpEqB
564         OpNeqB
565         OpNot
566         OpNeg8
567         OpNeg16
568         OpNeg32
569         OpNeg64
570         OpNeg32F
571         OpNeg64F
572         OpCom8
573         OpCom16
574         OpCom32
575         OpCom64
576         OpCtz16
577         OpCtz32
578         OpCtz64
579         OpClz16
580         OpClz32
581         OpClz64
582         OpBswap32
583         OpBswap64
584         OpSqrt
585         OpPhi
586         OpCopy
587         OpConvert
588         OpConstBool
589         OpConstString
590         OpConstNil
591         OpConst8
592         OpConst16
593         OpConst32
594         OpConst64
595         OpConst32F
596         OpConst64F
597         OpConstInterface
598         OpConstSlice
599         OpInitMem
600         OpArg
601         OpAddr
602         OpSP
603         OpSB
604         OpFunc
605         OpLoad
606         OpStore
607         OpMove
608         OpZero
609         OpClosureCall
610         OpStaticCall
611         OpDeferCall
612         OpGoCall
613         OpInterCall
614         OpSignExt8to16
615         OpSignExt8to32
616         OpSignExt8to64
617         OpSignExt16to32
618         OpSignExt16to64
619         OpSignExt32to64
620         OpZeroExt8to16
621         OpZeroExt8to32
622         OpZeroExt8to64
623         OpZeroExt16to32
624         OpZeroExt16to64
625         OpZeroExt32to64
626         OpTrunc16to8
627         OpTrunc32to8
628         OpTrunc32to16
629         OpTrunc64to8
630         OpTrunc64to16
631         OpTrunc64to32
632         OpCvt32to32F
633         OpCvt32to64F
634         OpCvt64to32F
635         OpCvt64to64F
636         OpCvt32Fto32
637         OpCvt32Fto64
638         OpCvt64Fto32
639         OpCvt64Fto64
640         OpCvt32Fto64F
641         OpCvt64Fto32F
642         OpIsNonNil
643         OpIsInBounds
644         OpIsSliceInBounds
645         OpNilCheck
646         OpGetG
647         OpGetClosurePtr
648         OpArrayIndex
649         OpPtrIndex
650         OpOffPtr
651         OpSliceMake
652         OpSlicePtr
653         OpSliceLen
654         OpSliceCap
655         OpComplexMake
656         OpComplexReal
657         OpComplexImag
658         OpStringMake
659         OpStringPtr
660         OpStringLen
661         OpIMake
662         OpITab
663         OpIData
664         OpStructMake0
665         OpStructMake1
666         OpStructMake2
667         OpStructMake3
668         OpStructMake4
669         OpStructSelect
670         OpStoreReg
671         OpLoadReg
672         OpFwdRef
673         OpUnknown
674         OpVarDef
675         OpVarKill
676         OpVarLive
677         OpKeepAlive
678 )
679
680 var opcodeTable = [...]opInfo{
681         {name: "OpInvalid"},
682
683         {
684                 name:         "ADDSS",
685                 argLen:       2,
686                 commutative:  true,
687                 resultInArg0: true,
688                 asm:          x86.AADDSS,
689                 reg: regInfo{
690                         inputs: []inputInfo{
691                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
692                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
693                         },
694                         outputs: []regMask{
695                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
696                         },
697                 },
698         },
699         {
700                 name:         "ADDSD",
701                 argLen:       2,
702                 commutative:  true,
703                 resultInArg0: true,
704                 asm:          x86.AADDSD,
705                 reg: regInfo{
706                         inputs: []inputInfo{
707                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
708                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
709                         },
710                         outputs: []regMask{
711                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
712                         },
713                 },
714         },
715         {
716                 name:         "SUBSS",
717                 argLen:       2,
718                 resultInArg0: true,
719                 asm:          x86.ASUBSS,
720                 reg: regInfo{
721                         inputs: []inputInfo{
722                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
723                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
724                         },
725                         clobbers: 2147483648, // X15
726                         outputs: []regMask{
727                                 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
728                         },
729                 },
730         },
731         {
732                 name:         "SUBSD",
733                 argLen:       2,
734                 resultInArg0: true,
735                 asm:          x86.ASUBSD,
736                 reg: regInfo{
737                         inputs: []inputInfo{
738                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
739                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
740                         },
741                         clobbers: 2147483648, // X15
742                         outputs: []regMask{
743                                 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
744                         },
745                 },
746         },
747         {
748                 name:         "MULSS",
749                 argLen:       2,
750                 commutative:  true,
751                 resultInArg0: true,
752                 asm:          x86.AMULSS,
753                 reg: regInfo{
754                         inputs: []inputInfo{
755                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
756                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
757                         },
758                         outputs: []regMask{
759                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
760                         },
761                 },
762         },
763         {
764                 name:         "MULSD",
765                 argLen:       2,
766                 commutative:  true,
767                 resultInArg0: true,
768                 asm:          x86.AMULSD,
769                 reg: regInfo{
770                         inputs: []inputInfo{
771                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
772                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
773                         },
774                         outputs: []regMask{
775                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
776                         },
777                 },
778         },
779         {
780                 name:         "DIVSS",
781                 argLen:       2,
782                 resultInArg0: true,
783                 asm:          x86.ADIVSS,
784                 reg: regInfo{
785                         inputs: []inputInfo{
786                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
787                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
788                         },
789                         clobbers: 2147483648, // X15
790                         outputs: []regMask{
791                                 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
792                         },
793                 },
794         },
795         {
796                 name:         "DIVSD",
797                 argLen:       2,
798                 resultInArg0: true,
799                 asm:          x86.ADIVSD,
800                 reg: regInfo{
801                         inputs: []inputInfo{
802                                 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
803                                 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
804                         },
805                         clobbers: 2147483648, // X15
806                         outputs: []regMask{
807                                 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
808                         },
809                 },
810         },
811         {
812                 name:    "MOVSSload",
813                 auxType: auxSymOff,
814                 argLen:  2,
815                 asm:     x86.AMOVSS,
816                 reg: regInfo{
817                         inputs: []inputInfo{
818                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
819                         },
820                         outputs: []regMask{
821                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
822                         },
823                 },
824         },
825         {
826                 name:    "MOVSDload",
827                 auxType: auxSymOff,
828                 argLen:  2,
829                 asm:     x86.AMOVSD,
830                 reg: regInfo{
831                         inputs: []inputInfo{
832                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
833                         },
834                         outputs: []regMask{
835                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
836                         },
837                 },
838         },
839         {
840                 name:              "MOVSSconst",
841                 auxType:           auxFloat32,
842                 argLen:            0,
843                 rematerializeable: true,
844                 asm:               x86.AMOVSS,
845                 reg: regInfo{
846                         outputs: []regMask{
847                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
848                         },
849                 },
850         },
851         {
852                 name:              "MOVSDconst",
853                 auxType:           auxFloat64,
854                 argLen:            0,
855                 rematerializeable: true,
856                 asm:               x86.AMOVSD,
857                 reg: regInfo{
858                         outputs: []regMask{
859                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
860                         },
861                 },
862         },
863         {
864                 name:    "MOVSSloadidx1",
865                 auxType: auxSymOff,
866                 argLen:  3,
867                 asm:     x86.AMOVSS,
868                 reg: regInfo{
869                         inputs: []inputInfo{
870                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
871                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
872                         },
873                         outputs: []regMask{
874                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
875                         },
876                 },
877         },
878         {
879                 name:    "MOVSSloadidx4",
880                 auxType: auxSymOff,
881                 argLen:  3,
882                 asm:     x86.AMOVSS,
883                 reg: regInfo{
884                         inputs: []inputInfo{
885                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
886                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
887                         },
888                         outputs: []regMask{
889                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
890                         },
891                 },
892         },
893         {
894                 name:    "MOVSDloadidx1",
895                 auxType: auxSymOff,
896                 argLen:  3,
897                 asm:     x86.AMOVSD,
898                 reg: regInfo{
899                         inputs: []inputInfo{
900                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
901                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
902                         },
903                         outputs: []regMask{
904                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
905                         },
906                 },
907         },
908         {
909                 name:    "MOVSDloadidx8",
910                 auxType: auxSymOff,
911                 argLen:  3,
912                 asm:     x86.AMOVSD,
913                 reg: regInfo{
914                         inputs: []inputInfo{
915                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
916                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
917                         },
918                         outputs: []regMask{
919                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
920                         },
921                 },
922         },
923         {
924                 name:    "MOVSSstore",
925                 auxType: auxSymOff,
926                 argLen:  3,
927                 asm:     x86.AMOVSS,
928                 reg: regInfo{
929                         inputs: []inputInfo{
930                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
931                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
932                         },
933                 },
934         },
935         {
936                 name:    "MOVSDstore",
937                 auxType: auxSymOff,
938                 argLen:  3,
939                 asm:     x86.AMOVSD,
940                 reg: regInfo{
941                         inputs: []inputInfo{
942                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
943                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
944                         },
945                 },
946         },
947         {
948                 name:    "MOVSSstoreidx1",
949                 auxType: auxSymOff,
950                 argLen:  4,
951                 asm:     x86.AMOVSS,
952                 reg: regInfo{
953                         inputs: []inputInfo{
954                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
955                                 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
956                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
957                         },
958                 },
959         },
960         {
961                 name:    "MOVSSstoreidx4",
962                 auxType: auxSymOff,
963                 argLen:  4,
964                 asm:     x86.AMOVSS,
965                 reg: regInfo{
966                         inputs: []inputInfo{
967                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
968                                 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
969                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
970                         },
971                 },
972         },
973         {
974                 name:    "MOVSDstoreidx1",
975                 auxType: auxSymOff,
976                 argLen:  4,
977                 asm:     x86.AMOVSD,
978                 reg: regInfo{
979                         inputs: []inputInfo{
980                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
981                                 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
982                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
983                         },
984                 },
985         },
986         {
987                 name:    "MOVSDstoreidx8",
988                 auxType: auxSymOff,
989                 argLen:  4,
990                 asm:     x86.AMOVSD,
991                 reg: regInfo{
992                         inputs: []inputInfo{
993                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
994                                 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
995                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
996                         },
997                 },
998         },
999         {
1000                 name:        "ADDQ",
1001                 argLen:      2,
1002                 commutative: true,
1003                 asm:         x86.AADDQ,
1004                 reg: regInfo{
1005                         inputs: []inputInfo{
1006                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1007                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1008                         },
1009                         clobbers: 8589934592, // FLAGS
1010                         outputs: []regMask{
1011                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1012                         },
1013                 },
1014         },
1015         {
1016                 name:        "ADDL",
1017                 argLen:      2,
1018                 commutative: true,
1019                 asm:         x86.AADDL,
1020                 reg: regInfo{
1021                         inputs: []inputInfo{
1022                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1023                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1024                         },
1025                         clobbers: 8589934592, // FLAGS
1026                         outputs: []regMask{
1027                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1028                         },
1029                 },
1030         },
1031         {
1032                 name:    "ADDQconst",
1033                 auxType: auxInt64,
1034                 argLen:  1,
1035                 asm:     x86.AADDQ,
1036                 reg: regInfo{
1037                         inputs: []inputInfo{
1038                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1039                         },
1040                         clobbers: 8589934592, // FLAGS
1041                         outputs: []regMask{
1042                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1043                         },
1044                 },
1045         },
1046         {
1047                 name:    "ADDLconst",
1048                 auxType: auxInt32,
1049                 argLen:  1,
1050                 asm:     x86.AADDL,
1051                 reg: regInfo{
1052                         inputs: []inputInfo{
1053                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1054                         },
1055                         clobbers: 8589934592, // FLAGS
1056                         outputs: []regMask{
1057                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1058                         },
1059                 },
1060         },
1061         {
1062                 name:         "SUBQ",
1063                 argLen:       2,
1064                 resultInArg0: true,
1065                 asm:          x86.ASUBQ,
1066                 reg: regInfo{
1067                         inputs: []inputInfo{
1068                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1069                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1070                         },
1071                         clobbers: 8589934592, // FLAGS
1072                         outputs: []regMask{
1073                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1074                         },
1075                 },
1076         },
1077         {
1078                 name:         "SUBL",
1079                 argLen:       2,
1080                 resultInArg0: true,
1081                 asm:          x86.ASUBL,
1082                 reg: regInfo{
1083                         inputs: []inputInfo{
1084                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1085                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1086                         },
1087                         clobbers: 8589934592, // FLAGS
1088                         outputs: []regMask{
1089                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1090                         },
1091                 },
1092         },
1093         {
1094                 name:         "SUBQconst",
1095                 auxType:      auxInt64,
1096                 argLen:       1,
1097                 resultInArg0: true,
1098                 asm:          x86.ASUBQ,
1099                 reg: regInfo{
1100                         inputs: []inputInfo{
1101                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1102                         },
1103                         clobbers: 8589934592, // FLAGS
1104                         outputs: []regMask{
1105                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1106                         },
1107                 },
1108         },
1109         {
1110                 name:         "SUBLconst",
1111                 auxType:      auxInt32,
1112                 argLen:       1,
1113                 resultInArg0: true,
1114                 asm:          x86.ASUBL,
1115                 reg: regInfo{
1116                         inputs: []inputInfo{
1117                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1118                         },
1119                         clobbers: 8589934592, // FLAGS
1120                         outputs: []regMask{
1121                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1122                         },
1123                 },
1124         },
1125         {
1126                 name:         "MULQ",
1127                 argLen:       2,
1128                 commutative:  true,
1129                 resultInArg0: true,
1130                 asm:          x86.AIMULQ,
1131                 reg: regInfo{
1132                         inputs: []inputInfo{
1133                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1134                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1135                         },
1136                         clobbers: 8589934592, // FLAGS
1137                         outputs: []regMask{
1138                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1139                         },
1140                 },
1141         },
1142         {
1143                 name:         "MULL",
1144                 argLen:       2,
1145                 commutative:  true,
1146                 resultInArg0: true,
1147                 asm:          x86.AIMULL,
1148                 reg: regInfo{
1149                         inputs: []inputInfo{
1150                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1151                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1152                         },
1153                         clobbers: 8589934592, // FLAGS
1154                         outputs: []regMask{
1155                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1156                         },
1157                 },
1158         },
1159         {
1160                 name:         "MULQconst",
1161                 auxType:      auxInt64,
1162                 argLen:       1,
1163                 resultInArg0: true,
1164                 asm:          x86.AIMULQ,
1165                 reg: regInfo{
1166                         inputs: []inputInfo{
1167                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1168                         },
1169                         clobbers: 8589934592, // FLAGS
1170                         outputs: []regMask{
1171                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1172                         },
1173                 },
1174         },
1175         {
1176                 name:         "MULLconst",
1177                 auxType:      auxInt32,
1178                 argLen:       1,
1179                 resultInArg0: true,
1180                 asm:          x86.AIMULL,
1181                 reg: regInfo{
1182                         inputs: []inputInfo{
1183                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1184                         },
1185                         clobbers: 8589934592, // FLAGS
1186                         outputs: []regMask{
1187                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1188                         },
1189                 },
1190         },
1191         {
1192                 name:   "HMULQ",
1193                 argLen: 2,
1194                 asm:    x86.AIMULQ,
1195                 reg: regInfo{
1196                         inputs: []inputInfo{
1197                                 {0, 1},     // AX
1198                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1199                         },
1200                         clobbers: 8589934593, // AX FLAGS
1201                         outputs: []regMask{
1202                                 4, // DX
1203                         },
1204                 },
1205         },
1206         {
1207                 name:   "HMULL",
1208                 argLen: 2,
1209                 asm:    x86.AIMULL,
1210                 reg: regInfo{
1211                         inputs: []inputInfo{
1212                                 {0, 1},     // AX
1213                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1214                         },
1215                         clobbers: 8589934593, // AX FLAGS
1216                         outputs: []regMask{
1217                                 4, // DX
1218                         },
1219                 },
1220         },
1221         {
1222                 name:   "HMULW",
1223                 argLen: 2,
1224                 asm:    x86.AIMULW,
1225                 reg: regInfo{
1226                         inputs: []inputInfo{
1227                                 {0, 1},     // AX
1228                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1229                         },
1230                         clobbers: 8589934593, // AX FLAGS
1231                         outputs: []regMask{
1232                                 4, // DX
1233                         },
1234                 },
1235         },
1236         {
1237                 name:   "HMULB",
1238                 argLen: 2,
1239                 asm:    x86.AIMULB,
1240                 reg: regInfo{
1241                         inputs: []inputInfo{
1242                                 {0, 1},     // AX
1243                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1244                         },
1245                         clobbers: 8589934593, // AX FLAGS
1246                         outputs: []regMask{
1247                                 4, // DX
1248                         },
1249                 },
1250         },
1251         {
1252                 name:   "HMULQU",
1253                 argLen: 2,
1254                 asm:    x86.AMULQ,
1255                 reg: regInfo{
1256                         inputs: []inputInfo{
1257                                 {0, 1},     // AX
1258                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1259                         },
1260                         clobbers: 8589934593, // AX FLAGS
1261                         outputs: []regMask{
1262                                 4, // DX
1263                         },
1264                 },
1265         },
1266         {
1267                 name:   "HMULLU",
1268                 argLen: 2,
1269                 asm:    x86.AMULL,
1270                 reg: regInfo{
1271                         inputs: []inputInfo{
1272                                 {0, 1},     // AX
1273                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1274                         },
1275                         clobbers: 8589934593, // AX FLAGS
1276                         outputs: []regMask{
1277                                 4, // DX
1278                         },
1279                 },
1280         },
1281         {
1282                 name:   "HMULWU",
1283                 argLen: 2,
1284                 asm:    x86.AMULW,
1285                 reg: regInfo{
1286                         inputs: []inputInfo{
1287                                 {0, 1},     // AX
1288                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1289                         },
1290                         clobbers: 8589934593, // AX FLAGS
1291                         outputs: []regMask{
1292                                 4, // DX
1293                         },
1294                 },
1295         },
1296         {
1297                 name:   "HMULBU",
1298                 argLen: 2,
1299                 asm:    x86.AMULB,
1300                 reg: regInfo{
1301                         inputs: []inputInfo{
1302                                 {0, 1},     // AX
1303                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1304                         },
1305                         clobbers: 8589934593, // AX FLAGS
1306                         outputs: []regMask{
1307                                 4, // DX
1308                         },
1309                 },
1310         },
1311         {
1312                 name:         "AVGQU",
1313                 argLen:       2,
1314                 commutative:  true,
1315                 resultInArg0: true,
1316                 reg: regInfo{
1317                         inputs: []inputInfo{
1318                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1319                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1320                         },
1321                         clobbers: 8589934592, // FLAGS
1322                         outputs: []regMask{
1323                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1324                         },
1325                 },
1326         },
1327         {
1328                 name:   "DIVQ",
1329                 argLen: 2,
1330                 asm:    x86.AIDIVQ,
1331                 reg: regInfo{
1332                         inputs: []inputInfo{
1333                                 {0, 1},     // AX
1334                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1335                         },
1336                         clobbers: 8589934596, // DX FLAGS
1337                         outputs: []regMask{
1338                                 1, // AX
1339                         },
1340                 },
1341         },
1342         {
1343                 name:   "DIVL",
1344                 argLen: 2,
1345                 asm:    x86.AIDIVL,
1346                 reg: regInfo{
1347                         inputs: []inputInfo{
1348                                 {0, 1},     // AX
1349                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1350                         },
1351                         clobbers: 8589934596, // DX FLAGS
1352                         outputs: []regMask{
1353                                 1, // AX
1354                         },
1355                 },
1356         },
1357         {
1358                 name:   "DIVW",
1359                 argLen: 2,
1360                 asm:    x86.AIDIVW,
1361                 reg: regInfo{
1362                         inputs: []inputInfo{
1363                                 {0, 1},     // AX
1364                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1365                         },
1366                         clobbers: 8589934596, // DX FLAGS
1367                         outputs: []regMask{
1368                                 1, // AX
1369                         },
1370                 },
1371         },
1372         {
1373                 name:   "DIVQU",
1374                 argLen: 2,
1375                 asm:    x86.ADIVQ,
1376                 reg: regInfo{
1377                         inputs: []inputInfo{
1378                                 {0, 1},     // AX
1379                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1380                         },
1381                         clobbers: 8589934596, // DX FLAGS
1382                         outputs: []regMask{
1383                                 1, // AX
1384                         },
1385                 },
1386         },
1387         {
1388                 name:   "DIVLU",
1389                 argLen: 2,
1390                 asm:    x86.ADIVL,
1391                 reg: regInfo{
1392                         inputs: []inputInfo{
1393                                 {0, 1},     // AX
1394                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1395                         },
1396                         clobbers: 8589934596, // DX FLAGS
1397                         outputs: []regMask{
1398                                 1, // AX
1399                         },
1400                 },
1401         },
1402         {
1403                 name:   "DIVWU",
1404                 argLen: 2,
1405                 asm:    x86.ADIVW,
1406                 reg: regInfo{
1407                         inputs: []inputInfo{
1408                                 {0, 1},     // AX
1409                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1410                         },
1411                         clobbers: 8589934596, // DX FLAGS
1412                         outputs: []regMask{
1413                                 1, // AX
1414                         },
1415                 },
1416         },
1417         {
1418                 name:   "MODQ",
1419                 argLen: 2,
1420                 asm:    x86.AIDIVQ,
1421                 reg: regInfo{
1422                         inputs: []inputInfo{
1423                                 {0, 1},     // AX
1424                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1425                         },
1426                         clobbers: 8589934593, // AX FLAGS
1427                         outputs: []regMask{
1428                                 4, // DX
1429                         },
1430                 },
1431         },
1432         {
1433                 name:   "MODL",
1434                 argLen: 2,
1435                 asm:    x86.AIDIVL,
1436                 reg: regInfo{
1437                         inputs: []inputInfo{
1438                                 {0, 1},     // AX
1439                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1440                         },
1441                         clobbers: 8589934593, // AX FLAGS
1442                         outputs: []regMask{
1443                                 4, // DX
1444                         },
1445                 },
1446         },
1447         {
1448                 name:   "MODW",
1449                 argLen: 2,
1450                 asm:    x86.AIDIVW,
1451                 reg: regInfo{
1452                         inputs: []inputInfo{
1453                                 {0, 1},     // AX
1454                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1455                         },
1456                         clobbers: 8589934593, // AX FLAGS
1457                         outputs: []regMask{
1458                                 4, // DX
1459                         },
1460                 },
1461         },
1462         {
1463                 name:   "MODQU",
1464                 argLen: 2,
1465                 asm:    x86.ADIVQ,
1466                 reg: regInfo{
1467                         inputs: []inputInfo{
1468                                 {0, 1},     // AX
1469                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1470                         },
1471                         clobbers: 8589934593, // AX FLAGS
1472                         outputs: []regMask{
1473                                 4, // DX
1474                         },
1475                 },
1476         },
1477         {
1478                 name:   "MODLU",
1479                 argLen: 2,
1480                 asm:    x86.ADIVL,
1481                 reg: regInfo{
1482                         inputs: []inputInfo{
1483                                 {0, 1},     // AX
1484                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1485                         },
1486                         clobbers: 8589934593, // AX FLAGS
1487                         outputs: []regMask{
1488                                 4, // DX
1489                         },
1490                 },
1491         },
1492         {
1493                 name:   "MODWU",
1494                 argLen: 2,
1495                 asm:    x86.ADIVW,
1496                 reg: regInfo{
1497                         inputs: []inputInfo{
1498                                 {0, 1},     // AX
1499                                 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1500                         },
1501                         clobbers: 8589934593, // AX FLAGS
1502                         outputs: []regMask{
1503                                 4, // DX
1504                         },
1505                 },
1506         },
1507         {
1508                 name:         "ANDQ",
1509                 argLen:       2,
1510                 commutative:  true,
1511                 resultInArg0: true,
1512                 asm:          x86.AANDQ,
1513                 reg: regInfo{
1514                         inputs: []inputInfo{
1515                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1516                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1517                         },
1518                         clobbers: 8589934592, // FLAGS
1519                         outputs: []regMask{
1520                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1521                         },
1522                 },
1523         },
1524         {
1525                 name:         "ANDL",
1526                 argLen:       2,
1527                 commutative:  true,
1528                 resultInArg0: true,
1529                 asm:          x86.AANDL,
1530                 reg: regInfo{
1531                         inputs: []inputInfo{
1532                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1533                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1534                         },
1535                         clobbers: 8589934592, // FLAGS
1536                         outputs: []regMask{
1537                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1538                         },
1539                 },
1540         },
1541         {
1542                 name:         "ANDQconst",
1543                 auxType:      auxInt64,
1544                 argLen:       1,
1545                 resultInArg0: true,
1546                 asm:          x86.AANDQ,
1547                 reg: regInfo{
1548                         inputs: []inputInfo{
1549                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1550                         },
1551                         clobbers: 8589934592, // FLAGS
1552                         outputs: []regMask{
1553                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1554                         },
1555                 },
1556         },
1557         {
1558                 name:         "ANDLconst",
1559                 auxType:      auxInt32,
1560                 argLen:       1,
1561                 resultInArg0: true,
1562                 asm:          x86.AANDL,
1563                 reg: regInfo{
1564                         inputs: []inputInfo{
1565                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1566                         },
1567                         clobbers: 8589934592, // FLAGS
1568                         outputs: []regMask{
1569                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1570                         },
1571                 },
1572         },
1573         {
1574                 name:         "ORQ",
1575                 argLen:       2,
1576                 commutative:  true,
1577                 resultInArg0: true,
1578                 asm:          x86.AORQ,
1579                 reg: regInfo{
1580                         inputs: []inputInfo{
1581                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1582                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1583                         },
1584                         clobbers: 8589934592, // FLAGS
1585                         outputs: []regMask{
1586                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1587                         },
1588                 },
1589         },
1590         {
1591                 name:         "ORL",
1592                 argLen:       2,
1593                 commutative:  true,
1594                 resultInArg0: true,
1595                 asm:          x86.AORL,
1596                 reg: regInfo{
1597                         inputs: []inputInfo{
1598                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1599                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1600                         },
1601                         clobbers: 8589934592, // FLAGS
1602                         outputs: []regMask{
1603                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1604                         },
1605                 },
1606         },
1607         {
1608                 name:         "ORQconst",
1609                 auxType:      auxInt64,
1610                 argLen:       1,
1611                 resultInArg0: true,
1612                 asm:          x86.AORQ,
1613                 reg: regInfo{
1614                         inputs: []inputInfo{
1615                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1616                         },
1617                         clobbers: 8589934592, // FLAGS
1618                         outputs: []regMask{
1619                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1620                         },
1621                 },
1622         },
1623         {
1624                 name:         "ORLconst",
1625                 auxType:      auxInt32,
1626                 argLen:       1,
1627                 resultInArg0: true,
1628                 asm:          x86.AORL,
1629                 reg: regInfo{
1630                         inputs: []inputInfo{
1631                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1632                         },
1633                         clobbers: 8589934592, // FLAGS
1634                         outputs: []regMask{
1635                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1636                         },
1637                 },
1638         },
1639         {
1640                 name:         "XORQ",
1641                 argLen:       2,
1642                 commutative:  true,
1643                 resultInArg0: true,
1644                 asm:          x86.AXORQ,
1645                 reg: regInfo{
1646                         inputs: []inputInfo{
1647                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1648                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1649                         },
1650                         clobbers: 8589934592, // FLAGS
1651                         outputs: []regMask{
1652                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1653                         },
1654                 },
1655         },
1656         {
1657                 name:         "XORL",
1658                 argLen:       2,
1659                 commutative:  true,
1660                 resultInArg0: true,
1661                 asm:          x86.AXORL,
1662                 reg: regInfo{
1663                         inputs: []inputInfo{
1664                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1665                                 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1666                         },
1667                         clobbers: 8589934592, // FLAGS
1668                         outputs: []regMask{
1669                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1670                         },
1671                 },
1672         },
1673         {
1674                 name:         "XORQconst",
1675                 auxType:      auxInt64,
1676                 argLen:       1,
1677                 resultInArg0: true,
1678                 asm:          x86.AXORQ,
1679                 reg: regInfo{
1680                         inputs: []inputInfo{
1681                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1682                         },
1683                         clobbers: 8589934592, // FLAGS
1684                         outputs: []regMask{
1685                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1686                         },
1687                 },
1688         },
1689         {
1690                 name:         "XORLconst",
1691                 auxType:      auxInt32,
1692                 argLen:       1,
1693                 resultInArg0: true,
1694                 asm:          x86.AXORL,
1695                 reg: regInfo{
1696                         inputs: []inputInfo{
1697                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1698                         },
1699                         clobbers: 8589934592, // FLAGS
1700                         outputs: []regMask{
1701                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1702                         },
1703                 },
1704         },
1705         {
1706                 name:   "CMPQ",
1707                 argLen: 2,
1708                 asm:    x86.ACMPQ,
1709                 reg: regInfo{
1710                         inputs: []inputInfo{
1711                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1712                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1713                         },
1714                         outputs: []regMask{
1715                                 8589934592, // FLAGS
1716                         },
1717                 },
1718         },
1719         {
1720                 name:   "CMPL",
1721                 argLen: 2,
1722                 asm:    x86.ACMPL,
1723                 reg: regInfo{
1724                         inputs: []inputInfo{
1725                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1726                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1727                         },
1728                         outputs: []regMask{
1729                                 8589934592, // FLAGS
1730                         },
1731                 },
1732         },
1733         {
1734                 name:   "CMPW",
1735                 argLen: 2,
1736                 asm:    x86.ACMPW,
1737                 reg: regInfo{
1738                         inputs: []inputInfo{
1739                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1740                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1741                         },
1742                         outputs: []regMask{
1743                                 8589934592, // FLAGS
1744                         },
1745                 },
1746         },
1747         {
1748                 name:   "CMPB",
1749                 argLen: 2,
1750                 asm:    x86.ACMPB,
1751                 reg: regInfo{
1752                         inputs: []inputInfo{
1753                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1754                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1755                         },
1756                         outputs: []regMask{
1757                                 8589934592, // FLAGS
1758                         },
1759                 },
1760         },
1761         {
1762                 name:    "CMPQconst",
1763                 auxType: auxInt64,
1764                 argLen:  1,
1765                 asm:     x86.ACMPQ,
1766                 reg: regInfo{
1767                         inputs: []inputInfo{
1768                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1769                         },
1770                         outputs: []regMask{
1771                                 8589934592, // FLAGS
1772                         },
1773                 },
1774         },
1775         {
1776                 name:    "CMPLconst",
1777                 auxType: auxInt32,
1778                 argLen:  1,
1779                 asm:     x86.ACMPL,
1780                 reg: regInfo{
1781                         inputs: []inputInfo{
1782                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1783                         },
1784                         outputs: []regMask{
1785                                 8589934592, // FLAGS
1786                         },
1787                 },
1788         },
1789         {
1790                 name:    "CMPWconst",
1791                 auxType: auxInt16,
1792                 argLen:  1,
1793                 asm:     x86.ACMPW,
1794                 reg: regInfo{
1795                         inputs: []inputInfo{
1796                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1797                         },
1798                         outputs: []regMask{
1799                                 8589934592, // FLAGS
1800                         },
1801                 },
1802         },
1803         {
1804                 name:    "CMPBconst",
1805                 auxType: auxInt8,
1806                 argLen:  1,
1807                 asm:     x86.ACMPB,
1808                 reg: regInfo{
1809                         inputs: []inputInfo{
1810                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1811                         },
1812                         outputs: []regMask{
1813                                 8589934592, // FLAGS
1814                         },
1815                 },
1816         },
1817         {
1818                 name:   "UCOMISS",
1819                 argLen: 2,
1820                 asm:    x86.AUCOMISS,
1821                 reg: regInfo{
1822                         inputs: []inputInfo{
1823                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
1824                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
1825                         },
1826                         outputs: []regMask{
1827                                 8589934592, // FLAGS
1828                         },
1829                 },
1830         },
1831         {
1832                 name:   "UCOMISD",
1833                 argLen: 2,
1834                 asm:    x86.AUCOMISD,
1835                 reg: regInfo{
1836                         inputs: []inputInfo{
1837                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
1838                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
1839                         },
1840                         outputs: []regMask{
1841                                 8589934592, // FLAGS
1842                         },
1843                 },
1844         },
1845         {
1846                 name:   "TESTQ",
1847                 argLen: 2,
1848                 asm:    x86.ATESTQ,
1849                 reg: regInfo{
1850                         inputs: []inputInfo{
1851                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1852                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1853                         },
1854                         outputs: []regMask{
1855                                 8589934592, // FLAGS
1856                         },
1857                 },
1858         },
1859         {
1860                 name:   "TESTL",
1861                 argLen: 2,
1862                 asm:    x86.ATESTL,
1863                 reg: regInfo{
1864                         inputs: []inputInfo{
1865                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1866                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1867                         },
1868                         outputs: []regMask{
1869                                 8589934592, // FLAGS
1870                         },
1871                 },
1872         },
1873         {
1874                 name:   "TESTW",
1875                 argLen: 2,
1876                 asm:    x86.ATESTW,
1877                 reg: regInfo{
1878                         inputs: []inputInfo{
1879                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1880                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1881                         },
1882                         outputs: []regMask{
1883                                 8589934592, // FLAGS
1884                         },
1885                 },
1886         },
1887         {
1888                 name:   "TESTB",
1889                 argLen: 2,
1890                 asm:    x86.ATESTB,
1891                 reg: regInfo{
1892                         inputs: []inputInfo{
1893                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1894                                 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1895                         },
1896                         outputs: []regMask{
1897                                 8589934592, // FLAGS
1898                         },
1899                 },
1900         },
1901         {
1902                 name:    "TESTQconst",
1903                 auxType: auxInt64,
1904                 argLen:  1,
1905                 asm:     x86.ATESTQ,
1906                 reg: regInfo{
1907                         inputs: []inputInfo{
1908                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1909                         },
1910                         outputs: []regMask{
1911                                 8589934592, // FLAGS
1912                         },
1913                 },
1914         },
1915         {
1916                 name:    "TESTLconst",
1917                 auxType: auxInt32,
1918                 argLen:  1,
1919                 asm:     x86.ATESTL,
1920                 reg: regInfo{
1921                         inputs: []inputInfo{
1922                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1923                         },
1924                         outputs: []regMask{
1925                                 8589934592, // FLAGS
1926                         },
1927                 },
1928         },
1929         {
1930                 name:    "TESTWconst",
1931                 auxType: auxInt16,
1932                 argLen:  1,
1933                 asm:     x86.ATESTW,
1934                 reg: regInfo{
1935                         inputs: []inputInfo{
1936                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1937                         },
1938                         outputs: []regMask{
1939                                 8589934592, // FLAGS
1940                         },
1941                 },
1942         },
1943         {
1944                 name:    "TESTBconst",
1945                 auxType: auxInt8,
1946                 argLen:  1,
1947                 asm:     x86.ATESTB,
1948                 reg: regInfo{
1949                         inputs: []inputInfo{
1950                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1951                         },
1952                         outputs: []regMask{
1953                                 8589934592, // FLAGS
1954                         },
1955                 },
1956         },
1957         {
1958                 name:         "SHLQ",
1959                 argLen:       2,
1960                 resultInArg0: true,
1961                 asm:          x86.ASHLQ,
1962                 reg: regInfo{
1963                         inputs: []inputInfo{
1964                                 {1, 2},     // CX
1965                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1966                         },
1967                         clobbers: 8589934592, // FLAGS
1968                         outputs: []regMask{
1969                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1970                         },
1971                 },
1972         },
1973         {
1974                 name:         "SHLL",
1975                 argLen:       2,
1976                 resultInArg0: true,
1977                 asm:          x86.ASHLL,
1978                 reg: regInfo{
1979                         inputs: []inputInfo{
1980                                 {1, 2},     // CX
1981                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1982                         },
1983                         clobbers: 8589934592, // FLAGS
1984                         outputs: []regMask{
1985                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1986                         },
1987                 },
1988         },
1989         {
1990                 name:         "SHLQconst",
1991                 auxType:      auxInt64,
1992                 argLen:       1,
1993                 resultInArg0: true,
1994                 asm:          x86.ASHLQ,
1995                 reg: regInfo{
1996                         inputs: []inputInfo{
1997                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
1998                         },
1999                         clobbers: 8589934592, // FLAGS
2000                         outputs: []regMask{
2001                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2002                         },
2003                 },
2004         },
2005         {
2006                 name:         "SHLLconst",
2007                 auxType:      auxInt32,
2008                 argLen:       1,
2009                 resultInArg0: true,
2010                 asm:          x86.ASHLL,
2011                 reg: regInfo{
2012                         inputs: []inputInfo{
2013                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2014                         },
2015                         clobbers: 8589934592, // FLAGS
2016                         outputs: []regMask{
2017                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2018                         },
2019                 },
2020         },
2021         {
2022                 name:         "SHRQ",
2023                 argLen:       2,
2024                 resultInArg0: true,
2025                 asm:          x86.ASHRQ,
2026                 reg: regInfo{
2027                         inputs: []inputInfo{
2028                                 {1, 2},     // CX
2029                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2030                         },
2031                         clobbers: 8589934592, // FLAGS
2032                         outputs: []regMask{
2033                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2034                         },
2035                 },
2036         },
2037         {
2038                 name:         "SHRL",
2039                 argLen:       2,
2040                 resultInArg0: true,
2041                 asm:          x86.ASHRL,
2042                 reg: regInfo{
2043                         inputs: []inputInfo{
2044                                 {1, 2},     // CX
2045                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2046                         },
2047                         clobbers: 8589934592, // FLAGS
2048                         outputs: []regMask{
2049                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2050                         },
2051                 },
2052         },
2053         {
2054                 name:         "SHRW",
2055                 argLen:       2,
2056                 resultInArg0: true,
2057                 asm:          x86.ASHRW,
2058                 reg: regInfo{
2059                         inputs: []inputInfo{
2060                                 {1, 2},     // CX
2061                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2062                         },
2063                         clobbers: 8589934592, // FLAGS
2064                         outputs: []regMask{
2065                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2066                         },
2067                 },
2068         },
2069         {
2070                 name:         "SHRB",
2071                 argLen:       2,
2072                 resultInArg0: true,
2073                 asm:          x86.ASHRB,
2074                 reg: regInfo{
2075                         inputs: []inputInfo{
2076                                 {1, 2},     // CX
2077                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2078                         },
2079                         clobbers: 8589934592, // FLAGS
2080                         outputs: []regMask{
2081                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2082                         },
2083                 },
2084         },
2085         {
2086                 name:         "SHRQconst",
2087                 auxType:      auxInt64,
2088                 argLen:       1,
2089                 resultInArg0: true,
2090                 asm:          x86.ASHRQ,
2091                 reg: regInfo{
2092                         inputs: []inputInfo{
2093                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2094                         },
2095                         clobbers: 8589934592, // FLAGS
2096                         outputs: []regMask{
2097                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2098                         },
2099                 },
2100         },
2101         {
2102                 name:         "SHRLconst",
2103                 auxType:      auxInt32,
2104                 argLen:       1,
2105                 resultInArg0: true,
2106                 asm:          x86.ASHRL,
2107                 reg: regInfo{
2108                         inputs: []inputInfo{
2109                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2110                         },
2111                         clobbers: 8589934592, // FLAGS
2112                         outputs: []regMask{
2113                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2114                         },
2115                 },
2116         },
2117         {
2118                 name:         "SHRWconst",
2119                 auxType:      auxInt16,
2120                 argLen:       1,
2121                 resultInArg0: true,
2122                 asm:          x86.ASHRW,
2123                 reg: regInfo{
2124                         inputs: []inputInfo{
2125                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2126                         },
2127                         clobbers: 8589934592, // FLAGS
2128                         outputs: []regMask{
2129                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2130                         },
2131                 },
2132         },
2133         {
2134                 name:         "SHRBconst",
2135                 auxType:      auxInt8,
2136                 argLen:       1,
2137                 resultInArg0: true,
2138                 asm:          x86.ASHRB,
2139                 reg: regInfo{
2140                         inputs: []inputInfo{
2141                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2142                         },
2143                         clobbers: 8589934592, // FLAGS
2144                         outputs: []regMask{
2145                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2146                         },
2147                 },
2148         },
2149         {
2150                 name:         "SARQ",
2151                 argLen:       2,
2152                 resultInArg0: true,
2153                 asm:          x86.ASARQ,
2154                 reg: regInfo{
2155                         inputs: []inputInfo{
2156                                 {1, 2},     // CX
2157                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2158                         },
2159                         clobbers: 8589934592, // FLAGS
2160                         outputs: []regMask{
2161                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2162                         },
2163                 },
2164         },
2165         {
2166                 name:         "SARL",
2167                 argLen:       2,
2168                 resultInArg0: true,
2169                 asm:          x86.ASARL,
2170                 reg: regInfo{
2171                         inputs: []inputInfo{
2172                                 {1, 2},     // CX
2173                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2174                         },
2175                         clobbers: 8589934592, // FLAGS
2176                         outputs: []regMask{
2177                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2178                         },
2179                 },
2180         },
2181         {
2182                 name:         "SARW",
2183                 argLen:       2,
2184                 resultInArg0: true,
2185                 asm:          x86.ASARW,
2186                 reg: regInfo{
2187                         inputs: []inputInfo{
2188                                 {1, 2},     // CX
2189                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2190                         },
2191                         clobbers: 8589934592, // FLAGS
2192                         outputs: []regMask{
2193                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2194                         },
2195                 },
2196         },
2197         {
2198                 name:         "SARB",
2199                 argLen:       2,
2200                 resultInArg0: true,
2201                 asm:          x86.ASARB,
2202                 reg: regInfo{
2203                         inputs: []inputInfo{
2204                                 {1, 2},     // CX
2205                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2206                         },
2207                         clobbers: 8589934592, // FLAGS
2208                         outputs: []regMask{
2209                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2210                         },
2211                 },
2212         },
2213         {
2214                 name:         "SARQconst",
2215                 auxType:      auxInt64,
2216                 argLen:       1,
2217                 resultInArg0: true,
2218                 asm:          x86.ASARQ,
2219                 reg: regInfo{
2220                         inputs: []inputInfo{
2221                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2222                         },
2223                         clobbers: 8589934592, // FLAGS
2224                         outputs: []regMask{
2225                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2226                         },
2227                 },
2228         },
2229         {
2230                 name:         "SARLconst",
2231                 auxType:      auxInt32,
2232                 argLen:       1,
2233                 resultInArg0: true,
2234                 asm:          x86.ASARL,
2235                 reg: regInfo{
2236                         inputs: []inputInfo{
2237                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2238                         },
2239                         clobbers: 8589934592, // FLAGS
2240                         outputs: []regMask{
2241                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2242                         },
2243                 },
2244         },
2245         {
2246                 name:         "SARWconst",
2247                 auxType:      auxInt16,
2248                 argLen:       1,
2249                 resultInArg0: true,
2250                 asm:          x86.ASARW,
2251                 reg: regInfo{
2252                         inputs: []inputInfo{
2253                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2254                         },
2255                         clobbers: 8589934592, // FLAGS
2256                         outputs: []regMask{
2257                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2258                         },
2259                 },
2260         },
2261         {
2262                 name:         "SARBconst",
2263                 auxType:      auxInt8,
2264                 argLen:       1,
2265                 resultInArg0: true,
2266                 asm:          x86.ASARB,
2267                 reg: regInfo{
2268                         inputs: []inputInfo{
2269                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2270                         },
2271                         clobbers: 8589934592, // FLAGS
2272                         outputs: []regMask{
2273                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2274                         },
2275                 },
2276         },
2277         {
2278                 name:         "ROLQconst",
2279                 auxType:      auxInt64,
2280                 argLen:       1,
2281                 resultInArg0: true,
2282                 asm:          x86.AROLQ,
2283                 reg: regInfo{
2284                         inputs: []inputInfo{
2285                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2286                         },
2287                         clobbers: 8589934592, // FLAGS
2288                         outputs: []regMask{
2289                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2290                         },
2291                 },
2292         },
2293         {
2294                 name:         "ROLLconst",
2295                 auxType:      auxInt32,
2296                 argLen:       1,
2297                 resultInArg0: true,
2298                 asm:          x86.AROLL,
2299                 reg: regInfo{
2300                         inputs: []inputInfo{
2301                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2302                         },
2303                         clobbers: 8589934592, // FLAGS
2304                         outputs: []regMask{
2305                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2306                         },
2307                 },
2308         },
2309         {
2310                 name:         "ROLWconst",
2311                 auxType:      auxInt16,
2312                 argLen:       1,
2313                 resultInArg0: true,
2314                 asm:          x86.AROLW,
2315                 reg: regInfo{
2316                         inputs: []inputInfo{
2317                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2318                         },
2319                         clobbers: 8589934592, // FLAGS
2320                         outputs: []regMask{
2321                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2322                         },
2323                 },
2324         },
2325         {
2326                 name:         "ROLBconst",
2327                 auxType:      auxInt8,
2328                 argLen:       1,
2329                 resultInArg0: true,
2330                 asm:          x86.AROLB,
2331                 reg: regInfo{
2332                         inputs: []inputInfo{
2333                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2334                         },
2335                         clobbers: 8589934592, // FLAGS
2336                         outputs: []regMask{
2337                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2338                         },
2339                 },
2340         },
2341         {
2342                 name:         "NEGQ",
2343                 argLen:       1,
2344                 resultInArg0: true,
2345                 asm:          x86.ANEGQ,
2346                 reg: regInfo{
2347                         inputs: []inputInfo{
2348                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2349                         },
2350                         clobbers: 8589934592, // FLAGS
2351                         outputs: []regMask{
2352                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2353                         },
2354                 },
2355         },
2356         {
2357                 name:         "NEGL",
2358                 argLen:       1,
2359                 resultInArg0: true,
2360                 asm:          x86.ANEGL,
2361                 reg: regInfo{
2362                         inputs: []inputInfo{
2363                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2364                         },
2365                         clobbers: 8589934592, // FLAGS
2366                         outputs: []regMask{
2367                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2368                         },
2369                 },
2370         },
2371         {
2372                 name:         "NOTQ",
2373                 argLen:       1,
2374                 resultInArg0: true,
2375                 asm:          x86.ANOTQ,
2376                 reg: regInfo{
2377                         inputs: []inputInfo{
2378                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2379                         },
2380                         clobbers: 8589934592, // FLAGS
2381                         outputs: []regMask{
2382                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2383                         },
2384                 },
2385         },
2386         {
2387                 name:         "NOTL",
2388                 argLen:       1,
2389                 resultInArg0: true,
2390                 asm:          x86.ANOTL,
2391                 reg: regInfo{
2392                         inputs: []inputInfo{
2393                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2394                         },
2395                         clobbers: 8589934592, // FLAGS
2396                         outputs: []regMask{
2397                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2398                         },
2399                 },
2400         },
2401         {
2402                 name:   "BSFQ",
2403                 argLen: 1,
2404                 asm:    x86.ABSFQ,
2405                 reg: regInfo{
2406                         inputs: []inputInfo{
2407                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2408                         },
2409                         clobbers: 8589934592, // FLAGS
2410                         outputs: []regMask{
2411                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2412                         },
2413                 },
2414         },
2415         {
2416                 name:   "BSFL",
2417                 argLen: 1,
2418                 asm:    x86.ABSFL,
2419                 reg: regInfo{
2420                         inputs: []inputInfo{
2421                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2422                         },
2423                         clobbers: 8589934592, // FLAGS
2424                         outputs: []regMask{
2425                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2426                         },
2427                 },
2428         },
2429         {
2430                 name:   "BSFW",
2431                 argLen: 1,
2432                 asm:    x86.ABSFW,
2433                 reg: regInfo{
2434                         inputs: []inputInfo{
2435                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2436                         },
2437                         clobbers: 8589934592, // FLAGS
2438                         outputs: []regMask{
2439                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2440                         },
2441                 },
2442         },
2443         {
2444                 name:   "BSRQ",
2445                 argLen: 1,
2446                 asm:    x86.ABSRQ,
2447                 reg: regInfo{
2448                         inputs: []inputInfo{
2449                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2450                         },
2451                         clobbers: 8589934592, // FLAGS
2452                         outputs: []regMask{
2453                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2454                         },
2455                 },
2456         },
2457         {
2458                 name:   "BSRL",
2459                 argLen: 1,
2460                 asm:    x86.ABSRL,
2461                 reg: regInfo{
2462                         inputs: []inputInfo{
2463                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2464                         },
2465                         clobbers: 8589934592, // FLAGS
2466                         outputs: []regMask{
2467                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2468                         },
2469                 },
2470         },
2471         {
2472                 name:   "BSRW",
2473                 argLen: 1,
2474                 asm:    x86.ABSRW,
2475                 reg: regInfo{
2476                         inputs: []inputInfo{
2477                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2478                         },
2479                         clobbers: 8589934592, // FLAGS
2480                         outputs: []regMask{
2481                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2482                         },
2483                 },
2484         },
2485         {
2486                 name:         "CMOVQEQconst",
2487                 auxType:      auxInt64,
2488                 argLen:       2,
2489                 resultInArg0: true,
2490                 asm:          x86.ACMOVQEQ,
2491                 reg: regInfo{
2492                         inputs: []inputInfo{
2493                                 {1, 8589934592}, // FLAGS
2494                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2495                         },
2496                         clobbers: 8589934593, // AX FLAGS
2497                         outputs: []regMask{
2498                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2499                         },
2500                 },
2501         },
2502         {
2503                 name:         "CMOVLEQconst",
2504                 auxType:      auxInt32,
2505                 argLen:       2,
2506                 resultInArg0: true,
2507                 asm:          x86.ACMOVLEQ,
2508                 reg: regInfo{
2509                         inputs: []inputInfo{
2510                                 {1, 8589934592}, // FLAGS
2511                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2512                         },
2513                         clobbers: 8589934593, // AX FLAGS
2514                         outputs: []regMask{
2515                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2516                         },
2517                 },
2518         },
2519         {
2520                 name:         "CMOVWEQconst",
2521                 auxType:      auxInt16,
2522                 argLen:       2,
2523                 resultInArg0: true,
2524                 asm:          x86.ACMOVLEQ,
2525                 reg: regInfo{
2526                         inputs: []inputInfo{
2527                                 {1, 8589934592}, // FLAGS
2528                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2529                         },
2530                         clobbers: 8589934593, // AX FLAGS
2531                         outputs: []regMask{
2532                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2533                         },
2534                 },
2535         },
2536         {
2537                 name:         "CMOVQNEconst",
2538                 auxType:      auxInt64,
2539                 argLen:       2,
2540                 resultInArg0: true,
2541                 asm:          x86.ACMOVQNE,
2542                 reg: regInfo{
2543                         inputs: []inputInfo{
2544                                 {1, 8589934592}, // FLAGS
2545                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2546                         },
2547                         clobbers: 8589934593, // AX FLAGS
2548                         outputs: []regMask{
2549                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2550                         },
2551                 },
2552         },
2553         {
2554                 name:         "CMOVLNEconst",
2555                 auxType:      auxInt32,
2556                 argLen:       2,
2557                 resultInArg0: true,
2558                 asm:          x86.ACMOVLNE,
2559                 reg: regInfo{
2560                         inputs: []inputInfo{
2561                                 {1, 8589934592}, // FLAGS
2562                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2563                         },
2564                         clobbers: 8589934593, // AX FLAGS
2565                         outputs: []regMask{
2566                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2567                         },
2568                 },
2569         },
2570         {
2571                 name:         "CMOVWNEconst",
2572                 auxType:      auxInt16,
2573                 argLen:       2,
2574                 resultInArg0: true,
2575                 asm:          x86.ACMOVLNE,
2576                 reg: regInfo{
2577                         inputs: []inputInfo{
2578                                 {1, 8589934592}, // FLAGS
2579                                 {0, 65518},      // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2580                         },
2581                         clobbers: 8589934593, // AX FLAGS
2582                         outputs: []regMask{
2583                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2584                         },
2585                 },
2586         },
2587         {
2588                 name:         "BSWAPQ",
2589                 argLen:       1,
2590                 resultInArg0: true,
2591                 asm:          x86.ABSWAPQ,
2592                 reg: regInfo{
2593                         inputs: []inputInfo{
2594                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2595                         },
2596                         clobbers: 8589934592, // FLAGS
2597                         outputs: []regMask{
2598                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2599                         },
2600                 },
2601         },
2602         {
2603                 name:         "BSWAPL",
2604                 argLen:       1,
2605                 resultInArg0: true,
2606                 asm:          x86.ABSWAPL,
2607                 reg: regInfo{
2608                         inputs: []inputInfo{
2609                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2610                         },
2611                         clobbers: 8589934592, // FLAGS
2612                         outputs: []regMask{
2613                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2614                         },
2615                 },
2616         },
2617         {
2618                 name:   "SQRTSD",
2619                 argLen: 1,
2620                 asm:    x86.ASQRTSD,
2621                 reg: regInfo{
2622                         inputs: []inputInfo{
2623                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
2624                         },
2625                         outputs: []regMask{
2626                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
2627                         },
2628                 },
2629         },
2630         {
2631                 name:   "SBBQcarrymask",
2632                 argLen: 1,
2633                 asm:    x86.ASBBQ,
2634                 reg: regInfo{
2635                         inputs: []inputInfo{
2636                                 {0, 8589934592}, // FLAGS
2637                         },
2638                         outputs: []regMask{
2639                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2640                         },
2641                 },
2642         },
2643         {
2644                 name:   "SBBLcarrymask",
2645                 argLen: 1,
2646                 asm:    x86.ASBBL,
2647                 reg: regInfo{
2648                         inputs: []inputInfo{
2649                                 {0, 8589934592}, // FLAGS
2650                         },
2651                         outputs: []regMask{
2652                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2653                         },
2654                 },
2655         },
2656         {
2657                 name:   "SETEQ",
2658                 argLen: 1,
2659                 asm:    x86.ASETEQ,
2660                 reg: regInfo{
2661                         inputs: []inputInfo{
2662                                 {0, 8589934592}, // FLAGS
2663                         },
2664                         outputs: []regMask{
2665                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2666                         },
2667                 },
2668         },
2669         {
2670                 name:   "SETNE",
2671                 argLen: 1,
2672                 asm:    x86.ASETNE,
2673                 reg: regInfo{
2674                         inputs: []inputInfo{
2675                                 {0, 8589934592}, // FLAGS
2676                         },
2677                         outputs: []regMask{
2678                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2679                         },
2680                 },
2681         },
2682         {
2683                 name:   "SETL",
2684                 argLen: 1,
2685                 asm:    x86.ASETLT,
2686                 reg: regInfo{
2687                         inputs: []inputInfo{
2688                                 {0, 8589934592}, // FLAGS
2689                         },
2690                         outputs: []regMask{
2691                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2692                         },
2693                 },
2694         },
2695         {
2696                 name:   "SETLE",
2697                 argLen: 1,
2698                 asm:    x86.ASETLE,
2699                 reg: regInfo{
2700                         inputs: []inputInfo{
2701                                 {0, 8589934592}, // FLAGS
2702                         },
2703                         outputs: []regMask{
2704                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2705                         },
2706                 },
2707         },
2708         {
2709                 name:   "SETG",
2710                 argLen: 1,
2711                 asm:    x86.ASETGT,
2712                 reg: regInfo{
2713                         inputs: []inputInfo{
2714                                 {0, 8589934592}, // FLAGS
2715                         },
2716                         outputs: []regMask{
2717                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2718                         },
2719                 },
2720         },
2721         {
2722                 name:   "SETGE",
2723                 argLen: 1,
2724                 asm:    x86.ASETGE,
2725                 reg: regInfo{
2726                         inputs: []inputInfo{
2727                                 {0, 8589934592}, // FLAGS
2728                         },
2729                         outputs: []regMask{
2730                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2731                         },
2732                 },
2733         },
2734         {
2735                 name:   "SETB",
2736                 argLen: 1,
2737                 asm:    x86.ASETCS,
2738                 reg: regInfo{
2739                         inputs: []inputInfo{
2740                                 {0, 8589934592}, // FLAGS
2741                         },
2742                         outputs: []regMask{
2743                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2744                         },
2745                 },
2746         },
2747         {
2748                 name:   "SETBE",
2749                 argLen: 1,
2750                 asm:    x86.ASETLS,
2751                 reg: regInfo{
2752                         inputs: []inputInfo{
2753                                 {0, 8589934592}, // FLAGS
2754                         },
2755                         outputs: []regMask{
2756                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2757                         },
2758                 },
2759         },
2760         {
2761                 name:   "SETA",
2762                 argLen: 1,
2763                 asm:    x86.ASETHI,
2764                 reg: regInfo{
2765                         inputs: []inputInfo{
2766                                 {0, 8589934592}, // FLAGS
2767                         },
2768                         outputs: []regMask{
2769                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2770                         },
2771                 },
2772         },
2773         {
2774                 name:   "SETAE",
2775                 argLen: 1,
2776                 asm:    x86.ASETCC,
2777                 reg: regInfo{
2778                         inputs: []inputInfo{
2779                                 {0, 8589934592}, // FLAGS
2780                         },
2781                         outputs: []regMask{
2782                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2783                         },
2784                 },
2785         },
2786         {
2787                 name:   "SETEQF",
2788                 argLen: 1,
2789                 asm:    x86.ASETEQ,
2790                 reg: regInfo{
2791                         inputs: []inputInfo{
2792                                 {0, 8589934592}, // FLAGS
2793                         },
2794                         clobbers: 8589934593, // AX FLAGS
2795                         outputs: []regMask{
2796                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2797                         },
2798                 },
2799         },
2800         {
2801                 name:   "SETNEF",
2802                 argLen: 1,
2803                 asm:    x86.ASETNE,
2804                 reg: regInfo{
2805                         inputs: []inputInfo{
2806                                 {0, 8589934592}, // FLAGS
2807                         },
2808                         clobbers: 8589934593, // AX FLAGS
2809                         outputs: []regMask{
2810                                 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2811                         },
2812                 },
2813         },
2814         {
2815                 name:   "SETORD",
2816                 argLen: 1,
2817                 asm:    x86.ASETPC,
2818                 reg: regInfo{
2819                         inputs: []inputInfo{
2820                                 {0, 8589934592}, // FLAGS
2821                         },
2822                         outputs: []regMask{
2823                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2824                         },
2825                 },
2826         },
2827         {
2828                 name:   "SETNAN",
2829                 argLen: 1,
2830                 asm:    x86.ASETPS,
2831                 reg: regInfo{
2832                         inputs: []inputInfo{
2833                                 {0, 8589934592}, // FLAGS
2834                         },
2835                         outputs: []regMask{
2836                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2837                         },
2838                 },
2839         },
2840         {
2841                 name:   "SETGF",
2842                 argLen: 1,
2843                 asm:    x86.ASETHI,
2844                 reg: regInfo{
2845                         inputs: []inputInfo{
2846                                 {0, 8589934592}, // FLAGS
2847                         },
2848                         outputs: []regMask{
2849                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2850                         },
2851                 },
2852         },
2853         {
2854                 name:   "SETGEF",
2855                 argLen: 1,
2856                 asm:    x86.ASETCC,
2857                 reg: regInfo{
2858                         inputs: []inputInfo{
2859                                 {0, 8589934592}, // FLAGS
2860                         },
2861                         outputs: []regMask{
2862                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2863                         },
2864                 },
2865         },
2866         {
2867                 name:   "MOVBQSX",
2868                 argLen: 1,
2869                 asm:    x86.AMOVBQSX,
2870                 reg: regInfo{
2871                         inputs: []inputInfo{
2872                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2873                         },
2874                         outputs: []regMask{
2875                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2876                         },
2877                 },
2878         },
2879         {
2880                 name:   "MOVBQZX",
2881                 argLen: 1,
2882                 asm:    x86.AMOVBQZX,
2883                 reg: regInfo{
2884                         inputs: []inputInfo{
2885                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2886                         },
2887                         outputs: []regMask{
2888                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2889                         },
2890                 },
2891         },
2892         {
2893                 name:   "MOVWQSX",
2894                 argLen: 1,
2895                 asm:    x86.AMOVWQSX,
2896                 reg: regInfo{
2897                         inputs: []inputInfo{
2898                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2899                         },
2900                         outputs: []regMask{
2901                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2902                         },
2903                 },
2904         },
2905         {
2906                 name:   "MOVWQZX",
2907                 argLen: 1,
2908                 asm:    x86.AMOVWQZX,
2909                 reg: regInfo{
2910                         inputs: []inputInfo{
2911                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2912                         },
2913                         outputs: []regMask{
2914                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2915                         },
2916                 },
2917         },
2918         {
2919                 name:   "MOVLQSX",
2920                 argLen: 1,
2921                 asm:    x86.AMOVLQSX,
2922                 reg: regInfo{
2923                         inputs: []inputInfo{
2924                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2925                         },
2926                         outputs: []regMask{
2927                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2928                         },
2929                 },
2930         },
2931         {
2932                 name:   "MOVLQZX",
2933                 argLen: 1,
2934                 asm:    x86.AMOVLQZX,
2935                 reg: regInfo{
2936                         inputs: []inputInfo{
2937                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2938                         },
2939                         outputs: []regMask{
2940                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2941                         },
2942                 },
2943         },
2944         {
2945                 name:              "MOVLconst",
2946                 auxType:           auxInt32,
2947                 argLen:            0,
2948                 rematerializeable: true,
2949                 asm:               x86.AMOVL,
2950                 reg: regInfo{
2951                         outputs: []regMask{
2952                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2953                         },
2954                 },
2955         },
2956         {
2957                 name:              "MOVQconst",
2958                 auxType:           auxInt64,
2959                 argLen:            0,
2960                 rematerializeable: true,
2961                 asm:               x86.AMOVQ,
2962                 reg: regInfo{
2963                         outputs: []regMask{
2964                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2965                         },
2966                 },
2967         },
2968         {
2969                 name:   "CVTTSD2SL",
2970                 argLen: 1,
2971                 asm:    x86.ACVTTSD2SL,
2972                 reg: regInfo{
2973                         inputs: []inputInfo{
2974                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
2975                         },
2976                         outputs: []regMask{
2977                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2978                         },
2979                 },
2980         },
2981         {
2982                 name:   "CVTTSD2SQ",
2983                 argLen: 1,
2984                 asm:    x86.ACVTTSD2SQ,
2985                 reg: regInfo{
2986                         inputs: []inputInfo{
2987                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
2988                         },
2989                         outputs: []regMask{
2990                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
2991                         },
2992                 },
2993         },
2994         {
2995                 name:   "CVTTSS2SL",
2996                 argLen: 1,
2997                 asm:    x86.ACVTTSS2SL,
2998                 reg: regInfo{
2999                         inputs: []inputInfo{
3000                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3001                         },
3002                         outputs: []regMask{
3003                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3004                         },
3005                 },
3006         },
3007         {
3008                 name:   "CVTTSS2SQ",
3009                 argLen: 1,
3010                 asm:    x86.ACVTTSS2SQ,
3011                 reg: regInfo{
3012                         inputs: []inputInfo{
3013                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3014                         },
3015                         outputs: []regMask{
3016                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3017                         },
3018                 },
3019         },
3020         {
3021                 name:   "CVTSL2SS",
3022                 argLen: 1,
3023                 asm:    x86.ACVTSL2SS,
3024                 reg: regInfo{
3025                         inputs: []inputInfo{
3026                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3027                         },
3028                         outputs: []regMask{
3029                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3030                         },
3031                 },
3032         },
3033         {
3034                 name:   "CVTSL2SD",
3035                 argLen: 1,
3036                 asm:    x86.ACVTSL2SD,
3037                 reg: regInfo{
3038                         inputs: []inputInfo{
3039                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3040                         },
3041                         outputs: []regMask{
3042                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3043                         },
3044                 },
3045         },
3046         {
3047                 name:   "CVTSQ2SS",
3048                 argLen: 1,
3049                 asm:    x86.ACVTSQ2SS,
3050                 reg: regInfo{
3051                         inputs: []inputInfo{
3052                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3053                         },
3054                         outputs: []regMask{
3055                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3056                         },
3057                 },
3058         },
3059         {
3060                 name:   "CVTSQ2SD",
3061                 argLen: 1,
3062                 asm:    x86.ACVTSQ2SD,
3063                 reg: regInfo{
3064                         inputs: []inputInfo{
3065                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3066                         },
3067                         outputs: []regMask{
3068                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3069                         },
3070                 },
3071         },
3072         {
3073                 name:   "CVTSD2SS",
3074                 argLen: 1,
3075                 asm:    x86.ACVTSD2SS,
3076                 reg: regInfo{
3077                         inputs: []inputInfo{
3078                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3079                         },
3080                         outputs: []regMask{
3081                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3082                         },
3083                 },
3084         },
3085         {
3086                 name:   "CVTSS2SD",
3087                 argLen: 1,
3088                 asm:    x86.ACVTSS2SD,
3089                 reg: regInfo{
3090                         inputs: []inputInfo{
3091                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3092                         },
3093                         outputs: []regMask{
3094                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3095                         },
3096                 },
3097         },
3098         {
3099                 name:         "PXOR",
3100                 argLen:       2,
3101                 commutative:  true,
3102                 resultInArg0: true,
3103                 asm:          x86.APXOR,
3104                 reg: regInfo{
3105                         inputs: []inputInfo{
3106                                 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3107                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3108                         },
3109                         outputs: []regMask{
3110                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3111                         },
3112                 },
3113         },
3114         {
3115                 name:              "LEAQ",
3116                 auxType:           auxSymOff,
3117                 argLen:            1,
3118                 rematerializeable: true,
3119                 reg: regInfo{
3120                         inputs: []inputInfo{
3121                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3122                         },
3123                         outputs: []regMask{
3124                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3125                         },
3126                 },
3127         },
3128         {
3129                 name:    "LEAQ1",
3130                 auxType: auxSymOff,
3131                 argLen:  2,
3132                 reg: regInfo{
3133                         inputs: []inputInfo{
3134                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3135                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3136                         },
3137                         outputs: []regMask{
3138                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3139                         },
3140                 },
3141         },
3142         {
3143                 name:    "LEAQ2",
3144                 auxType: auxSymOff,
3145                 argLen:  2,
3146                 reg: regInfo{
3147                         inputs: []inputInfo{
3148                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3149                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3150                         },
3151                         outputs: []regMask{
3152                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3153                         },
3154                 },
3155         },
3156         {
3157                 name:    "LEAQ4",
3158                 auxType: auxSymOff,
3159                 argLen:  2,
3160                 reg: regInfo{
3161                         inputs: []inputInfo{
3162                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3163                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3164                         },
3165                         outputs: []regMask{
3166                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3167                         },
3168                 },
3169         },
3170         {
3171                 name:    "LEAQ8",
3172                 auxType: auxSymOff,
3173                 argLen:  2,
3174                 reg: regInfo{
3175                         inputs: []inputInfo{
3176                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3177                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3178                         },
3179                         outputs: []regMask{
3180                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3181                         },
3182                 },
3183         },
3184         {
3185                 name:    "MOVBload",
3186                 auxType: auxSymOff,
3187                 argLen:  2,
3188                 asm:     x86.AMOVBLZX,
3189                 reg: regInfo{
3190                         inputs: []inputInfo{
3191                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3192                         },
3193                         outputs: []regMask{
3194                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3195                         },
3196                 },
3197         },
3198         {
3199                 name:    "MOVBQSXload",
3200                 auxType: auxSymOff,
3201                 argLen:  2,
3202                 asm:     x86.AMOVBQSX,
3203                 reg: regInfo{
3204                         inputs: []inputInfo{
3205                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3206                         },
3207                         outputs: []regMask{
3208                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3209                         },
3210                 },
3211         },
3212         {
3213                 name:    "MOVWload",
3214                 auxType: auxSymOff,
3215                 argLen:  2,
3216                 asm:     x86.AMOVWLZX,
3217                 reg: regInfo{
3218                         inputs: []inputInfo{
3219                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3220                         },
3221                         outputs: []regMask{
3222                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3223                         },
3224                 },
3225         },
3226         {
3227                 name:    "MOVWQSXload",
3228                 auxType: auxSymOff,
3229                 argLen:  2,
3230                 asm:     x86.AMOVWQSX,
3231                 reg: regInfo{
3232                         inputs: []inputInfo{
3233                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3234                         },
3235                         outputs: []regMask{
3236                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3237                         },
3238                 },
3239         },
3240         {
3241                 name:    "MOVLload",
3242                 auxType: auxSymOff,
3243                 argLen:  2,
3244                 asm:     x86.AMOVL,
3245                 reg: regInfo{
3246                         inputs: []inputInfo{
3247                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3248                         },
3249                         outputs: []regMask{
3250                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3251                         },
3252                 },
3253         },
3254         {
3255                 name:    "MOVLQSXload",
3256                 auxType: auxSymOff,
3257                 argLen:  2,
3258                 asm:     x86.AMOVLQSX,
3259                 reg: regInfo{
3260                         inputs: []inputInfo{
3261                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3262                         },
3263                         outputs: []regMask{
3264                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3265                         },
3266                 },
3267         },
3268         {
3269                 name:    "MOVQload",
3270                 auxType: auxSymOff,
3271                 argLen:  2,
3272                 asm:     x86.AMOVQ,
3273                 reg: regInfo{
3274                         inputs: []inputInfo{
3275                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3276                         },
3277                         outputs: []regMask{
3278                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3279                         },
3280                 },
3281         },
3282         {
3283                 name:    "MOVBstore",
3284                 auxType: auxSymOff,
3285                 argLen:  3,
3286                 asm:     x86.AMOVB,
3287                 reg: regInfo{
3288                         inputs: []inputInfo{
3289                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3290                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3291                         },
3292                 },
3293         },
3294         {
3295                 name:    "MOVWstore",
3296                 auxType: auxSymOff,
3297                 argLen:  3,
3298                 asm:     x86.AMOVW,
3299                 reg: regInfo{
3300                         inputs: []inputInfo{
3301                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3302                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3303                         },
3304                 },
3305         },
3306         {
3307                 name:    "MOVLstore",
3308                 auxType: auxSymOff,
3309                 argLen:  3,
3310                 asm:     x86.AMOVL,
3311                 reg: regInfo{
3312                         inputs: []inputInfo{
3313                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3314                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3315                         },
3316                 },
3317         },
3318         {
3319                 name:    "MOVQstore",
3320                 auxType: auxSymOff,
3321                 argLen:  3,
3322                 asm:     x86.AMOVQ,
3323                 reg: regInfo{
3324                         inputs: []inputInfo{
3325                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3326                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3327                         },
3328                 },
3329         },
3330         {
3331                 name:    "MOVOload",
3332                 auxType: auxSymOff,
3333                 argLen:  2,
3334                 asm:     x86.AMOVUPS,
3335                 reg: regInfo{
3336                         inputs: []inputInfo{
3337                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3338                         },
3339                         outputs: []regMask{
3340                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3341                         },
3342                 },
3343         },
3344         {
3345                 name:    "MOVOstore",
3346                 auxType: auxSymOff,
3347                 argLen:  3,
3348                 asm:     x86.AMOVUPS,
3349                 reg: regInfo{
3350                         inputs: []inputInfo{
3351                                 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3352                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3353                         },
3354                 },
3355         },
3356         {
3357                 name:    "MOVBloadidx1",
3358                 auxType: auxSymOff,
3359                 argLen:  3,
3360                 asm:     x86.AMOVBLZX,
3361                 reg: regInfo{
3362                         inputs: []inputInfo{
3363                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3364                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3365                         },
3366                         outputs: []regMask{
3367                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3368                         },
3369                 },
3370         },
3371         {
3372                 name:    "MOVWloadidx1",
3373                 auxType: auxSymOff,
3374                 argLen:  3,
3375                 asm:     x86.AMOVWLZX,
3376                 reg: regInfo{
3377                         inputs: []inputInfo{
3378                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3379                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3380                         },
3381                         outputs: []regMask{
3382                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3383                         },
3384                 },
3385         },
3386         {
3387                 name:    "MOVWloadidx2",
3388                 auxType: auxSymOff,
3389                 argLen:  3,
3390                 asm:     x86.AMOVWLZX,
3391                 reg: regInfo{
3392                         inputs: []inputInfo{
3393                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3394                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3395                         },
3396                         outputs: []regMask{
3397                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3398                         },
3399                 },
3400         },
3401         {
3402                 name:    "MOVLloadidx1",
3403                 auxType: auxSymOff,
3404                 argLen:  3,
3405                 asm:     x86.AMOVL,
3406                 reg: regInfo{
3407                         inputs: []inputInfo{
3408                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3409                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3410                         },
3411                         outputs: []regMask{
3412                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3413                         },
3414                 },
3415         },
3416         {
3417                 name:    "MOVLloadidx4",
3418                 auxType: auxSymOff,
3419                 argLen:  3,
3420                 asm:     x86.AMOVL,
3421                 reg: regInfo{
3422                         inputs: []inputInfo{
3423                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3424                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3425                         },
3426                         outputs: []regMask{
3427                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3428                         },
3429                 },
3430         },
3431         {
3432                 name:    "MOVQloadidx1",
3433                 auxType: auxSymOff,
3434                 argLen:  3,
3435                 asm:     x86.AMOVQ,
3436                 reg: regInfo{
3437                         inputs: []inputInfo{
3438                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3439                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3440                         },
3441                         outputs: []regMask{
3442                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3443                         },
3444                 },
3445         },
3446         {
3447                 name:    "MOVQloadidx8",
3448                 auxType: auxSymOff,
3449                 argLen:  3,
3450                 asm:     x86.AMOVQ,
3451                 reg: regInfo{
3452                         inputs: []inputInfo{
3453                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3454                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3455                         },
3456                         outputs: []regMask{
3457                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3458                         },
3459                 },
3460         },
3461         {
3462                 name:    "MOVBstoreidx1",
3463                 auxType: auxSymOff,
3464                 argLen:  4,
3465                 asm:     x86.AMOVB,
3466                 reg: regInfo{
3467                         inputs: []inputInfo{
3468                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3469                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3470                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3471                         },
3472                 },
3473         },
3474         {
3475                 name:    "MOVWstoreidx1",
3476                 auxType: auxSymOff,
3477                 argLen:  4,
3478                 asm:     x86.AMOVW,
3479                 reg: regInfo{
3480                         inputs: []inputInfo{
3481                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3482                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3483                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3484                         },
3485                 },
3486         },
3487         {
3488                 name:    "MOVWstoreidx2",
3489                 auxType: auxSymOff,
3490                 argLen:  4,
3491                 asm:     x86.AMOVW,
3492                 reg: regInfo{
3493                         inputs: []inputInfo{
3494                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3495                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3496                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3497                         },
3498                 },
3499         },
3500         {
3501                 name:    "MOVLstoreidx1",
3502                 auxType: auxSymOff,
3503                 argLen:  4,
3504                 asm:     x86.AMOVL,
3505                 reg: regInfo{
3506                         inputs: []inputInfo{
3507                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3508                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3509                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3510                         },
3511                 },
3512         },
3513         {
3514                 name:    "MOVLstoreidx4",
3515                 auxType: auxSymOff,
3516                 argLen:  4,
3517                 asm:     x86.AMOVL,
3518                 reg: regInfo{
3519                         inputs: []inputInfo{
3520                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3521                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3522                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3523                         },
3524                 },
3525         },
3526         {
3527                 name:    "MOVQstoreidx1",
3528                 auxType: auxSymOff,
3529                 argLen:  4,
3530                 asm:     x86.AMOVQ,
3531                 reg: regInfo{
3532                         inputs: []inputInfo{
3533                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3534                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3535                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3536                         },
3537                 },
3538         },
3539         {
3540                 name:    "MOVQstoreidx8",
3541                 auxType: auxSymOff,
3542                 argLen:  4,
3543                 asm:     x86.AMOVQ,
3544                 reg: regInfo{
3545                         inputs: []inputInfo{
3546                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3547                                 {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3548                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3549                         },
3550                 },
3551         },
3552         {
3553                 name:    "MOVBstoreconst",
3554                 auxType: auxSymValAndOff,
3555                 argLen:  2,
3556                 asm:     x86.AMOVB,
3557                 reg: regInfo{
3558                         inputs: []inputInfo{
3559                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3560                         },
3561                 },
3562         },
3563         {
3564                 name:    "MOVWstoreconst",
3565                 auxType: auxSymValAndOff,
3566                 argLen:  2,
3567                 asm:     x86.AMOVW,
3568                 reg: regInfo{
3569                         inputs: []inputInfo{
3570                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3571                         },
3572                 },
3573         },
3574         {
3575                 name:    "MOVLstoreconst",
3576                 auxType: auxSymValAndOff,
3577                 argLen:  2,
3578                 asm:     x86.AMOVL,
3579                 reg: regInfo{
3580                         inputs: []inputInfo{
3581                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3582                         },
3583                 },
3584         },
3585         {
3586                 name:    "MOVQstoreconst",
3587                 auxType: auxSymValAndOff,
3588                 argLen:  2,
3589                 asm:     x86.AMOVQ,
3590                 reg: regInfo{
3591                         inputs: []inputInfo{
3592                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3593                         },
3594                 },
3595         },
3596         {
3597                 name:    "MOVBstoreconstidx1",
3598                 auxType: auxSymValAndOff,
3599                 argLen:  3,
3600                 asm:     x86.AMOVB,
3601                 reg: regInfo{
3602                         inputs: []inputInfo{
3603                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3604                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3605                         },
3606                 },
3607         },
3608         {
3609                 name:    "MOVWstoreconstidx1",
3610                 auxType: auxSymValAndOff,
3611                 argLen:  3,
3612                 asm:     x86.AMOVW,
3613                 reg: regInfo{
3614                         inputs: []inputInfo{
3615                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3616                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3617                         },
3618                 },
3619         },
3620         {
3621                 name:    "MOVWstoreconstidx2",
3622                 auxType: auxSymValAndOff,
3623                 argLen:  3,
3624                 asm:     x86.AMOVW,
3625                 reg: regInfo{
3626                         inputs: []inputInfo{
3627                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3628                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3629                         },
3630                 },
3631         },
3632         {
3633                 name:    "MOVLstoreconstidx1",
3634                 auxType: auxSymValAndOff,
3635                 argLen:  3,
3636                 asm:     x86.AMOVL,
3637                 reg: regInfo{
3638                         inputs: []inputInfo{
3639                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3640                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3641                         },
3642                 },
3643         },
3644         {
3645                 name:    "MOVLstoreconstidx4",
3646                 auxType: auxSymValAndOff,
3647                 argLen:  3,
3648                 asm:     x86.AMOVL,
3649                 reg: regInfo{
3650                         inputs: []inputInfo{
3651                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3652                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3653                         },
3654                 },
3655         },
3656         {
3657                 name:    "MOVQstoreconstidx1",
3658                 auxType: auxSymValAndOff,
3659                 argLen:  3,
3660                 asm:     x86.AMOVQ,
3661                 reg: regInfo{
3662                         inputs: []inputInfo{
3663                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3664                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3665                         },
3666                 },
3667         },
3668         {
3669                 name:    "MOVQstoreconstidx8",
3670                 auxType: auxSymValAndOff,
3671                 argLen:  3,
3672                 asm:     x86.AMOVQ,
3673                 reg: regInfo{
3674                         inputs: []inputInfo{
3675                                 {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3676                                 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3677                         },
3678                 },
3679         },
3680         {
3681                 name:    "DUFFZERO",
3682                 auxType: auxInt64,
3683                 argLen:  3,
3684                 reg: regInfo{
3685                         inputs: []inputInfo{
3686                                 {0, 128},   // DI
3687                                 {1, 65536}, // X0
3688                         },
3689                         clobbers: 8589934720, // DI FLAGS
3690                 },
3691         },
3692         {
3693                 name:              "MOVOconst",
3694                 auxType:           auxInt128,
3695                 argLen:            0,
3696                 rematerializeable: true,
3697                 reg: regInfo{
3698                         outputs: []regMask{
3699                                 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
3700                         },
3701                 },
3702         },
3703         {
3704                 name:   "REPSTOSQ",
3705                 argLen: 4,
3706                 reg: regInfo{
3707                         inputs: []inputInfo{
3708                                 {0, 128}, // DI
3709                                 {1, 2},   // CX
3710                                 {2, 1},   // AX
3711                         },
3712                         clobbers: 130, // CX DI
3713                 },
3714         },
3715         {
3716                 name:    "CALLstatic",
3717                 auxType: auxSymOff,
3718                 argLen:  1,
3719                 reg: regInfo{
3720                         clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
3721                 },
3722         },
3723         {
3724                 name:    "CALLclosure",
3725                 auxType: auxInt64,
3726                 argLen:  3,
3727                 reg: regInfo{
3728                         inputs: []inputInfo{
3729                                 {1, 4},     // DX
3730                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3731                         },
3732                         clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
3733                 },
3734         },
3735         {
3736                 name:    "CALLdefer",
3737                 auxType: auxInt64,
3738                 argLen:  1,
3739                 reg: regInfo{
3740                         clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
3741                 },
3742         },
3743         {
3744                 name:    "CALLgo",
3745                 auxType: auxInt64,
3746                 argLen:  1,
3747                 reg: regInfo{
3748                         clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
3749                 },
3750         },
3751         {
3752                 name:    "CALLinter",
3753                 auxType: auxInt64,
3754                 argLen:  2,
3755                 reg: regInfo{
3756                         inputs: []inputInfo{
3757                                 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3758                         },
3759                         clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
3760                 },
3761         },
3762         {
3763                 name:    "DUFFCOPY",
3764                 auxType: auxInt64,
3765                 argLen:  3,
3766                 reg: regInfo{
3767                         inputs: []inputInfo{
3768                                 {0, 128}, // DI
3769                                 {1, 64},  // SI
3770                         },
3771                         clobbers: 8590000320, // SI DI X0 FLAGS
3772                 },
3773         },
3774         {
3775                 name:   "REPMOVSQ",
3776                 argLen: 4,
3777                 reg: regInfo{
3778                         inputs: []inputInfo{
3779                                 {0, 128}, // DI
3780                                 {1, 64},  // SI
3781                                 {2, 2},   // CX
3782                         },
3783                         clobbers: 194, // CX SI DI
3784                 },
3785         },
3786         {
3787                 name:   "InvertFlags",
3788                 argLen: 1,
3789                 reg:    regInfo{},
3790         },
3791         {
3792                 name:   "LoweredGetG",
3793                 argLen: 1,
3794                 reg: regInfo{
3795                         outputs: []regMask{
3796                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3797                         },
3798                 },
3799         },
3800         {
3801                 name:   "LoweredGetClosurePtr",
3802                 argLen: 0,
3803                 reg: regInfo{
3804                         outputs: []regMask{
3805                                 4, // DX
3806                         },
3807                 },
3808         },
3809         {
3810                 name:   "LoweredNilCheck",
3811                 argLen: 2,
3812                 reg: regInfo{
3813                         inputs: []inputInfo{
3814                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3815                         },
3816                         clobbers: 8589934592, // FLAGS
3817                 },
3818         },
3819         {
3820                 name:   "MOVQconvert",
3821                 argLen: 2,
3822                 asm:    x86.AMOVQ,
3823                 reg: regInfo{
3824                         inputs: []inputInfo{
3825                                 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3826                         },
3827                         outputs: []regMask{
3828                                 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3829                         },
3830                 },
3831         },
3832         {
3833                 name:   "FlagEQ",
3834                 argLen: 0,
3835                 reg:    regInfo{},
3836         },
3837         {
3838                 name:   "FlagLT_ULT",
3839                 argLen: 0,
3840                 reg:    regInfo{},
3841         },
3842         {
3843                 name:   "FlagLT_UGT",
3844                 argLen: 0,
3845                 reg:    regInfo{},
3846         },
3847         {
3848                 name:   "FlagGT_UGT",
3849                 argLen: 0,
3850                 reg:    regInfo{},
3851         },
3852         {
3853                 name:   "FlagGT_ULT",
3854                 argLen: 0,
3855                 reg:    regInfo{},
3856         },
3857
3858         {
3859                 name:        "ADD",
3860                 argLen:      2,
3861                 commutative: true,
3862                 asm:         arm.AADD,
3863                 reg: regInfo{
3864                         inputs: []inputInfo{
3865                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3866                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3867                         },
3868                         outputs: []regMask{
3869                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3870                         },
3871                 },
3872         },
3873         {
3874                 name:    "ADDconst",
3875                 auxType: auxSymOff,
3876                 argLen:  1,
3877                 asm:     arm.AADD,
3878                 reg: regInfo{
3879                         inputs: []inputInfo{
3880                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
3881                         },
3882                         outputs: []regMask{
3883                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3884                         },
3885                 },
3886         },
3887         {
3888                 name:   "SUB",
3889                 argLen: 2,
3890                 asm:    arm.ASUB,
3891                 reg: regInfo{
3892                         inputs: []inputInfo{
3893                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3894                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3895                         },
3896                         outputs: []regMask{
3897                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3898                         },
3899                 },
3900         },
3901         {
3902                 name:    "SUBconst",
3903                 auxType: auxInt32,
3904                 argLen:  1,
3905                 asm:     arm.ASUB,
3906                 reg: regInfo{
3907                         inputs: []inputInfo{
3908                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3909                         },
3910                         outputs: []regMask{
3911                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3912                         },
3913                 },
3914         },
3915         {
3916                 name:   "RSB",
3917                 argLen: 2,
3918                 asm:    arm.ARSB,
3919                 reg: regInfo{
3920                         inputs: []inputInfo{
3921                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3922                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3923                         },
3924                         outputs: []regMask{
3925                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3926                         },
3927                 },
3928         },
3929         {
3930                 name:    "RSBconst",
3931                 auxType: auxInt32,
3932                 argLen:  1,
3933                 asm:     arm.ARSB,
3934                 reg: regInfo{
3935                         inputs: []inputInfo{
3936                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3937                         },
3938                         outputs: []regMask{
3939                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3940                         },
3941                 },
3942         },
3943         {
3944                 name:        "MUL",
3945                 argLen:      2,
3946                 commutative: true,
3947                 asm:         arm.AMUL,
3948                 reg: regInfo{
3949                         inputs: []inputInfo{
3950                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3951                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3952                         },
3953                         outputs: []regMask{
3954                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3955                         },
3956                 },
3957         },
3958         {
3959                 name:        "HMUL",
3960                 argLen:      2,
3961                 commutative: true,
3962                 asm:         arm.AMULL,
3963                 reg: regInfo{
3964                         inputs: []inputInfo{
3965                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3966                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3967                         },
3968                         outputs: []regMask{
3969                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3970                         },
3971                 },
3972         },
3973         {
3974                 name:        "HMULU",
3975                 argLen:      2,
3976                 commutative: true,
3977                 asm:         arm.AMULLU,
3978                 reg: regInfo{
3979                         inputs: []inputInfo{
3980                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3981                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3982                         },
3983                         outputs: []regMask{
3984                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3985                         },
3986                 },
3987         },
3988         {
3989                 name:        "AND",
3990                 argLen:      2,
3991                 commutative: true,
3992                 asm:         arm.AAND,
3993                 reg: regInfo{
3994                         inputs: []inputInfo{
3995                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3996                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
3997                         },
3998                         outputs: []regMask{
3999                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4000                         },
4001                 },
4002         },
4003         {
4004                 name:    "ANDconst",
4005                 auxType: auxInt32,
4006                 argLen:  1,
4007                 asm:     arm.AAND,
4008                 reg: regInfo{
4009                         inputs: []inputInfo{
4010                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4011                         },
4012                         outputs: []regMask{
4013                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4014                         },
4015                 },
4016         },
4017         {
4018                 name:        "OR",
4019                 argLen:      2,
4020                 commutative: true,
4021                 asm:         arm.AORR,
4022                 reg: regInfo{
4023                         inputs: []inputInfo{
4024                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4025                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4026                         },
4027                         outputs: []regMask{
4028                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4029                         },
4030                 },
4031         },
4032         {
4033                 name:    "ORconst",
4034                 auxType: auxInt32,
4035                 argLen:  1,
4036                 asm:     arm.AORR,
4037                 reg: regInfo{
4038                         inputs: []inputInfo{
4039                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4040                         },
4041                         outputs: []regMask{
4042                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4043                         },
4044                 },
4045         },
4046         {
4047                 name:        "XOR",
4048                 argLen:      2,
4049                 commutative: true,
4050                 asm:         arm.AEOR,
4051                 reg: regInfo{
4052                         inputs: []inputInfo{
4053                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4054                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4055                         },
4056                         outputs: []regMask{
4057                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4058                         },
4059                 },
4060         },
4061         {
4062                 name:    "XORconst",
4063                 auxType: auxInt32,
4064                 argLen:  1,
4065                 asm:     arm.AEOR,
4066                 reg: regInfo{
4067                         inputs: []inputInfo{
4068                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4069                         },
4070                         outputs: []regMask{
4071                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4072                         },
4073                 },
4074         },
4075         {
4076                 name:   "BIC",
4077                 argLen: 2,
4078                 asm:    arm.ABIC,
4079                 reg: regInfo{
4080                         inputs: []inputInfo{
4081                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4082                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4083                         },
4084                         outputs: []regMask{
4085                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4086                         },
4087                 },
4088         },
4089         {
4090                 name:    "BICconst",
4091                 auxType: auxInt32,
4092                 argLen:  1,
4093                 asm:     arm.ABIC,
4094                 reg: regInfo{
4095                         inputs: []inputInfo{
4096                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4097                         },
4098                         outputs: []regMask{
4099                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4100                         },
4101                 },
4102         },
4103         {
4104                 name:   "MVN",
4105                 argLen: 1,
4106                 asm:    arm.AMVN,
4107                 reg: regInfo{
4108                         inputs: []inputInfo{
4109                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4110                         },
4111                         outputs: []regMask{
4112                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4113                         },
4114                 },
4115         },
4116         {
4117                 name:   "SLL",
4118                 argLen: 2,
4119                 asm:    arm.ASLL,
4120                 reg: regInfo{
4121                         inputs: []inputInfo{
4122                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4123                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4124                         },
4125                         clobbers: 65536, // FLAGS
4126                         outputs: []regMask{
4127                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4128                         },
4129                 },
4130         },
4131         {
4132                 name:    "SLLconst",
4133                 auxType: auxInt32,
4134                 argLen:  1,
4135                 asm:     arm.ASLL,
4136                 reg: regInfo{
4137                         inputs: []inputInfo{
4138                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4139                         },
4140                         outputs: []regMask{
4141                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4142                         },
4143                 },
4144         },
4145         {
4146                 name:   "SRL",
4147                 argLen: 2,
4148                 asm:    arm.ASRL,
4149                 reg: regInfo{
4150                         inputs: []inputInfo{
4151                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4152                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4153                         },
4154                         clobbers: 65536, // FLAGS
4155                         outputs: []regMask{
4156                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4157                         },
4158                 },
4159         },
4160         {
4161                 name:    "SRLconst",
4162                 auxType: auxInt32,
4163                 argLen:  1,
4164                 asm:     arm.ASRL,
4165                 reg: regInfo{
4166                         inputs: []inputInfo{
4167                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4168                         },
4169                         outputs: []regMask{
4170                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4171                         },
4172                 },
4173         },
4174         {
4175                 name:   "SRA",
4176                 argLen: 2,
4177                 asm:    arm.ASRA,
4178                 reg: regInfo{
4179                         inputs: []inputInfo{
4180                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4181                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4182                         },
4183                         clobbers: 65536, // FLAGS
4184                         outputs: []regMask{
4185                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4186                         },
4187                 },
4188         },
4189         {
4190                 name:    "SRAconst",
4191                 auxType: auxInt32,
4192                 argLen:  1,
4193                 asm:     arm.ASRA,
4194                 reg: regInfo{
4195                         inputs: []inputInfo{
4196                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4197                         },
4198                         outputs: []regMask{
4199                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4200                         },
4201                 },
4202         },
4203         {
4204                 name:   "CMP",
4205                 argLen: 2,
4206                 asm:    arm.ACMP,
4207                 reg: regInfo{
4208                         inputs: []inputInfo{
4209                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4210                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4211                         },
4212                         outputs: []regMask{
4213                                 65536, // FLAGS
4214                         },
4215                 },
4216         },
4217         {
4218                 name:    "CMPconst",
4219                 auxType: auxInt32,
4220                 argLen:  1,
4221                 asm:     arm.ACMP,
4222                 reg: regInfo{
4223                         inputs: []inputInfo{
4224                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4225                         },
4226                         outputs: []regMask{
4227                                 65536, // FLAGS
4228                         },
4229                 },
4230         },
4231         {
4232                 name:   "CMN",
4233                 argLen: 2,
4234                 asm:    arm.ACMN,
4235                 reg: regInfo{
4236                         inputs: []inputInfo{
4237                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4238                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4239                         },
4240                         outputs: []regMask{
4241                                 65536, // FLAGS
4242                         },
4243                 },
4244         },
4245         {
4246                 name:    "CMNconst",
4247                 auxType: auxInt32,
4248                 argLen:  1,
4249                 asm:     arm.ACMN,
4250                 reg: regInfo{
4251                         inputs: []inputInfo{
4252                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4253                         },
4254                         outputs: []regMask{
4255                                 65536, // FLAGS
4256                         },
4257                 },
4258         },
4259         {
4260                 name:        "TST",
4261                 argLen:      2,
4262                 commutative: true,
4263                 asm:         arm.ATST,
4264                 reg: regInfo{
4265                         inputs: []inputInfo{
4266                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4267                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4268                         },
4269                         outputs: []regMask{
4270                                 65536, // FLAGS
4271                         },
4272                 },
4273         },
4274         {
4275                 name:    "TSTconst",
4276                 auxType: auxInt32,
4277                 argLen:  1,
4278                 asm:     arm.ATST,
4279                 reg: regInfo{
4280                         inputs: []inputInfo{
4281                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4282                         },
4283                         outputs: []regMask{
4284                                 65536, // FLAGS
4285                         },
4286                 },
4287         },
4288         {
4289                 name:        "TEQ",
4290                 argLen:      2,
4291                 commutative: true,
4292                 asm:         arm.ATEQ,
4293                 reg: regInfo{
4294                         inputs: []inputInfo{
4295                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4296                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4297                         },
4298                         outputs: []regMask{
4299                                 65536, // FLAGS
4300                         },
4301                 },
4302         },
4303         {
4304                 name:    "TEQconst",
4305                 auxType: auxInt32,
4306                 argLen:  1,
4307                 asm:     arm.ATEQ,
4308                 reg: regInfo{
4309                         inputs: []inputInfo{
4310                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4311                         },
4312                         outputs: []regMask{
4313                                 65536, // FLAGS
4314                         },
4315                 },
4316         },
4317         {
4318                 name:              "MOVWconst",
4319                 auxType:           auxInt32,
4320                 argLen:            0,
4321                 rematerializeable: true,
4322                 asm:               arm.AMOVW,
4323                 reg: regInfo{
4324                         outputs: []regMask{
4325                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4326                         },
4327                 },
4328         },
4329         {
4330                 name:    "MOVBload",
4331                 auxType: auxSymOff,
4332                 argLen:  2,
4333                 asm:     arm.AMOVB,
4334                 reg: regInfo{
4335                         inputs: []inputInfo{
4336                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4337                         },
4338                         outputs: []regMask{
4339                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4340                         },
4341                 },
4342         },
4343         {
4344                 name:    "MOVBUload",
4345                 auxType: auxSymOff,
4346                 argLen:  2,
4347                 asm:     arm.AMOVBU,
4348                 reg: regInfo{
4349                         inputs: []inputInfo{
4350                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4351                         },
4352                         outputs: []regMask{
4353                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4354                         },
4355                 },
4356         },
4357         {
4358                 name:    "MOVHload",
4359                 auxType: auxSymOff,
4360                 argLen:  2,
4361                 asm:     arm.AMOVH,
4362                 reg: regInfo{
4363                         inputs: []inputInfo{
4364                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4365                         },
4366                         outputs: []regMask{
4367                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4368                         },
4369                 },
4370         },
4371         {
4372                 name:    "MOVHUload",
4373                 auxType: auxSymOff,
4374                 argLen:  2,
4375                 asm:     arm.AMOVHU,
4376                 reg: regInfo{
4377                         inputs: []inputInfo{
4378                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4379                         },
4380                         outputs: []regMask{
4381                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4382                         },
4383                 },
4384         },
4385         {
4386                 name:    "MOVWload",
4387                 auxType: auxSymOff,
4388                 argLen:  2,
4389                 asm:     arm.AMOVW,
4390                 reg: regInfo{
4391                         inputs: []inputInfo{
4392                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4393                         },
4394                         outputs: []regMask{
4395                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4396                         },
4397                 },
4398         },
4399         {
4400                 name:    "MOVBstore",
4401                 auxType: auxSymOff,
4402                 argLen:  3,
4403                 asm:     arm.AMOVB,
4404                 reg: regInfo{
4405                         inputs: []inputInfo{
4406                                 {1, 5119},   // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4407                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4408                         },
4409                 },
4410         },
4411         {
4412                 name:    "MOVHstore",
4413                 auxType: auxSymOff,
4414                 argLen:  3,
4415                 asm:     arm.AMOVH,
4416                 reg: regInfo{
4417                         inputs: []inputInfo{
4418                                 {1, 5119},   // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4419                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4420                         },
4421                 },
4422         },
4423         {
4424                 name:    "MOVWstore",
4425                 auxType: auxSymOff,
4426                 argLen:  3,
4427                 asm:     arm.AMOVW,
4428                 reg: regInfo{
4429                         inputs: []inputInfo{
4430                                 {1, 5119},   // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4431                                 {0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
4432                         },
4433                 },
4434         },
4435         {
4436                 name:   "MOVBreg",
4437                 argLen: 1,
4438                 asm:    arm.AMOVBS,
4439                 reg: regInfo{
4440                         inputs: []inputInfo{
4441                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4442                         },
4443                         outputs: []regMask{
4444                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4445                         },
4446                 },
4447         },
4448         {
4449                 name:   "MOVBUreg",
4450                 argLen: 1,
4451                 asm:    arm.AMOVBU,
4452                 reg: regInfo{
4453                         inputs: []inputInfo{
4454                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4455                         },
4456                         outputs: []regMask{
4457                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4458                         },
4459                 },
4460         },
4461         {
4462                 name:   "MOVHreg",
4463                 argLen: 1,
4464                 asm:    arm.AMOVHS,
4465                 reg: regInfo{
4466                         inputs: []inputInfo{
4467                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4468                         },
4469                         outputs: []regMask{
4470                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4471                         },
4472                 },
4473         },
4474         {
4475                 name:   "MOVHUreg",
4476                 argLen: 1,
4477                 asm:    arm.AMOVHU,
4478                 reg: regInfo{
4479                         inputs: []inputInfo{
4480                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4481                         },
4482                         outputs: []regMask{
4483                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4484                         },
4485                 },
4486         },
4487         {
4488                 name:    "CALLstatic",
4489                 auxType: auxSymOff,
4490                 argLen:  1,
4491                 reg: regInfo{
4492                         clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4493                 },
4494         },
4495         {
4496                 name:    "CALLclosure",
4497                 auxType: auxInt64,
4498                 argLen:  3,
4499                 reg: regInfo{
4500                         inputs: []inputInfo{
4501                                 {1, 128},   // R7
4502                                 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
4503                         },
4504                         clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4505                 },
4506         },
4507         {
4508                 name:    "CALLdefer",
4509                 auxType: auxInt64,
4510                 argLen:  1,
4511                 reg: regInfo{
4512                         clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4513                 },
4514         },
4515         {
4516                 name:    "CALLgo",
4517                 auxType: auxInt64,
4518                 argLen:  1,
4519                 reg: regInfo{
4520                         clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4521                 },
4522         },
4523         {
4524                 name:    "CALLinter",
4525                 auxType: auxInt64,
4526                 argLen:  2,
4527                 reg: regInfo{
4528                         inputs: []inputInfo{
4529                                 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4530                         },
4531                         clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4532                 },
4533         },
4534         {
4535                 name:   "LoweredNilCheck",
4536                 argLen: 2,
4537                 reg: regInfo{
4538                         inputs: []inputInfo{
4539                                 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
4540                         },
4541                         clobbers: 65536, // FLAGS
4542                 },
4543         },
4544         {
4545                 name:   "Equal",
4546                 argLen: 1,
4547                 reg: regInfo{
4548                         inputs: []inputInfo{
4549                                 {0, 65536}, // FLAGS
4550                         },
4551                         outputs: []regMask{
4552                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4553                         },
4554                 },
4555         },
4556         {
4557                 name:   "NotEqual",
4558                 argLen: 1,
4559                 reg: regInfo{
4560                         inputs: []inputInfo{
4561                                 {0, 65536}, // FLAGS
4562                         },
4563                         outputs: []regMask{
4564                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4565                         },
4566                 },
4567         },
4568         {
4569                 name:   "LessThan",
4570                 argLen: 1,
4571                 reg: regInfo{
4572                         inputs: []inputInfo{
4573                                 {0, 65536}, // FLAGS
4574                         },
4575                         outputs: []regMask{
4576                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4577                         },
4578                 },
4579         },
4580         {
4581                 name:   "LessEqual",
4582                 argLen: 1,
4583                 reg: regInfo{
4584                         inputs: []inputInfo{
4585                                 {0, 65536}, // FLAGS
4586                         },
4587                         outputs: []regMask{
4588                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4589                         },
4590                 },
4591         },
4592         {
4593                 name:   "GreaterThan",
4594                 argLen: 1,
4595                 reg: regInfo{
4596                         inputs: []inputInfo{
4597                                 {0, 65536}, // FLAGS
4598                         },
4599                         outputs: []regMask{
4600                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4601                         },
4602                 },
4603         },
4604         {
4605                 name:   "GreaterEqual",
4606                 argLen: 1,
4607                 reg: regInfo{
4608                         inputs: []inputInfo{
4609                                 {0, 65536}, // FLAGS
4610                         },
4611                         outputs: []regMask{
4612                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4613                         },
4614                 },
4615         },
4616         {
4617                 name:   "LessThanU",
4618                 argLen: 1,
4619                 reg: regInfo{
4620                         inputs: []inputInfo{
4621                                 {0, 65536}, // FLAGS
4622                         },
4623                         outputs: []regMask{
4624                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4625                         },
4626                 },
4627         },
4628         {
4629                 name:   "LessEqualU",
4630                 argLen: 1,
4631                 reg: regInfo{
4632                         inputs: []inputInfo{
4633                                 {0, 65536}, // FLAGS
4634                         },
4635                         outputs: []regMask{
4636                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4637                         },
4638                 },
4639         },
4640         {
4641                 name:   "GreaterThanU",
4642                 argLen: 1,
4643                 reg: regInfo{
4644                         inputs: []inputInfo{
4645                                 {0, 65536}, // FLAGS
4646                         },
4647                         outputs: []regMask{
4648                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4649                         },
4650                 },
4651         },
4652         {
4653                 name:   "GreaterEqualU",
4654                 argLen: 1,
4655                 reg: regInfo{
4656                         inputs: []inputInfo{
4657                                 {0, 65536}, // FLAGS
4658                         },
4659                         outputs: []regMask{
4660                                 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4661                         },
4662                 },
4663         },
4664         {
4665                 name:    "DUFFZERO",
4666                 auxType: auxInt64,
4667                 argLen:  3,
4668                 reg: regInfo{
4669                         inputs: []inputInfo{
4670                                 {0, 2}, // R1
4671                                 {1, 1}, // R0
4672                         },
4673                         clobbers: 2, // R1
4674                 },
4675         },
4676         {
4677                 name:    "DUFFCOPY",
4678                 auxType: auxInt64,
4679                 argLen:  3,
4680                 reg: regInfo{
4681                         inputs: []inputInfo{
4682                                 {0, 4}, // R2
4683                                 {1, 2}, // R1
4684                         },
4685                         clobbers: 7, // R0 R1 R2
4686                 },
4687         },
4688         {
4689                 name:   "LoweredZero",
4690                 argLen: 4,
4691                 reg: regInfo{
4692                         inputs: []inputInfo{
4693                                 {0, 2},    // R1
4694                                 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4695                                 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4696                         },
4697                         clobbers: 65538, // R1 FLAGS
4698                 },
4699         },
4700         {
4701                 name:   "LoweredMove",
4702                 argLen: 4,
4703                 reg: regInfo{
4704                         inputs: []inputInfo{
4705                                 {0, 4},    // R2
4706                                 {1, 2},    // R1
4707                                 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
4708                         },
4709                         clobbers: 65542, // R1 R2 FLAGS
4710                 },
4711         },
4712
4713         {
4714                 name:        "Add8",
4715                 argLen:      2,
4716                 commutative: true,
4717                 generic:     true,
4718         },
4719         {
4720                 name:        "Add16",
4721                 argLen:      2,
4722                 commutative: true,
4723                 generic:     true,
4724         },
4725         {
4726                 name:        "Add32",
4727                 argLen:      2,
4728                 commutative: true,
4729                 generic:     true,
4730         },
4731         {
4732                 name:        "Add64",
4733                 argLen:      2,
4734                 commutative: true,
4735                 generic:     true,
4736         },
4737         {
4738                 name:    "AddPtr",
4739                 argLen:  2,
4740                 generic: true,
4741         },
4742         {
4743                 name:    "Add32F",
4744                 argLen:  2,
4745                 generic: true,
4746         },
4747         {
4748                 name:    "Add64F",
4749                 argLen:  2,
4750                 generic: true,
4751         },
4752         {
4753                 name:    "Sub8",
4754                 argLen:  2,
4755                 generic: true,
4756         },
4757         {
4758                 name:    "Sub16",
4759                 argLen:  2,
4760                 generic: true,
4761         },
4762         {
4763                 name:    "Sub32",
4764                 argLen:  2,
4765                 generic: true,
4766         },
4767         {
4768                 name:    "Sub64",
4769                 argLen:  2,
4770                 generic: true,
4771         },
4772         {
4773                 name:    "SubPtr",
4774                 argLen:  2,
4775                 generic: true,
4776         },
4777         {
4778                 name:    "Sub32F",
4779                 argLen:  2,
4780                 generic: true,
4781         },
4782         {
4783                 name:    "Sub64F",
4784                 argLen:  2,
4785                 generic: true,
4786         },
4787         {
4788                 name:        "Mul8",
4789                 argLen:      2,
4790                 commutative: true,
4791                 generic:     true,
4792         },
4793         {
4794                 name:        "Mul16",
4795                 argLen:      2,
4796                 commutative: true,
4797                 generic:     true,
4798         },
4799         {
4800                 name:        "Mul32",
4801                 argLen:      2,
4802                 commutative: true,
4803                 generic:     true,
4804         },
4805         {
4806                 name:        "Mul64",
4807                 argLen:      2,
4808                 commutative: true,
4809                 generic:     true,
4810         },
4811         {
4812                 name:    "Mul32F",
4813                 argLen:  2,
4814                 generic: true,
4815         },
4816         {
4817                 name:    "Mul64F",
4818                 argLen:  2,
4819                 generic: true,
4820         },
4821         {
4822                 name:    "Div32F",
4823                 argLen:  2,
4824                 generic: true,
4825         },
4826         {
4827                 name:    "Div64F",
4828                 argLen:  2,
4829                 generic: true,
4830         },
4831         {
4832                 name:    "Hmul8",
4833                 argLen:  2,
4834                 generic: true,
4835         },
4836         {
4837                 name:    "Hmul8u",
4838                 argLen:  2,
4839                 generic: true,
4840         },
4841         {
4842                 name:    "Hmul16",
4843                 argLen:  2,
4844                 generic: true,
4845         },
4846         {
4847                 name:    "Hmul16u",
4848                 argLen:  2,
4849                 generic: true,
4850         },
4851         {
4852                 name:    "Hmul32",
4853                 argLen:  2,
4854                 generic: true,
4855         },
4856         {
4857                 name:    "Hmul32u",
4858                 argLen:  2,
4859                 generic: true,
4860         },
4861         {
4862                 name:    "Hmul64",
4863                 argLen:  2,
4864                 generic: true,
4865         },
4866         {
4867                 name:    "Hmul64u",
4868                 argLen:  2,
4869                 generic: true,
4870         },
4871         {
4872                 name:    "Avg64u",
4873                 argLen:  2,
4874                 generic: true,
4875         },
4876         {
4877                 name:    "Div8",
4878                 argLen:  2,
4879                 generic: true,
4880         },
4881         {
4882                 name:    "Div8u",
4883                 argLen:  2,
4884                 generic: true,
4885         },
4886         {
4887                 name:    "Div16",
4888                 argLen:  2,
4889                 generic: true,
4890         },
4891         {
4892                 name:    "Div16u",
4893                 argLen:  2,
4894                 generic: true,
4895         },
4896         {
4897                 name:    "Div32",
4898                 argLen:  2,
4899                 generic: true,
4900         },
4901         {
4902                 name:    "Div32u",
4903                 argLen:  2,
4904                 generic: true,
4905         },
4906         {
4907                 name:    "Div64",
4908                 argLen:  2,
4909                 generic: true,
4910         },
4911         {
4912                 name:    "Div64u",
4913                 argLen:  2,
4914                 generic: true,
4915         },
4916         {
4917                 name:    "Mod8",
4918                 argLen:  2,
4919                 generic: true,
4920         },
4921         {
4922                 name:    "Mod8u",
4923                 argLen:  2,
4924                 generic: true,
4925         },
4926         {
4927                 name:    "Mod16",
4928                 argLen:  2,
4929                 generic: true,
4930         },
4931         {
4932                 name:    "Mod16u",
4933                 argLen:  2,
4934                 generic: true,
4935         },
4936         {
4937                 name:    "Mod32",
4938                 argLen:  2,
4939                 generic: true,
4940         },
4941         {
4942                 name:    "Mod32u",
4943                 argLen:  2,
4944                 generic: true,
4945         },
4946         {
4947                 name:    "Mod64",
4948                 argLen:  2,
4949                 generic: true,
4950         },
4951         {
4952                 name:    "Mod64u",
4953                 argLen:  2,
4954                 generic: true,
4955         },
4956         {
4957                 name:        "And8",
4958                 argLen:      2,
4959                 commutative: true,
4960                 generic:     true,
4961         },
4962         {
4963                 name:        "And16",
4964                 argLen:      2,
4965                 commutative: true,
4966                 generic:     true,
4967         },
4968         {
4969                 name:        "And32",
4970                 argLen:      2,
4971                 commutative: true,
4972                 generic:     true,
4973         },
4974         {
4975                 name:        "And64",
4976                 argLen:      2,
4977                 commutative: true,
4978                 generic:     true,
4979         },
4980         {
4981                 name:        "Or8",
4982                 argLen:      2,
4983                 commutative: true,
4984                 generic:     true,
4985         },
4986         {
4987                 name:        "Or16",
4988                 argLen:      2,
4989                 commutative: true,
4990                 generic:     true,
4991         },
4992         {
4993                 name:        "Or32",
4994                 argLen:      2,
4995                 commutative: true,
4996                 generic:     true,
4997         },
4998         {
4999                 name:        "Or64",
5000                 argLen:      2,
5001                 commutative: true,
5002                 generic:     true,
5003         },
5004         {
5005                 name:        "Xor8",
5006                 argLen:      2,
5007                 commutative: true,
5008                 generic:     true,
5009         },
5010         {
5011                 name:        "Xor16",
5012                 argLen:      2,
5013                 commutative: true,
5014                 generic:     true,
5015         },
5016         {
5017                 name:        "Xor32",
5018                 argLen:      2,
5019                 commutative: true,
5020                 generic:     true,
5021         },
5022         {
5023                 name:        "Xor64",
5024                 argLen:      2,
5025                 commutative: true,
5026                 generic:     true,
5027         },
5028         {
5029                 name:    "Lsh8x8",
5030                 argLen:  2,
5031                 generic: true,
5032         },
5033         {
5034                 name:    "Lsh8x16",
5035                 argLen:  2,
5036                 generic: true,
5037         },
5038         {
5039                 name:    "Lsh8x32",
5040                 argLen:  2,
5041                 generic: true,
5042         },
5043         {
5044                 name:    "Lsh8x64",
5045                 argLen:  2,
5046                 generic: true,
5047         },
5048         {
5049                 name:    "Lsh16x8",
5050                 argLen:  2,
5051                 generic: true,
5052         },
5053         {
5054                 name:    "Lsh16x16",
5055                 argLen:  2,
5056                 generic: true,
5057         },
5058         {
5059                 name:    "Lsh16x32",
5060                 argLen:  2,
5061                 generic: true,
5062         },
5063         {
5064                 name:    "Lsh16x64",
5065                 argLen:  2,
5066                 generic: true,
5067         },
5068         {
5069                 name:    "Lsh32x8",
5070                 argLen:  2,
5071                 generic: true,
5072         },
5073         {
5074                 name:    "Lsh32x16",
5075                 argLen:  2,
5076                 generic: true,
5077         },
5078         {
5079                 name:    "Lsh32x32",
5080                 argLen:  2,
5081                 generic: true,
5082         },
5083         {
5084                 name:    "Lsh32x64",
5085                 argLen:  2,
5086                 generic: true,
5087         },
5088         {
5089                 name:    "Lsh64x8",
5090                 argLen:  2,
5091                 generic: true,
5092         },
5093         {
5094                 name:    "Lsh64x16",
5095                 argLen:  2,
5096                 generic: true,
5097         },
5098         {
5099                 name:    "Lsh64x32",
5100                 argLen:  2,
5101                 generic: true,
5102         },
5103         {
5104                 name:    "Lsh64x64",
5105                 argLen:  2,
5106                 generic: true,
5107         },
5108         {
5109                 name:    "Rsh8x8",
5110                 argLen:  2,
5111                 generic: true,
5112         },
5113         {
5114                 name:    "Rsh8x16",
5115                 argLen:  2,
5116                 generic: true,
5117         },
5118         {
5119                 name:    "Rsh8x32",
5120                 argLen:  2,
5121                 generic: true,
5122         },
5123         {
5124                 name:    "Rsh8x64",
5125                 argLen:  2,
5126                 generic: true,
5127         },
5128         {
5129                 name:    "Rsh16x8",
5130                 argLen:  2,
5131                 generic: true,
5132         },
5133         {
5134                 name:    "Rsh16x16",
5135                 argLen:  2,
5136                 generic: true,
5137         },
5138         {
5139                 name:    "Rsh16x32",
5140                 argLen:  2,
5141                 generic: true,
5142         },
5143         {
5144                 name:    "Rsh16x64",
5145                 argLen:  2,
5146                 generic: true,
5147         },
5148         {
5149                 name:    "Rsh32x8",
5150                 argLen:  2,
5151                 generic: true,
5152         },
5153         {
5154                 name:    "Rsh32x16",
5155                 argLen:  2,
5156                 generic: true,
5157         },
5158         {
5159                 name:    "Rsh32x32",
5160                 argLen:  2,
5161                 generic: true,
5162         },
5163         {
5164                 name:    "Rsh32x64",
5165                 argLen:  2,
5166                 generic: true,
5167         },
5168         {
5169                 name:    "Rsh64x8",
5170                 argLen:  2,
5171                 generic: true,
5172         },
5173         {
5174                 name:    "Rsh64x16",
5175                 argLen:  2,
5176                 generic: true,
5177         },
5178         {
5179                 name:    "Rsh64x32",
5180                 argLen:  2,
5181                 generic: true,
5182         },
5183         {
5184                 name:    "Rsh64x64",
5185                 argLen:  2,
5186                 generic: true,
5187         },
5188         {
5189                 name:    "Rsh8Ux8",
5190                 argLen:  2,
5191                 generic: true,
5192         },
5193         {
5194                 name:    "Rsh8Ux16",
5195                 argLen:  2,
5196                 generic: true,
5197         },
5198         {
5199                 name:    "Rsh8Ux32",
5200                 argLen:  2,
5201                 generic: true,
5202         },
5203         {
5204                 name:    "Rsh8Ux64",
5205                 argLen:  2,
5206                 generic: true,
5207         },
5208         {
5209                 name:    "Rsh16Ux8",
5210                 argLen:  2,
5211                 generic: true,
5212         },
5213         {
5214                 name:    "Rsh16Ux16",
5215                 argLen:  2,
5216                 generic: true,
5217         },
5218         {
5219                 name:    "Rsh16Ux32",
5220                 argLen:  2,
5221                 generic: true,
5222         },
5223         {
5224                 name:    "Rsh16Ux64",
5225                 argLen:  2,
5226                 generic: true,
5227         },
5228         {
5229                 name:    "Rsh32Ux8",
5230                 argLen:  2,
5231                 generic: true,
5232         },
5233         {
5234                 name:    "Rsh32Ux16",
5235                 argLen:  2,
5236                 generic: true,
5237         },
5238         {
5239                 name:    "Rsh32Ux32",
5240                 argLen:  2,
5241                 generic: true,
5242         },
5243         {
5244                 name:    "Rsh32Ux64",
5245                 argLen:  2,
5246                 generic: true,
5247         },
5248         {
5249                 name:    "Rsh64Ux8",
5250                 argLen:  2,
5251                 generic: true,
5252         },
5253         {
5254                 name:    "Rsh64Ux16",
5255                 argLen:  2,
5256                 generic: true,
5257         },
5258         {
5259                 name:    "Rsh64Ux32",
5260                 argLen:  2,
5261                 generic: true,
5262         },
5263         {
5264                 name:    "Rsh64Ux64",
5265                 argLen:  2,
5266                 generic: true,
5267         },
5268         {
5269                 name:    "Lrot8",
5270                 auxType: auxInt64,
5271                 argLen:  1,
5272                 generic: true,
5273         },
5274         {
5275                 name:    "Lrot16",
5276                 auxType: auxInt64,
5277                 argLen:  1,
5278                 generic: true,
5279         },
5280         {
5281                 name:    "Lrot32",
5282                 auxType: auxInt64,
5283                 argLen:  1,
5284                 generic: true,
5285         },
5286         {
5287                 name:    "Lrot64",
5288                 auxType: auxInt64,
5289                 argLen:  1,
5290                 generic: true,
5291         },
5292         {
5293                 name:        "Eq8",
5294                 argLen:      2,
5295                 commutative: true,
5296                 generic:     true,
5297         },
5298         {
5299                 name:        "Eq16",
5300                 argLen:      2,
5301                 commutative: true,
5302                 generic:     true,
5303         },
5304         {
5305                 name:        "Eq32",
5306                 argLen:      2,
5307                 commutative: true,
5308                 generic:     true,
5309         },
5310         {
5311                 name:        "Eq64",
5312                 argLen:      2,
5313                 commutative: true,
5314                 generic:     true,
5315         },
5316         {
5317                 name:        "EqPtr",
5318                 argLen:      2,
5319                 commutative: true,
5320                 generic:     true,
5321         },
5322         {
5323                 name:    "EqInter",
5324                 argLen:  2,
5325                 generic: true,
5326         },
5327         {
5328                 name:    "EqSlice",
5329                 argLen:  2,
5330                 generic: true,
5331         },
5332         {
5333                 name:    "Eq32F",
5334                 argLen:  2,
5335                 generic: true,
5336         },
5337         {
5338                 name:    "Eq64F",
5339                 argLen:  2,
5340                 generic: true,
5341         },
5342         {
5343                 name:        "Neq8",
5344                 argLen:      2,
5345                 commutative: true,
5346                 generic:     true,
5347         },
5348         {
5349                 name:        "Neq16",
5350                 argLen:      2,
5351                 commutative: true,
5352                 generic:     true,
5353         },
5354         {
5355                 name:        "Neq32",
5356                 argLen:      2,
5357                 commutative: true,
5358                 generic:     true,
5359         },
5360         {
5361                 name:        "Neq64",
5362                 argLen:      2,
5363                 commutative: true,
5364                 generic:     true,
5365         },
5366         {
5367                 name:        "NeqPtr",
5368                 argLen:      2,
5369                 commutative: true,
5370                 generic:     true,
5371         },
5372         {
5373                 name:    "NeqInter",
5374                 argLen:  2,
5375                 generic: true,
5376         },
5377         {
5378                 name:    "NeqSlice",
5379                 argLen:  2,
5380                 generic: true,
5381         },
5382         {
5383                 name:    "Neq32F",
5384                 argLen:  2,
5385                 generic: true,
5386         },
5387         {
5388                 name:    "Neq64F",
5389                 argLen:  2,
5390                 generic: true,
5391         },
5392         {
5393                 name:    "Less8",
5394                 argLen:  2,
5395                 generic: true,
5396         },
5397         {
5398                 name:    "Less8U",
5399                 argLen:  2,
5400                 generic: true,
5401         },
5402         {
5403                 name:    "Less16",
5404                 argLen:  2,
5405                 generic: true,
5406         },
5407         {
5408                 name:    "Less16U",
5409                 argLen:  2,
5410                 generic: true,
5411         },
5412         {
5413                 name:    "Less32",
5414                 argLen:  2,
5415                 generic: true,
5416         },
5417         {
5418                 name:    "Less32U",
5419                 argLen:  2,
5420                 generic: true,
5421         },
5422         {
5423                 name:    "Less64",
5424                 argLen:  2,
5425                 generic: true,
5426         },
5427         {
5428                 name:    "Less64U",
5429                 argLen:  2,
5430                 generic: true,
5431         },
5432         {
5433                 name:    "Less32F",
5434                 argLen:  2,
5435                 generic: true,
5436         },
5437         {
5438                 name:    "Less64F",
5439                 argLen:  2,
5440                 generic: true,
5441         },
5442         {
5443                 name:    "Leq8",
5444                 argLen:  2,
5445                 generic: true,
5446         },
5447         {
5448                 name:    "Leq8U",
5449                 argLen:  2,
5450                 generic: true,
5451         },
5452         {
5453                 name:    "Leq16",
5454                 argLen:  2,
5455                 generic: true,
5456         },
5457         {
5458                 name:    "Leq16U",
5459                 argLen:  2,
5460                 generic: true,
5461         },
5462         {
5463                 name:    "Leq32",
5464                 argLen:  2,
5465                 generic: true,
5466         },
5467         {
5468                 name:    "Leq32U",
5469                 argLen:  2,
5470                 generic: true,
5471         },
5472         {
5473                 name:    "Leq64",
5474                 argLen:  2,
5475                 generic: true,
5476         },
5477         {
5478                 name:    "Leq64U",
5479                 argLen:  2,
5480                 generic: true,
5481         },
5482         {
5483                 name:    "Leq32F",
5484                 argLen:  2,
5485                 generic: true,
5486         },
5487         {
5488                 name:    "Leq64F",
5489                 argLen:  2,
5490                 generic: true,
5491         },
5492         {
5493                 name:    "Greater8",
5494                 argLen:  2,
5495                 generic: true,
5496         },
5497         {
5498                 name:    "Greater8U",
5499                 argLen:  2,
5500                 generic: true,
5501         },
5502         {
5503                 name:    "Greater16",
5504                 argLen:  2,
5505                 generic: true,
5506         },
5507         {
5508                 name:    "Greater16U",
5509                 argLen:  2,
5510                 generic: true,
5511         },
5512         {
5513                 name:    "Greater32",
5514                 argLen:  2,
5515                 generic: true,
5516         },
5517         {
5518                 name:    "Greater32U",
5519                 argLen:  2,
5520                 generic: true,
5521         },
5522         {
5523                 name:    "Greater64",
5524                 argLen:  2,
5525                 generic: true,
5526         },
5527         {
5528                 name:    "Greater64U",
5529                 argLen:  2,
5530                 generic: true,
5531         },
5532         {
5533                 name:    "Greater32F",
5534                 argLen:  2,
5535                 generic: true,
5536         },
5537         {
5538                 name:    "Greater64F",
5539                 argLen:  2,
5540                 generic: true,
5541         },
5542         {
5543                 name:    "Geq8",
5544                 argLen:  2,
5545                 generic: true,
5546         },
5547         {
5548                 name:    "Geq8U",
5549                 argLen:  2,
5550                 generic: true,
5551         },
5552         {
5553                 name:    "Geq16",
5554                 argLen:  2,
5555                 generic: true,
5556         },
5557         {
5558                 name:    "Geq16U",
5559                 argLen:  2,
5560                 generic: true,
5561         },
5562         {
5563                 name:    "Geq32",
5564                 argLen:  2,
5565                 generic: true,
5566         },
5567         {
5568                 name:    "Geq32U",
5569                 argLen:  2,
5570                 generic: true,
5571         },
5572         {
5573                 name:    "Geq64",
5574                 argLen:  2,
5575                 generic: true,
5576         },
5577         {
5578                 name:    "Geq64U",
5579                 argLen:  2,
5580                 generic: true,
5581         },
5582         {
5583                 name:    "Geq32F",
5584                 argLen:  2,
5585                 generic: true,
5586         },
5587         {
5588                 name:    "Geq64F",
5589                 argLen:  2,
5590                 generic: true,
5591         },
5592         {
5593                 name:    "AndB",
5594                 argLen:  2,
5595                 generic: true,
5596         },
5597         {
5598                 name:    "OrB",
5599                 argLen:  2,
5600                 generic: true,
5601         },
5602         {
5603                 name:    "EqB",
5604                 argLen:  2,
5605                 generic: true,
5606         },
5607         {
5608                 name:    "NeqB",
5609                 argLen:  2,
5610                 generic: true,
5611         },
5612         {
5613                 name:    "Not",
5614                 argLen:  1,
5615                 generic: true,
5616         },
5617         {
5618                 name:    "Neg8",
5619                 argLen:  1,
5620                 generic: true,
5621         },
5622         {
5623                 name:    "Neg16",
5624                 argLen:  1,
5625                 generic: true,
5626         },
5627         {
5628                 name:    "Neg32",
5629                 argLen:  1,
5630                 generic: true,
5631         },
5632         {
5633                 name:    "Neg64",
5634                 argLen:  1,
5635                 generic: true,
5636         },
5637         {
5638                 name:    "Neg32F",
5639                 argLen:  1,
5640                 generic: true,
5641         },
5642         {
5643                 name:    "Neg64F",
5644                 argLen:  1,
5645                 generic: true,
5646         },
5647         {
5648                 name:    "Com8",
5649                 argLen:  1,
5650                 generic: true,
5651         },
5652         {
5653                 name:    "Com16",
5654                 argLen:  1,
5655                 generic: true,
5656         },
5657         {
5658                 name:    "Com32",
5659                 argLen:  1,
5660                 generic: true,
5661         },
5662         {
5663                 name:    "Com64",
5664                 argLen:  1,
5665                 generic: true,
5666         },
5667         {
5668                 name:    "Ctz16",
5669                 argLen:  1,
5670                 generic: true,
5671         },
5672         {
5673                 name:    "Ctz32",
5674                 argLen:  1,
5675                 generic: true,
5676         },
5677         {
5678                 name:    "Ctz64",
5679                 argLen:  1,
5680                 generic: true,
5681         },
5682         {
5683                 name:    "Clz16",
5684                 argLen:  1,
5685                 generic: true,
5686         },
5687         {
5688                 name:    "Clz32",
5689                 argLen:  1,
5690                 generic: true,
5691         },
5692         {
5693                 name:    "Clz64",
5694                 argLen:  1,
5695                 generic: true,
5696         },
5697         {
5698                 name:    "Bswap32",
5699                 argLen:  1,
5700                 generic: true,
5701         },
5702         {
5703                 name:    "Bswap64",
5704                 argLen:  1,
5705                 generic: true,
5706         },
5707         {
5708                 name:    "Sqrt",
5709                 argLen:  1,
5710                 generic: true,
5711         },
5712         {
5713                 name:    "Phi",
5714                 argLen:  -1,
5715                 generic: true,
5716         },
5717         {
5718                 name:    "Copy",
5719                 argLen:  1,
5720                 generic: true,
5721         },
5722         {
5723                 name:    "Convert",
5724                 argLen:  2,
5725                 generic: true,
5726         },
5727         {
5728                 name:    "ConstBool",
5729                 auxType: auxBool,
5730                 argLen:  0,
5731                 generic: true,
5732         },
5733         {
5734                 name:    "ConstString",
5735                 auxType: auxString,
5736                 argLen:  0,
5737                 generic: true,
5738         },
5739         {
5740                 name:    "ConstNil",
5741                 argLen:  0,
5742                 generic: true,
5743         },
5744         {
5745                 name:    "Const8",
5746                 auxType: auxInt8,
5747                 argLen:  0,
5748                 generic: true,
5749         },
5750         {
5751                 name:    "Const16",
5752                 auxType: auxInt16,
5753                 argLen:  0,
5754                 generic: true,
5755         },
5756         {
5757                 name:    "Const32",
5758                 auxType: auxInt32,
5759                 argLen:  0,
5760                 generic: true,
5761         },
5762         {
5763                 name:    "Const64",
5764                 auxType: auxInt64,
5765                 argLen:  0,
5766                 generic: true,
5767         },
5768         {
5769                 name:    "Const32F",
5770                 auxType: auxFloat32,
5771                 argLen:  0,
5772                 generic: true,
5773         },
5774         {
5775                 name:    "Const64F",
5776                 auxType: auxFloat64,
5777                 argLen:  0,
5778                 generic: true,
5779         },
5780         {
5781                 name:    "ConstInterface",
5782                 argLen:  0,
5783                 generic: true,
5784         },
5785         {
5786                 name:    "ConstSlice",
5787                 argLen:  0,
5788                 generic: true,
5789         },
5790         {
5791                 name:    "InitMem",
5792                 argLen:  0,
5793                 generic: true,
5794         },
5795         {
5796                 name:    "Arg",
5797                 auxType: auxSymOff,
5798                 argLen:  0,
5799                 generic: true,
5800         },
5801         {
5802                 name:    "Addr",
5803                 auxType: auxSym,
5804                 argLen:  1,
5805                 generic: true,
5806         },
5807         {
5808                 name:    "SP",
5809                 argLen:  0,
5810                 generic: true,
5811         },
5812         {
5813                 name:    "SB",
5814                 argLen:  0,
5815                 generic: true,
5816         },
5817         {
5818                 name:    "Func",
5819                 auxType: auxSym,
5820                 argLen:  0,
5821                 generic: true,
5822         },
5823         {
5824                 name:    "Load",
5825                 argLen:  2,
5826                 generic: true,
5827         },
5828         {
5829                 name:    "Store",
5830                 auxType: auxInt64,
5831                 argLen:  3,
5832                 generic: true,
5833         },
5834         {
5835                 name:    "Move",
5836                 auxType: auxInt64,
5837                 argLen:  3,
5838                 generic: true,
5839         },
5840         {
5841                 name:    "Zero",
5842                 auxType: auxInt64,
5843                 argLen:  2,
5844                 generic: true,
5845         },
5846         {
5847                 name:    "ClosureCall",
5848                 auxType: auxInt64,
5849                 argLen:  3,
5850                 generic: true,
5851         },
5852         {
5853                 name:    "StaticCall",
5854                 auxType: auxSymOff,
5855                 argLen:  1,
5856                 generic: true,
5857         },
5858         {
5859                 name:    "DeferCall",
5860                 auxType: auxInt64,
5861                 argLen:  1,
5862                 generic: true,
5863         },
5864         {
5865                 name:    "GoCall",
5866                 auxType: auxInt64,
5867                 argLen:  1,
5868                 generic: true,
5869         },
5870         {
5871                 name:    "InterCall",
5872                 auxType: auxInt64,
5873                 argLen:  2,
5874                 generic: true,
5875         },
5876         {
5877                 name:    "SignExt8to16",
5878                 argLen:  1,
5879                 generic: true,
5880         },
5881         {
5882                 name:    "SignExt8to32",
5883                 argLen:  1,
5884                 generic: true,
5885         },
5886         {
5887                 name:    "SignExt8to64",
5888                 argLen:  1,
5889                 generic: true,
5890         },
5891         {
5892                 name:    "SignExt16to32",
5893                 argLen:  1,
5894                 generic: true,
5895         },
5896         {
5897                 name:    "SignExt16to64",
5898                 argLen:  1,
5899                 generic: true,
5900         },
5901         {
5902                 name:    "SignExt32to64",
5903                 argLen:  1,
5904                 generic: true,
5905         },
5906         {
5907                 name:    "ZeroExt8to16",
5908                 argLen:  1,
5909                 generic: true,
5910         },
5911         {
5912                 name:    "ZeroExt8to32",
5913                 argLen:  1,
5914                 generic: true,
5915         },
5916         {
5917                 name:    "ZeroExt8to64",
5918                 argLen:  1,
5919                 generic: true,
5920         },
5921         {
5922                 name:    "ZeroExt16to32",
5923                 argLen:  1,
5924                 generic: true,
5925         },
5926         {
5927                 name:    "ZeroExt16to64",
5928                 argLen:  1,
5929                 generic: true,
5930         },
5931         {
5932                 name:    "ZeroExt32to64",
5933                 argLen:  1,
5934                 generic: true,
5935         },
5936         {
5937                 name:    "Trunc16to8",
5938                 argLen:  1,
5939                 generic: true,
5940         },
5941         {
5942                 name:    "Trunc32to8",
5943                 argLen:  1,
5944                 generic: true,
5945         },
5946         {
5947                 name:    "Trunc32to16",
5948                 argLen:  1,
5949                 generic: true,
5950         },
5951         {
5952                 name:    "Trunc64to8",
5953                 argLen:  1,
5954                 generic: true,
5955         },
5956         {
5957                 name:    "Trunc64to16",
5958                 argLen:  1,
5959                 generic: true,
5960         },
5961         {
5962                 name:    "Trunc64to32",
5963                 argLen:  1,
5964                 generic: true,
5965         },
5966         {
5967                 name:    "Cvt32to32F",
5968                 argLen:  1,
5969                 generic: true,
5970         },
5971         {
5972                 name:    "Cvt32to64F",
5973                 argLen:  1,
5974                 generic: true,
5975         },
5976         {
5977                 name:    "Cvt64to32F",
5978                 argLen:  1,
5979                 generic: true,
5980         },
5981         {
5982                 name:    "Cvt64to64F",
5983                 argLen:  1,
5984                 generic: true,
5985         },
5986         {
5987                 name:    "Cvt32Fto32",
5988                 argLen:  1,
5989                 generic: true,
5990         },
5991         {
5992                 name:    "Cvt32Fto64",
5993                 argLen:  1,
5994                 generic: true,
5995         },
5996         {
5997                 name:    "Cvt64Fto32",
5998                 argLen:  1,
5999                 generic: true,
6000         },
6001         {
6002                 name:    "Cvt64Fto64",
6003                 argLen:  1,
6004                 generic: true,
6005         },
6006         {
6007                 name:    "Cvt32Fto64F",
6008                 argLen:  1,
6009                 generic: true,
6010         },
6011         {
6012                 name:    "Cvt64Fto32F",
6013                 argLen:  1,
6014                 generic: true,
6015         },
6016         {
6017                 name:    "IsNonNil",
6018                 argLen:  1,
6019                 generic: true,
6020         },
6021         {
6022                 name:    "IsInBounds",
6023                 argLen:  2,
6024                 generic: true,
6025         },
6026         {
6027                 name:    "IsSliceInBounds",
6028                 argLen:  2,
6029                 generic: true,
6030         },
6031         {
6032                 name:    "NilCheck",
6033                 argLen:  2,
6034                 generic: true,
6035         },
6036         {
6037                 name:    "GetG",
6038                 argLen:  1,
6039                 generic: true,
6040         },
6041         {
6042                 name:    "GetClosurePtr",
6043                 argLen:  0,
6044                 generic: true,
6045         },
6046         {
6047                 name:    "ArrayIndex",
6048                 auxType: auxInt64,
6049                 argLen:  1,
6050                 generic: true,
6051         },
6052         {
6053                 name:    "PtrIndex",
6054                 argLen:  2,
6055                 generic: true,
6056         },
6057         {
6058                 name:    "OffPtr",
6059                 auxType: auxInt64,
6060                 argLen:  1,
6061                 generic: true,
6062         },
6063         {
6064                 name:    "SliceMake",
6065                 argLen:  3,
6066                 generic: true,
6067         },
6068         {
6069                 name:    "SlicePtr",
6070                 argLen:  1,
6071                 generic: true,
6072         },
6073         {
6074                 name:    "SliceLen",
6075                 argLen:  1,
6076                 generic: true,
6077         },
6078         {
6079                 name:    "SliceCap",
6080                 argLen:  1,
6081                 generic: true,
6082         },
6083         {
6084                 name:    "ComplexMake",
6085                 argLen:  2,
6086                 generic: true,
6087         },
6088         {
6089                 name:    "ComplexReal",
6090                 argLen:  1,
6091                 generic: true,
6092         },
6093         {
6094                 name:    "ComplexImag",
6095                 argLen:  1,
6096                 generic: true,
6097         },
6098         {
6099                 name:    "StringMake",
6100                 argLen:  2,
6101                 generic: true,
6102         },
6103         {
6104                 name:    "StringPtr",
6105                 argLen:  1,
6106                 generic: true,
6107         },
6108         {
6109                 name:    "StringLen",
6110                 argLen:  1,
6111                 generic: true,
6112         },
6113         {
6114                 name:    "IMake",
6115                 argLen:  2,
6116                 generic: true,
6117         },
6118         {
6119                 name:    "ITab",
6120                 argLen:  1,
6121                 generic: true,
6122         },
6123         {
6124                 name:    "IData",
6125                 argLen:  1,
6126                 generic: true,
6127         },
6128         {
6129                 name:    "StructMake0",
6130                 argLen:  0,
6131                 generic: true,
6132         },
6133         {
6134                 name:    "StructMake1",
6135                 argLen:  1,
6136                 generic: true,
6137         },
6138         {
6139                 name:    "StructMake2",
6140                 argLen:  2,
6141                 generic: true,
6142         },
6143         {
6144                 name:    "StructMake3",
6145                 argLen:  3,
6146                 generic: true,
6147         },
6148         {
6149                 name:    "StructMake4",
6150                 argLen:  4,
6151                 generic: true,
6152         },
6153         {
6154                 name:    "StructSelect",
6155                 auxType: auxInt64,
6156                 argLen:  1,
6157                 generic: true,
6158         },
6159         {
6160                 name:    "StoreReg",
6161                 argLen:  1,
6162                 generic: true,
6163         },
6164         {
6165                 name:    "LoadReg",
6166                 argLen:  1,
6167                 generic: true,
6168         },
6169         {
6170                 name:    "FwdRef",
6171                 auxType: auxSym,
6172                 argLen:  0,
6173                 generic: true,
6174         },
6175         {
6176                 name:    "Unknown",
6177                 argLen:  0,
6178                 generic: true,
6179         },
6180         {
6181                 name:    "VarDef",
6182                 auxType: auxSym,
6183                 argLen:  1,
6184                 generic: true,
6185         },
6186         {
6187                 name:    "VarKill",
6188                 auxType: auxSym,
6189                 argLen:  1,
6190                 generic: true,
6191         },
6192         {
6193                 name:    "VarLive",
6194                 auxType: auxSym,
6195                 argLen:  1,
6196                 generic: true,
6197         },
6198         {
6199                 name:    "KeepAlive",
6200                 argLen:  2,
6201                 generic: true,
6202         },
6203 }
6204
6205 func (o Op) Asm() obj.As    { return opcodeTable[o].asm }
6206 func (o Op) String() string { return opcodeTable[o].name }
6207
6208 var registersAMD64 = [...]Register{
6209         {0, "AX"},
6210         {1, "CX"},
6211         {2, "DX"},
6212         {3, "BX"},
6213         {4, "SP"},
6214         {5, "BP"},
6215         {6, "SI"},
6216         {7, "DI"},
6217         {8, "R8"},
6218         {9, "R9"},
6219         {10, "R10"},
6220         {11, "R11"},
6221         {12, "R12"},
6222         {13, "R13"},
6223         {14, "R14"},
6224         {15, "R15"},
6225         {16, "X0"},
6226         {17, "X1"},
6227         {18, "X2"},
6228         {19, "X3"},
6229         {20, "X4"},
6230         {21, "X5"},
6231         {22, "X6"},
6232         {23, "X7"},
6233         {24, "X8"},
6234         {25, "X9"},
6235         {26, "X10"},
6236         {27, "X11"},
6237         {28, "X12"},
6238         {29, "X13"},
6239         {30, "X14"},
6240         {31, "X15"},
6241         {32, "SB"},
6242         {33, "FLAGS"},
6243 }
6244 var flagRegMaskAMD64 = regMask(8589934592)
6245 var registersARM = [...]Register{
6246         {0, "R0"},
6247         {1, "R1"},
6248         {2, "R2"},
6249         {3, "R3"},
6250         {4, "R4"},
6251         {5, "R5"},
6252         {6, "R6"},
6253         {7, "R7"},
6254         {8, "R8"},
6255         {9, "R9"},
6256         {10, "R10"},
6257         {11, "R11"},
6258         {12, "R12"},
6259         {13, "SP"},
6260         {14, "R14"},
6261         {15, "R15"},
6262         {16, "FLAGS"},
6263         {17, "SB"},
6264 }
6265 var flagRegMaskARM = regMask(65536)